IEC TR 61191-9:2023, which is a Technical Report, applies to electronic and electromechanical automotive circuit board assemblies and describes current best practices for dealing with electrochemical reactions like migration or corrosion and ionic contamination on the surface of a circuit board as one failure mode under humidity load. This document deals with the evaluation of materials and manufacturing processes for the manufacturing of electronic assemblies with focus on their reliability under humidity loads. The electrical operation of a device in a humid environment can trigger electrochemical reactions that can lead to short circuits and malfunctions on the assembly. In this context, a large number of terms and methods are mentioned, such as CAF (conductive anodic filament), anodic migration phenomena, dendrite growth, cathodic migration, ROSE (resistivity of solvent extract), ionic contamination, SIR (surface insulation resistance), impedance spectroscopy, etc., which are used and interpreted differently. The aim of the document is to achieve a uniform use of language and to list the possibilities and limitations of common measurement methods. The focus of the document is on the error pattern of electrochemical migration on the surface of assemblies with cathodic formation of dendrites.
Evaluation of different test methods of control units under high humidity load are not part of this document.

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IEC 62878-1:2019(E) specifies the generic requirements and test methods for device-embedded substrates. The basic test methods for printed board substrate materials and substrates themselves are specified in IEC 61189-3. This part of IEC 62878 is applicable to device-embedded substrates fabricated by use of organic base material, which includes, for example, active or passive devices, discrete components formed in the fabrication process of electronic printed boards, and sheet-formed components. The IEC 62878 series applies neither to the re-distribution layer (RDL) nor to electronic modules defined in IEC 62421.

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IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material. This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers. IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

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IEC TR 60068-3-12:2022(E) which is a Technical Report, describes the creation of temperature-time profiles (in specific envelope profiles) for reflow soldering of electronic assemblies, considering tolerances resulting from the accuracy of the measuring equipment, preparation method and specifications of the manufacturers of components, circuit boards, solder paste, etc.).
This edition includes the following significant technical changes with respect to the previous edition: a) Extended purpose Guidance is added on how to create a reflow profile considering the tolerances resulting from the accuracy of the measuring equipment, preparation method and specifications of the component manufacturers (components, PCB, solder paste, etc.). b) Distinction from existing standards The envelope profile given in this document does not represent a temperature-time profile for the qualification of materials but defines the reflow process limits for the soldering of electronic assemblies.
The schematic temperature-time-limit curves of the envelope profile are derived from generally valid findings (literature data). Additionally, tolerance considerations are given for all envelope points of the envelope profile.
In contrast to IEC TR 60068-3-12:2014, the creation of the envelope profile is not primarily linked to a concrete example. c) Subclause 8.2 presents an approach for establishing a possible temperature profile for a lead-free reflow soldering process using SnAgCu solder paste that is taken from IEC TR 60068-3-12:2014. d) Synergies with existing standards Limit values and tolerances from standards and guidelines for the qualification of materials are included in this document and are listed as examples in the references.

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This part of IEC 61189 establishes a method suitable for testing the softness of FCCL (Flexible
Copper Clad Laminate) products and related materials. This method determines the resilience
under specified conditions. The test is performed on the sample as manufactured and without
conditioning. The test does not apply to the resilience force lower than 10 mN.

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IEC PAS 61191-10:2022(E) provides guidelines which deal with the requirements for the protective coating,
its properties, as well as the application of liquid coating materials for electronic assemblies. These guidelines help control in practice the application of protective coatings from the layout to the functional test of the assembly after coating.

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IEC 60068-2-82:2019 specifies tests for the whiskering propensity of surface finishes of electric or electronic components and mechanical parts such as punched/stamped parts (for example, jumpers, electrostatic discharge protection shields, mechanical fixations, press‑fit pins and other mechanical parts used in electronic assemblies) representing the finished stage, with tin or tin-alloy finish. Changes of the physical dimensions of mould compounds, plastics and the like during the required test flow are not considered or assessed. The test methods have been developed by using a knowledge-based approach. This edition includes the following significant technical changes with respect to the previous edition: – extension of the scope of the test standard from electronic to electromechanic components and press-fit pins, which are used for assembly and interconnect technology; – significant reduction of the testing effort by a knowledge-based selection of test conditions i.e. tests not relevant for a given materials system can be omitted (see Annex D); – harmonization with JESD 201A by omission of severities M, N for temperature cycling tests; – highly reduced test duration (1 000 h instead of 4 000 h) for damp-heat test by introducing test condition at elevated humidity of 85 % R.H. and a temperature of 85 °C providing increased severity.

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IEC TR 61760-3-1:2022(E) supplements IEC 61760-3 to describe examples of solder paste supply methods, the relationship between the terminal position tolerance and the through hole diameter, and provides guidelines for the design of printed circuit boards with solder paste surface printing method, including specific examples.

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This part of IEC 61760 defines requirements for component specifications of electronic
components that are intended for usage in surface mounting technology. To this end, it
specifies a reference set of process conditions and related test conditions to be considered
when compiling component specifications.
The objective of this document is to ensure that a wide variety of SMDs can be subjected to
the same placement, mounting and subsequent processes (e.g. cleaning, inspection) during
assembly. This document defines tests and requirements that need to be part of any SMD
component's general, sectional or detail specification. In addition, this document provides
component users and manufacturers with a reference set of typical process conditions used in
surface mounting technology.
Some of the requirements for component specifications in this document are also applicable
to components with leads intended for mounting on a circuit board. Cases for which this is
appropriate are indicated in the relevant subclauses.

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IEC TR 62878-2-9:2022(E) comprises the long-term discussion among Jisso International Council (JIC) members during 1999 and 2005, when the interim agreement among all JIC members about the “concept of Jisso” as well as the “Jisso product level” for the common understanding on IEC TC 91 (electronic assembly technology) activities was reached. Further discussion on “Jisso Product Level” could be needed among the current JIC members to finalize it in the near future based on this technical report.

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This part of IEC 61189 specifies a test method to determine the decomposition temperature (Td)
of base laminate materials using thermogravimetric analysis (TGA).

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NEW!IEC 61191-1:2018 is available as IEC 61191-1:2018 RLV which contains the International Standard and its Redline version, showing all changes of the technical content compared to the previous edition.IEC 61191-1:2018 prescribes requirements for materials, methods and verification criteria for producing quality soldered interconnections and assemblies using surface mount and related assembly technologies. This part of IEC 61191 also includes recommendations for good manufacturing processes. This edition includes the following significant technical changes with respect to the previous edition: - the requirements have been updated to be compliant with the acceptance criteria in IPC‑A-610F; - the term "assembly drawing" has been changed to "assembly documentation" throughout; - references to IEC standards have been corrected; - Clause 9 was completely rewritten; - Annex B was removed because there are already procedures for circuit board assemblies.

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This document specifies two separate methods for determining the resistance of a material to wet and
dry abrasion.
It is applicable to the coated surface or surfaces of coated fabrics.
It does not apply to determining the abrasion behaviour of an uncoated surface of a coated fabric, for
which the methods for uncoated textiles described in the ISO 12947 series apply.

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IEC 60068-2-21:2021 is applicable to all electrical and electronic components whose terminations or integral mounting devices are liable to be submitted to stresses during normal assembly or handling operations and is also applicable to surface mount devices (SMDs). This seventh edition cancels and replaces the sixth edition, published in 2006, and IEC 60068‑2‑77:1999. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition:  integration of parts of IEC 60068-2-77 (see Annex X); IEC 60068-2-77 is withdrawn with the publication of this document; Annex X is added to show the correlation of the clauses and subclauses in this edition of IEC 60068-2-21 with the clauses in IEC 60068-2-21:2006 and IEC 60068-2-77:1999.

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This part of IEC 62878 specifies the requirements and evaluation methods of electrical
connectivity. It is applicable to stacked electronic modules.

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IEC 62878-2-602:2021 specifies the requirements and evaluation methods of electrical connectivity. It is applicable to stacked electronic modules.

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IEC 60068-2-21:2021 is applicable to all electrical and electronic components whose terminations or integral mounting devices are liable to be submitted to stresses during normal assembly or handling operations and is also applicable to surface mount devices (SMDs).
This seventh edition cancels and replaces the sixth edition, published in 2006, and IEC 60068‑2‑77:1999. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition:  
integration of parts of IEC 60068-2-77 (see Annex X); IEC 60068-2-77 is withdrawn with the publication of this document;
Annex X is added to show the correlation of the clauses and subclauses in this edition of IEC 60068-2-21 with the clauses in IEC 60068-2-21:2006 and IEC 60068-2-77:1999.

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IEC TR 62878-2-8:2021(E) describes a warpage control of active device embedded substrate along with parameters for determining warpage, which are useful during package assembly. Warpage results are explained using warpage driving force, resistance and neutral axis, for typical die embedded substrate, where the discrete active dies are placed in the core of substrate and interconnected to the substrate by direct Cu bonding. The same principles are applicable in other device embedded substrates. Even though the detailed structure of other device embedded substrates might be different, the origin and determination of the parameters of warpage are the same and thus the purpose of this report is to help engineers improve the warpage behaviours of their products by applying this principle.

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IEC 62878-2-602:2021 specifies the requirements and evaluation methods of electrical connectivity. It is applicable to stacked electronic modules.

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This part of IEC 61189 specifies methods for testing the characteristics of soldering paste using
fine solder particles (hereinafter referred to as solder paste).
This document is applicable to the solder paste using fine solder particle such as type 6, type 7
specified in IEC 61190-1-2 or finer particle sizes.
This type of solder paste is used for connecting wiring and components in high-density printed
circuit boards which are used in electronic or communication equipment and such, equipping
fine wiring (e.g., minimum conductor widths and minimum conductor gaps of 60 μm or less).
Test methods for the characteristics of solder paste in this document are considering the effect
of surface activation force due to the fine sized solder particles which could affect the test result
by existing test methods.

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This part of IEC 61189 is used to quantify the deleterious effects of flux residues on surface
insulation resistance (SIR) in the presence of moisture.
Interdigitated comb patterns comprising long parallel electrodes on an IPC B53 standardized
test coupon are used for the evaluation. Coupons are conditioned and measurements taken at
a high temperature and humidity. The electrodes are electrically biased during conditioning to
facilitate electrochemical reactions, as shown in Figure 1 and Figure 3.
Reference can be made to IEC TR 61189-5-506, which examines different geometry comb
patterns: 400 μm x 500 μm; 400 μm x 200 μm; and 318 μm x 318 μm.
Specifically, this method is designed to simultaneously assess:
• leakage current caused by ionized water films and electrochemical degradation of test
vehicle, (corrosion, dendritic growth);
• provide metrics that can appropriately be used for binary classification (e.g. go/no go;
pass/fail);
• compare, rank or characterize materials and processes.
This test is carried out at high humidity and heat conditions.

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IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

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IEC 62878-1:2019(E) specifies the generic requirements and test methods for device-embedded substrates. The basic test methods for printed board substrate materials and substrates themselves are specified in IEC 61189-3.
This part of IEC 62878 is applicable to device-embedded substrates fabricated by use of organic base material, which includes, for example, active or passive devices, discrete components formed in the fabrication process of electronic printed boards, and sheet-formed components.
The IEC 62878 series applies neither to the re-distribution layer (RDL) nor to electronic modules defined in IEC 62421.

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This part of IEC 61760 gives a reference set of requirements, process conditions and related
test conditions to be used when compiling specifications of electronic components that are
intended for usage in through-hole reflow soldering technology.
The object of this document is to ensure that components with leads intended for through-hole
reflow and surface mounting components can be subjected to the same placement and
mounting processes. Hereto, this document defines test and requirements that need to be part
of any component generic, sectional or detail specification, when through-hole reflow soldering
is intended.
Furthermore, this document provides component users and manufacturers with a reference set
of typical process conditions used in through-hole reflow soldering technology.

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This part of IEC 61189 is used for evaluating the changes to the surface insulation resistance
of a pre-selected material set on a representative test coupon and quantifies the deleterious
effects of improperly used materials and processes that can lead to decreases in electrical
resistance.
An assembly process involves a number of different process materials including solder flux,
solder paste, solder wire, underfill materials, adhesives, staking compounds, temporary
masking materials, cleaning solvents, conformal coatings and more. The test employs two
different test conditions of 85 °C and 85 % relative humidity (RH), preferred for a process that
includes cleaning, or 40 °C and 90 % relative humidity (RH), preferred for processes where no
cleaning is involved.
NOTE 40 °C and 93 % RH can be used as an alternative to 40 °C and 90 % RH. Additional information is provided
in 5.4 and A.5.2.
Testing is material (set) and process / equipment specific. Qualifications are to be performed
using the production intent equipment, processes and materials.

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This part of IEC 61189 specifies the reflow soldering ability test method for components
mounted on organic rigid printed boards, the reflow heat resistance test method for organic rigid
printed boards, and the reflow soldering ability test method for the lands of organic rigid printed
boards in applications using solder alloys, which are eutectic or near-eutectic tin-lead (Pb), or
lead-free alloys.
The printed boards materials for this organic rigid printed boards are epoxide woven E-glass
laminated sheets that are specified in IEC 61249-2 (all parts).
The objective of this document is to ensure the soldering ability of the solder joint and of the
lands of the printed boards. In addition, test methods are provided to ensure that the printed
boards can resist the heat load to which they are exposed during soldering.
This document covers tests Tg1, Tg2, Tg3, Tg4, Tg5, and Tg6 listed in Table 1:

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IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

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IEC TR 61191-8:2021(E) gives guidelines for dealing with voiding in surface-mount solder joints of printed board assemblies for use in automotive electronics. This technical report focuses exclusively on voids in solder joints connecting packaged electronic or electromechanical components with printed boards (PBs). Voids in other solder joints (e.g. in a joint between a silicon die and a substrate within an electronic component, solder joints of through-hole components, etc.) are not considered. The technical background for the occurrence of voids in solder joints, the potential impact of voiding on printed board assembly reliability and functionality, the investigation of voiding levels in sample- and series-production by use of X‑ray inspection as well as typical voiding levels in different types of solder joints are discussed. Recommendations for the control of voiding in series production are also given. Annex A collects typical voiding levels of components and recommendations for acceptability.

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IEC 61188-6-2:2021 describes the requirements of design and use for soldering surfaces of land pattern on circuit boards. This document includes land pattern for surface mounted components. These requirements are based on the solder joint requirements of IEC 61191‑2:2017.

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This part of IEC 61760 gives a reference set of requirements, process conditions and related test conditions to be used when compiling specifications of electronic components that are intended for usage in through-hole reflow soldering technology. The object of this document is to ensure that components with leads intended for through-hole reflow and surface mounting components can be subjected to the same placement and mounting processes. Hereto, this document defines test and requirements that need to be part of any component generic, sectional or detail specification, when through-hole reflow soldering is intended. Furthermore, this document provides component users and manufacturers with a reference set of typical process conditions used in through-hole reflow soldering technology.

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IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

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IEC 60194-1:2021 covers terms and definitions closely related with TC91 technology.
This document, together with IEC 60194-2:2017, cancel and replace IEC 60194:2015. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition:
1) exclusion of 32 general terms better served by other TCs;
2) exclusion of 47 terms no longer used by the electronic assembly industry;
3) inclusion of 14 new terms related with device embedded substrate technology;
4) inclusion of 113 synonymous terms;
5) removal of identification codes for terms and annexes.

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IEC 61188-6-2:2021 describes the requirements of design and use for soldering surfaces of land pattern on circuit boards. This document includes land pattern for surface mounted components. These requirements are based on the solder joint requirements of IEC 61191‑2:2017.

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IEC 61760-3:2021 gives a reference set of requirements, process conditions and related test conditions to be used when compiling specifications of electronic components that are intended for usage in through-hole reflow soldering technology.
The object of this document is to ensure that components with leads intended for through-hole reflow and surface mounting components can be subjected to the same placement and mounting processes. Hereto, this document defines test and requirements that need to be part of any component generic, sectional or detail specification, when through-hole reflow soldering is intended.
Furthermore, this document provides component users and manufacturers with a reference set of typical process conditions used in through-hole reflow soldering technology.
This edition includes the following significant technical changes with respect to the previous edition:
a) change position tolerance requirement (0,4 mm maximum to between 0,2 mm and 0,4 mm);
b) introduce through-hole vacant method as a solder paste supply method.

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IEC 61190-1-3:2017 prescribes the requirements and test methods for electronic grade solder alloys, for fluxed and non-fluxed bar, ribbon, powder solders and solder paste, for electronic soldering applications and for "special" electronic grade solders. For the generic specifications of solder alloys and fluxes, see ISO 9453. This document is a quality control document and is not intended to relate directly to the material's performance in the manufacturing process. This edition includes the following significant technical changes with respect to the previous edition: a) The maximum impurity level of Pb has been revised and the table of lead free solder alloys includes some additional lead free solder alloys.

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IEC TR 61188-8:2021(E) describes the configuration of part shape data of semiconductor devices and electrical components registered in the CAD library. This document mainly describes the configuration of 2D and 3D parts shape data.

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IEC 61191-2:2017(E) gives the requirements for surface mount solder connections. The requirements pertain to those assemblies that are totally surface mounted or to the surface mounted portions of those assemblies that include other related technologies (e.g. through-hole, chip mounting, terminal mounting, etc.). This edition includes the following significant technical changes with respect to the previous edition: a)   the requirements have been updated to be compliant with the acceptance criteria in IPC‑A-610F; b)   some of the terminology used in the document has been updated; c)   references to IEC standards have been corrected; d)   five termination styles have been added.

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This part of IEC 61189 is a test method designed to determine the proportion of soluble ionic
residues present upon a circuit board, electronic component or assembly. The conductivity of
the solution used to dissolve the ionic residues is measured to evaluate the level of ionic
residues.

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IEC 62090:2017(E) applies to labels on the packaging of electronic components for automatic handling in B2B processes. These labels use linear bar code and two-dimensional (2D) symbols. Labels for direct product marking and shipping labels are excluded. Labels required on the packaging of electronic components that are intended for the retail channel of distribution in B2C processes are also excluded from this document. Bar code and 2D symbol markings are used, in general, for automatic identification and automatic handling of components in electronics assembly lines. Intended applications include systems that automate the control of component packages during production, inventory and distribution. This edition includes the following significant technical changes with respect to the previous edition: a) Applicable data elements have been added. Data identifiers of those data elements are “10D”, “14D”, ”2P”, “25L”, “18V”, “V”, “J”, “3S”, “13E”, “33L” and “34L”. b) The following new informative annexes have been added: - Annex C, URL; - Annex D, Examples of data element short titles; - Annex E, Package levels for component package labels.

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IEC 60068-2-69:2017 outlines test Te/Tc, the solder bath wetting balance method and the solder globule wetting balance method to determine, quantitatively, the solderability of the terminations. Data obtained by these methods are not intended to be used as absolute quantitative data for pass–fail purposes. The procedures describe the solder bath wetting balance method and the solder globule wetting balance method. They are applicable to components and printed boards with metallic terminations and metallized solder pads. This document provides the measurement procedures for solder alloys both with and without lead (Pb). This edition includes the following significant technical changes with respect to the previous edition: - integration of IEC 60068-2-54; - inclusion of tests of printed boards; - inclusion of new component types, and updating test parameters for the whole component list; - inclusion of a new gauge R & R test protocol to ensure that the respective wetting balance equipment is correctly calibrated.

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IEC TR 61191-7:2020(E) serves as a Technical Report and provides information, how technical cleanliness can be assessed within the electronics assembly industry. Technical cleanliness concerns sources, analysis, reduction and control as well as associated risks of particulate matter, so-called foreign-object debris, on components and electronic assemblies in the electronics industry.

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IEC 62739-3:2017(E) describes the selection methodology of an appropriate evaluating test method for the erosion of the metal materials without or with surface processing intended to be used for lead-free wave soldering equipment as a solder bath and other components which are in contact with the molten solder.

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This part of IEC 61191 prescribes requirements for materials, methods and verification criteria for producing quality soldered interconnections and assemblies using surface mount and related assembly technologies. This part of IEC 61191 also includes recommendations for good manufacturing processes.

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IEC 62878-1:2019 specifies the generic requirements and test methods for device-embedded substrates. The basic test methods for printed board substrate materials and substrates themselves are specified in IEC 61189-3.
This part of IEC 62878 is applicable to device-embedded substrates fabricated by use of organic base material, which includes, for example, active or passive devices, discrete components formed in the fabrication process of electronic printed boards, and sheet-formed components.
The IEC 62878 series applies neither to the re-distribution layer (RDL) nor to electronic modules defined in IEC 62421.

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