EN 61523-2:2002

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

Berechnung von Verzögerung und Leistungsaufnahme beim Entwurf von Chips - Teil 2: Vorgezogene Berechnung der Verzögerung für CMOS-ASIC-Bibliotheken

Calcul de puissance et de délai - Partie 2: Spécification du calcul du délai de pré-implantation pour les librairies ASIC CMOS

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries (IEC 61523-2:2002)

General Information

• Status: Withdrawn
• Publication Date: 08-Aug-2002
• Withdrawal Date: 30-Jun-2005
• ICS: 35.240.50 - IT applications in industry
• Technical Committee: CLC/SR 93 - Design automation
• Drafting Committee: IEC/TC 93 - IEC_TC_93
• Parallel Committee: IEC/TC 93 - IEC_TC_93
• Current Stage: 9960 - Withdrawal effective - Withdrawal
• Start Date: 01-Oct-2011
• Completion Date: 01-Oct-2011
• Ref Project: SIST EN 61523-2:2004 - Delay and power calculation standards -- Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Standards Content (Sample)

SLOVENSKI SIST EN 61523-2:2004

STANDARD
julij 2004
Delay and power calculation standards - Part 2: Pre-layout delay calculation
specification for CMOS ASIC libraries (IEC 61523-2:2002)
ICS 31.200 Referenčna številka
SIST EN 61523-2:2004(en)
©  Standard je založil in izdal Slovenski inštitut za standardizacijo. Razmnoževanje ali kopiranje celote ali delov tega dokumenta ni dovoljeno

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EUROPEAN STANDARD EN 61523-2
NORME EUROPÉENNE
EUROPÄISCHE NORM August 2002
ICS 35.240.50
English version
Delay and power calculation standards
Part 2: Pre-layout delay calculation specification
for CMOS ASIC libraries
(IEC 61523-2:2002)
Calcul de puissance et de délai Berechnung von Verzögerung und
Partie 2 : Spécification du calcul Leistungsaufnahme beim Entwurf
du délai de pré-implantation von Chips
pour les librairies ASIC CMOS Teil 2: Vorgezogene Berechnung
(CEI 61523-2:2002) der Verzögerung
für CMOS-ASIC-Bibliotheken
(IEC 61523-2:2002)
This European Standard was approved by CENELEC on 2002-07-01. CENELEC members are bound to
comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European
Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and
notified to the Central Secretariat has the same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic,
Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Luxembourg, Malta,
Netherlands, Norway, Portugal, Slovakia, Spain, Sweden, Switzerland and United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Central Secretariat: rue de Stassart 35, B - 1050 Brussels
© 2002 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 61523-2:2002 E

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EN 61523-2:2002 - 2 -
Foreword
The text of document 93/151/FDIS, future edition 1 of IEC 61523-2, prepared by IEC TC 93, Design
automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as
EN 61523-2 on 2002-07-01.
The ASIC Library Representation Working Group of EIAL EDA Technical Committee also participated
in the preparation of this standard.
1)
This standard is a revision of the EIAJ document: ASIC Library Representation (ALR):1994.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2003-04-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2005-07-01
Annexes designated "normative" are part of the body of the standard.
Annexes designated "informative" are given for information only.
In this standard, annex ZA is normative and annexes A to F are informative.
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 61523-2:2002 was approved by CENELEC as a European
Standard without any modification.
__________

1)

Electronic Industries Association of Japan.

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- 3 - EN 61523-2:2002
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
This European Standard incorporates by dated or undated reference, provisions from other
publications. These normative references are cited at the appropriate places in the text and the
publications are listed hereafter. For dated references, subsequent amendments to or revisions of any
of these publications apply to this European Standard only when incorporated in it by amendment or
revision. For undated references the latest edition of the publication referred to applies (including
amendments).
NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant
EN/HD applies.
Publication Year Title EN/HD Year
IEEE 1481 1999 Integrated Circuit (IC) Delay and Power--
Calculation System

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INTERNATIONAL IEC
STANDARD
61523-2
First edition
2002-05
Delay and power calculation standards –
Part 2:
pre-layout delay calculation specification
for CMOS ASIC libraries
© IEC 2002 ⎯ Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or b
...