prEN IEC 63550-4:2025

Semiconductor devices - Neuromorphic devices - Part 4: Evaluation method of asymmetry in memristor devices

Halbleiterbauelemente – Neuromorphe Bauelemente -Teil 4: Bewertungsmethode für Asymmetrien in neuromorphen Memristor-Bauelementen

Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 4: Méthode d’évaluation de l’asymétrie des dispositifs à memristance

Polprevodniški elementi - Nevromorfne naprave - 4. del: Metoda ocenjevanja asimetrije v memristorskih napravah

General Information

• Status: Not Published
• Publication Date: 04-Apr-2027
• ICS: 31.080.99 - Other semiconductor devices
• Technical Committee: CLC/TC 47X - Semiconductor devices and trusted chips
• Current Stage: 4060 - Enquiry results established and sent to TC, SR, BTTF - Enquiry
• Start Date: 28-Nov-2025
• Completion Date: 28-Nov-2025
• Ref Project: oSIST prEN IEC 63550-4:2025 - Semiconductor devices - Neuromorphic devices - Part 4: Evaluation method of asymmetry in memristor devices

Standards Content (Sample)

SLOVENSKI STANDARD
01-november-2025
Polprevodniški elementi - Nevromorfne naprave - 4. del: Metoda ocenjevanja
asimetrije v memristorskih napravah
Semiconductor devices - Neuromorphic devices - Part 4: Evaluation method of
asymmetry in memristor devices
Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 4: Méthode
d’évaluation de l’asymétrie des dispositifs à memristance
Ta slovenski standard je istoveten z: prEN IEC 63550-4:2025
ICS:
31.080.99 Drugi polprevodniški elementi Other semiconductor devices
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47/2940/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 63550-4 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2025-09-05 2025-11-28
SUPERSEDES DOCUMENTS:
47/2874/CD, 47/2928/CC
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
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TITLE:
Semiconductor devices - Neuromorphic devices - Part 4: Evaluation method of asymmetry in
memristor devices
PROPOSED STABILITY DATE: 2029
NOTE FROM TC/SC OFFICERS:
download this electronic file, to make a copy and to print out the content for the sole purpose of preparing National
Committee positions. You may not copy or "mirror" the file or printed version of the document, or any part of it, for
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IEC CDV 63550-4 © IEC 2025
1 CONTENTS
3 FOREWORD . 3
4 1 Scope . 5
5 2 Normative references . 5
6 3 Terms and definitions . 5
7 4 Device under test (DUT) . 6
8 5 Requirements of test apparatus and environment . 7
9 5.1 Test apparatus . 7
10 5.1.1 Overall system . 7
11 5.1.2 Semiconductor parameter analyzer . 7
12 5.1.3 Probe station . 7
13 5.2 Test environment . 8
14 6 Test method . 8
15 6.1 Test process . 8
16 6.2 Data processing and evaluation . 9
17 6.2.1 Evaluation method of asymmetry . 9
18 6.2.2 Calculation of asymmetry, 𝝈𝐝𝟐𝐝, and 𝝈𝐜𝟐𝐜 . 12
19 7 Test report . 13
20 Annex A (informative) Some examples for asymmetry evaluation . 14
21 A.1 Asymmetry calculated from asymmetric nonlinearity model . 14
22 A.2 Asymmetry calculated from symmetric nonlinearity model . 14
23 Bibliography . 15
25 Figure 1 – Block Diagram of the measurement setup of a memristor device . 7
26 Figure 2 – The flow chart of asymmetry test in memristor devices . 9
27 Figure 3 – The asymmetric nonlinearity model . 11
28 Figure 4 – The symmetric nonlinearity model . 12
29 Figure A.1 – Exemplary asymmetric nonlinear conductance change. 14
30 Figure A.2 – Exemplary symmetric nonlinear conductance change . 14
IEC CDV 63550-4 © IEC 2025
35 INTERNATIONAL ELECTROTECHNICAL COMMISSION
36 ____________
38 Semiconductor devices - Neuromorphic devices -
40 Part 4: Evaluation method of asymmetry in memristor devices
42 FOREWORD
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71 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
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78 not be held responsible for identifying any or all such patent rights.
79 IEC 63550-4 has been prepared by IEC technical subcommittee 47: Semiconductor devices. It
80 is an International Standard.
81 The text of this International Standard is based on the following documents:
NP Report on voting
47/2813/NP 47/2837/RVN
83 Full information on the voting for its approval can be found in the report on voting indicated in
84 the above table.
85 The language used for the development of this International Standard is English.
IEC CDV 63550-4 © IEC 2025
86 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
87 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement available
88 at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
89 described in greater detail at www.iec.ch/publications.
90 A list of all parts in the IEC 63550 series, published under the general title Semiconductor
91 devices – Neuromorphic devices, can be found on the IEC website.
92 The committee has decided that the contents of this document will remain unchanged until the
93 stability date indicated on the IEC website under webstore.iec.ch in the data related to the
94 specific document. At this date, the document will be
95 • reconfirmed,
96 • withdrawn,
97 • replaced by a revised edition, or
98 • amended.
IEC CDV 63550-4 © IEC 2025
101 Semiconductor devices - Neuromorphic devices -
103 Part 4: Evaluation method of asymmetry in memristor devices
105 1 Scope
106 This part of IEC 63550-4 focuses on evaluating asymmetry characteristics, which play a crucial
107 role in memristors handling of imbalanced switching behaviours in neuromorphic operations,
108 requiring distinct characterization methods apart from linearity assessments. The test methods
109 of asymmetry in this international standard include asymmetry, cycle-to-cycle variation (𝜎 ) of
c2c
110 asymmetry and device-to-device variation (𝜎 ) of asymmetry. This document applies to all
d2d
111 two-terminal neuromorphic memristor devices, regardless of the underlying mechanism.
112 2 Normative references
113 There are no normative references in this document.
114 3 Terms and definitions
115 For the purpose of this document, the following terms and definitions apply.
116 ISO and IEC maintain terminological databases for use in standardization at the following
117 addresses:
118 • IEC Electropedia: available at http://www.electropedia.org/
119 • ISO Online browsing platform: available at http://www.iso.org/obp
120 3.1
121 pre-synaptic voltage
122 Vpre
123 bias applied to the pre-synaptic terminal of the memristor devices.
124 3.2
125 post-synaptic voltage
126 Vpost
127 bias applied to the post-synaptic terminal of the memristor devices
128 3.3
129 memristor
130 nonlinear two-terminal electrical component that limits or regulate the flow of electrical current
131 in a circuit and remembers the amount of charge that has previously flowed through it
132 3.4
133 forming voltage
134 Vform
135 high voltage applied across the active layer to induce defects within the active layer to form a
136 filament or conduction path initially.
137 3.5
138 memristor programming voltage
139 V
p
140 voltage applied to the pre-synaptic terminal of memristor to change its resistance state.
IEC CDV 63550-4 © IEC 2025
141 3.6
142 set voltage
143 Vset
144 bias applied to switch a memristor to a low resistance state.
145 3.7
146 reset voltage
147 V
reset
148 bias applied to switch a memristor to a high resistance state.
149 3.8
150 step voltage
151 V
step
152 step size of voltage increments during gradual voltage application.
153 3.9
154 read voltage
155 Vread
156 specific voltage for measuring the resistance of memristor.
157 3.10
158 read current
159 Iread
160 specific current value at VRead of memristor.
161 3.11
162 resistance of memristor
163 R
read
164 resistance value at VRead, defined by the following formula.
𝑽
𝐫𝐞𝐚𝐝
165 𝑹 =
𝐑𝐞𝐚𝐝
𝑰
𝐫𝐞𝐚𝐝
...