EN 62418:2010
(Main)Semiconductor devices - Metallization stress void test
Semiconductor devices - Metallization stress void test
IEC 62418:2010 describes a method of metallization stress void test and associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.
Halbleiterbauelemente - Prüfverfahren zur Metallisierungs-Stressmigration
Dispositifs à semi-conducteurs - Essai sur les cavités dues aux contraintes de la métallisation
La CEI 62418:2010 décrit une méthode d'essai sur les cavités dues aux contraintes générées par la métallisation et les critères associés. Elle s'applique à la métallisation à l'aluminium (Al) ou au cuivre (Cu).
Polprevodniški elementi - Preskus brez upoštevanja obremenitve metalizacije (IEC 62418:2010)
Ta mednarodni standard opisuje metodo preskusa brez upoštevanja obremenitve metalizacije in povezana merila. Velja za metalizacijo z aluminijem (Al) ali bakrom (Cu). Ta standard velja za preiskavo zanesljivosti in kvalifikacijo polprevodniškega procesa.
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
01-september-2010
Polprevodniški elementi - Preskus brez upoštevanja obremenitve metalizacije (IEC
62418:2010)
Semiconductor devices - Metallization stress void test (IEC 62418:2010)
Halbleiterbauelemente - Prüfverfahren zur Metallisierungs-Stressmigration (IEC
62418:2010)
Dispositifs à semi-conducteurs - Essai sur les cavités dues aux contraintes de la
métallisation (CEI 62418:2010)
Ta slovenski standard je istoveten z: EN 62418:2010
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
EUROPEAN STANDARD
EN 62418
NORME EUROPÉENNE
July 2010
EUROPÄISCHE NORM
ICS 31.080
English version
Semiconductor devices -
Metallization stress void test
(IEC 62418:2010)
Dispositifs à semi-conducteurs - Halbleiterbauelemente -
Essai sur les cavités dues aux contraintes Prüfverfahren zur Metallisierungs-
de la métallisation Stressmigration
(CEI 62418:2010) (IEC 62418:2010)
This European Standard was approved by CENELEC on 2010-07-01. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,
the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia,
Spain, Sweden, Switzerland and the United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Management Centre: Avenue Marnix 17, B - 1000 Brussels
© 2010 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 62418:2010 E
Foreword
The text of document 47/2043/FDIS, future edition 1 of IEC 62418, prepared by IEC TC 47,
Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 62418 on 2010-07-01.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent
rights.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
(dop) 2011-04-01
national standard or by endorsement
– latest date by which the national standards conflicting
(dow) 2013-07-01
with the EN have to be withdrawn
__________
Endorsement notice
The text of the International Standard IEC 62418:2010 was approved by CENELEC as a European
Standard without any modification.
__________
IEC 62418 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Metallization stress void test
Dispositifs à semiconducteurs – Essai sur les cavités dues aux contraintes
de la métallisation
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
Q
CODE PRIX
ICS 31.080 ISBN 978-2-88910-697-4
– 2 – 62418 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Test equipment.5
3 Test structure .5
3.1 Test structure patterns .5
3.2 Line pattern.5
3.3 Via chain pattern .5
3.3.1 Pattern types .5
3.3.2 Pattern for aluminium (Al) process.5
3.3.3 Pattern for copper (Cu) process.6
4 Stress temperature.6
5 Procedure .6
5.1 Stress void evaluation methods .6
5.2 Resistance measurement method.6
5.3 Inspection method .7
6 Failure criteria .8
6.1 Resistance method.8
6.2 Inspection method .8
7 Data interpretation and lifetime extrapolation (resistance change method).8
8 Items to be specified and reported.9
8.1 Resistance change method .9
8.2 Inspection method .10
Annex A (informative) Stress migration mechanism .11
Annex B (informative) Technology-dependent factors for aluminium .13
Annex C (informative) Technology-dependent factors for copper .14
Annex D (informative) Precautions.15
Bibliography.17
Figure A.1 – Schematic representation of the stress-void formation mechanism in Al.11
Table 1 – Void classification .7
62418 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
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6) All users should ensure that they have the latest edition of this publication.
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62418 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2043/FDIS 47/2050/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
– 4 – 62418 © IEC:2010
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
62418 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST
1 Scope
This International Standard describes a method of metallization stress void test and
associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.
This standard is applicable for reliability investigation and qualification of semiconductor
process.
2 Test equipment
A calibrated hot chuck or thermal chamber is required to subject the wafers or packaged test
structures to the specified temperature (±5 °C) for the specified time. For resistance
measurements dedicated equipment is needed. For void inspection deprocessing equipment
is required to remove the scratch protection layer. The inspections are performed with a
scanning electron microscope (SEM).
3 Test structure
3.1 Test structure patterns
Test structures shall be used for all metal layers which have to be inspected and several
different types of structure may be used. The following two types of test structures are
applicable for this test standard.
NOTE For metallization without refractory shunt layers reflective notching at steps can occur in test structures
with underlying topography, which will therefore tend to indicate a relatively worse stress-voiding behaviour.
3.2 Line pattern
Parallel lines which are patterned at the minimum linewidth allowed by design form an
appropriate test structure. Unless otherwise specified a minimum length of 500 μm and a total
length of 1 cm to 1 000 cm are recommended condition. Single long isolated lines are
recommended because stress voiding is often sensitive to line-to-line separation.
NOTE 1 Narrow lines are susceptible for stress voiding because the stress in the metal is typically higher in
narrower lines than in wider lines.
NOTE 2 The line length should be sufficient to insure that void nucleation sites will exist.
3.3 Via chain pattern
3.3.1 Pattern types
A via chain pattern is applicable as a test structure. For technology investigations a Kelvin-
pattern for four-point measurements may also be used.
3.3.2 Pattern for aluminium (Al) process
Via chains need to consist of a pattern of vias connected by minimum linewidth. The
recommended number of vias is between 1 000 and 100 000. It is recommended to use
isolated and long minimum linewidths.
– 6 – 62418 © IEC:2010
3.3.3 Pattern for copper (Cu) process
For Cu metallization the following structures are applicabl
...
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