ETSI TS 103 713 V15.1.0 (2020-02)

Smart Secure Platform (SSP); SPI interface (Release 15)

RTS/SCP-T103713vf10

General Information

• Status: Published
• Publication Date: 02-Feb-2020
• Technical Committee: SET TEC - SET-TEC
• Current Stage: 12 - Completion
• Due Date: 12-Feb-2020
• Completion Date: 03-Feb-2020

Standards Content (Sample)

TECHNICAL SPECIFICATION
Smart Secure Platform (SSP);
SPI interface
(Release 15)
Release 15 2 ETSI TS 103 713 V15.1.0 (2020-02)

Reference
RTS/SCP-T103713vf10
Keywords
M2M, MFF
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ETSI
Release 15 3 ETSI TS 103 713 V15.1.0 (2020-02)
Contents
Intellectual Property Rights . 5
Foreword . 5
Modal verbs terminology . 5
1 Scope . 6
2 References . 6
2.1 Normative references . 6
2.2 Informative references . 6
3 Definition of terms, symbols and abbreviations . 7
3.1 Terms . 7
3.2 Symbols . 7
3.3 Abbreviations . 7
4 Introduction . 8
5 SCL Under-Layers Protocol Stack . 8
6 Electrical interfaces . 9
6.1 Introduction . 9
6.2 Physical interface with 5 signals . 9
6.3 Physical interface with 4 signals . 10
6.4 Electrical characteristics . 11
6.4.1 DC characteristics . 11
6.4.2 Data transfer mode, AC characteristics . 11
7 Data Link Layer . 13
7.1 Overview . 13
7.2 MAC Layer . 13
7.2.1 Overview . 13
7.2.2 Timing . 13
7.2.2.1 Timing definitions . 13
7.2.2.2 T1 = Slave Ready Time. 13
7.2.2.3 T2 = Slave Request Time . 13
7.2.3 5 signals MAC layer . 14
7.2.3.1 Initiation of the data transfer from the master . 14
7.2.3.2 Initiation of the data transfer from the slave . 14
7.2.3.3 Simultaneous initiation of a data transfer from both master and slave . 15
7.2.3.4 MAC activation . 15
7.2.3.5 MAC deactivation . 16
7.2.4 4 signals MAC layer . 16
7.2.4.1 Introduction . 16
7.2.4.2 Initiation of the data transfer from the master . 16
7.2.4.3 Initiation of the data transfer from the slave . 16
7.2.4.4 Simultaneous initiation of the data transfer from both master and slave. 17
7.2.4.5 Slave-driven Flow Control . 18
7.2.4.6 MAC activation . 18
7.2.4.7 MAC deactivation . 18
7.3 Link Layer Frame . 19
7.3.1 Overview . 19
7.3.2 Frames generation and transfer rules . 20
7.3.3 Data transfer cases . 21
7.4 LLC layers . 22
7.5 Interworking of the LLC layers . 23
7.6 MCT LLC definition . 24
7.6.1 MCT LPDU structure . 24
7.6.2 MCT_DATA from master . 24
7.6.3 MCT_DATA from slave . 25
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7.6.4 MCT activation procedure . 26
7.7 SHDLC LLC definition . 26
7.7.1 SHDLC overview . 26
7.7.2 Endpoints . 26
7.7.3 Flow control . 27
7.7.3.1 Overview . 27
7.7.3.2 Flow control based on SHDLC . 27
7.8 Power management . 27
7.8.1 Power saving mode . 27
7.8.2 Conditions for entering power saving mode . 27
7.8.2.1 Slave entering power saving mode . 27
7.8.2.2 Master entering power saving mode . 28
7.8.3 Resuming from power saving mode . 28
7.8.3.1 Resuming the slave from power saving mode . 28
7.8.3.2 Resuming the master from power saving mode . 28
Annex A (informative): Change history . 30
History . 31

ETSI
Release 15 5 ETSI TS 103 713 V15.1.0 (2020-02)
Intellectual Property Rights
Essential patents
IPRs essential or potentially essential to normative deliverables may have been declared to ETSI. The information
pertaining to these essential IPRs, if any, is publicly available for ETSI members and non-members, and can be found
in ETSI SR 000 314: "Intellectual Property Rights (IPRs); Essential, or potentially Essential, IPRs notified to ETSI in
respect of ETSI standards", which is available from the ETSI Secretariat. Latest updates are available on the ETSI Web
server (https://ipr.etsi.org/).
Pursuant to the ETSI IPR Policy, no investigation, including IPR searches, has been carried out by ETSI. No guarantee
can be given as to the existence of other IPRs not referenced in ETSI SR 000 314 (or the updates on the ETSI Web
server) which are, or may be, or may become, essential to the present document.
Trademarks
The present document may include trademarks and/or tradenames which are asserted and/or registered by their owners.
ETSI claims no ownership of these except for any which are indicated as being the property of ETSI, and conveys no
right to use or reproduce any trademark and/or tradename. Mention of those trademarks in the present document does
not constitute an endorsement by ETSI of products, services or organizations associated with those trademarks.
Foreword
This Technical Specification (TS) has been produced by ETSI Technical Committee Smart Card Platform (SCP).
The contents of the present document are subject to continuing work within TC SCP and may change following formal
TC SCP approval. If TC SCP modifies the contents of the present document, it will then be republished by ETSI with
an identifying change of release date and an increase in version number as follows:
Version x.y.z
where:
x the first digit:
0 early working draft;
1 presented to TC SCP for information;
2 presented to TC SCP for approval;
3 or greater indicates TC SCP approved document under change control.
y the second digit is incremented for all changes of substance, i.e. technical enhancements, corrections,
updates, etc.
z the third digit is incremented when editorial only changes have been incorporated in the document.
Modal verbs terminology
In the present document "shall", "shall not", "should", "should not", "may", "need not", "will", "will not", "can" and
"cannot" are to be interpreted as described in clause 3.2 of the ETSI Drafting Rules (Verbal forms for the expression of
provisions).
"must" and "must not" are NOT allowed in ETSI deliverables except when used in direct citation.
ETSI
Release 15 6 ETSI TS 103 713 V15.1.0 (2020-02)
1 Scope
The present document describes the SPI interface for the communication of an SSP, as defined in ETSI
TS 103 666-1 [1] using the SCL protocol.
2 References
2.1 Normative references
References are either specific (identified by date of publication and/or edition number or version number) or
non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the
referenced document (including any amendments) applies.
• In the case of a reference to a TC SCP document, a non-specific reference implicitly refers to the latest version
of that document in the same Release as the present document.
Referenced documents which are not found to be publicly available in the expected location might be found at
https://docbox.etsi.org/Reference/.
NOTE: While any hyperlinks included in this clause were valid at the time of publication, ETSI cannot guarantee
their long term validity.
The following referenced documents are necessary for the application of the present document.
[1] ETSI TS 103 666-1: "Smart Secure Platform (SSP); Part 1: General characteristics".
[2] ETSI TS 102 613: "Smart Cards; UICC - Contactless Front-end (CLF) Interface; Physical and data
link layer characteristics".
[3] ISO/IEC 13239: "Information Technology -- Telecommunications and information exchange
between systems -- High-level Data Link Control (HDLC) procedures".
2.2 Informative references
References are either specific (identified by date of publication and/or edition number or version number) or
non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the
referenced document (including any amendments) applies.
• In the case of a reference to a TC SCP document, a non-specific reference implicitly refers to the latest version
of that document in the same Release as the present document.
NOTE: While any hyperlinks included in this clause were valid at the time of publication, ETSI cannot guarantee
their long term validity.
The following referenced documents are not necessary for the application of the present document but they assist the
user with regard to a particular subject area.
[i.1] ETSI TR 102 216: "Smart cards; Vocabulary for Smart Card Platform specifications".
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3 Definition of terms, symbols and abbreviations
3.1 Terms
For the purposes of the present document, the terms given in ETSI TR 102 216 [i.1] and the following apply:
data transfer: information exchange during an SPI access between the master and the slave with SPI_MISO driven by
the slave and SPI_MOSI driven by the master while the master is toggling the SPI_CLK signal
flow control: mechanism of the Data Link Layer that consists of methods applied by the transmitter in order to send at
any time a number of logical data units that can be accepted by the receiver
frame: link layer data structure consisting of a prologue or frame header, payload and epilogue or trailer usually
containing the CRC bytes
MAC access request: request from the slave to the master for a data transfer, i.e. a MAC phase initiated by the slave
MAC phase: initiation of a data transfer by the master and/or request for a data transfer by the slave
SPI access: SPI_NSS assertion by the master, if not already asserted in the MAC phase, followed by SPI_CLK start for
transferring a certain number of bytes according to the SPI master configuration
NOTE: The number of bytes transferred during an SPI access is always the same in both directions on SPI_MISO
and SPI_MOSI and is also referred to as access length.
window size: maximum number of logical data units that can be sent from the transmitter to the receiver without any
link layer acknowledgements for any of these data units
window size slot: fixed space used by the slave in the receive buffer for the logical data units.
NOTE: The length of a window size slot equals the Data Link Layer MTU.
3.2 Symbols
Void.
3.3 Abbreviations
For the purposes of the present document, the following abbreviations apply:
AC Alternating Current
ACT Activation
CLF ContactLess Frontend
CMD Command
CPHA Clock Phase
CPOL Clock Polarity
CRC Cyclic Redundancy Check
DC Direct Current
DLL Data Link Layer
FIFO First In, First Out
IO Input/Output
IOH High Output Current (Output current corresponding to VOH)
IOL Low Output Current (Output current corresponding to VOL)
LLC Logical Link Control
LPDU Link Protocol Data Unit
MAC Medium Access Control
MCT MAC aCTivation
MISO Master Input Slave Output
MOSI Master Output Slave Input
MTU Maximum Transmission Unit
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NSD Non-Significant Data
OD Open Drain
RFU Reserved for Future Use
SCL SSP Common Layer
SHDLC Simplified High Level Data Link Control
SPI Serial Peripheral Interface
SSP Smart Secure Platform
SWP Single Wire Protocol
NOTE: Defined in ETSI TS 102 613 [2].
VDD Supply Voltage
VIH High Input Voltage (Input Voltage for High Logic Level)
VIL Low Input Voltage (Input Voltage for Low Logic Level)
VOH High Output Voltage (Output Voltage for High Logic Level)
VOL Low Output Voltage (Output Voltage for Low Logic Level)
4 Introduction
The Serial Peripheral Interface (SPI) is a serial synchronous full-duplex communication interface between a single
master and one or more slaves present on the same SPI bus, each slave being selected at one time by a dedicated
SPI_NSS signal. This clause defines the physical, MAC and data link layers for the SPI interface.
In this clause the terms master and slave refer respectively to the terms master SPI and slave SPI.
5 SCL Under-Layers Protocol Stack
Figure 5.1 illustrates the protocol stack below the SCL supporting the SPI interface.

Figure 5.1: Protocol stack for SPI Interface
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6 Electrical interfaces
6.1 Introduction
In the clauses below, different implementations of SPI interface are defined. These implementations allow bi-directional
communication and the possibility for the slave to initiate communication with the master when it has data available
thus avoiding the necessity for continuous polling to be performed by master.
Slave may initiate communication to send a command without a prior command from master.
6.2 Physical interface with 5 signals
Figure 6.1 illustrates the SPI electrical interface using 5 signals.

Figure 6.1: SPI electrical interface with 5 signals
This SPI interface describes two sets of signals:
• The generic and legacy SPI interface using the 4 signals: SPI_MOSI (Master Output Slave Input), SPI_MISO
(Master Input Slave Output), SPI_CLK (clock) and the SPI_NSS signal used for the selection of a Slave
Endpoint among N slaves sharing the same bus. SPI_MISO, SPI_MOSI and SPI_CLK can be shared between
several SPI slaves present on the same SPI bus.
• The SPI_INT signal allows the slave to initiate a MAC access request in order to notify the master to start a
data transfer.
SPI_INT signal is considered active or asserted at high voltage level.
SPI_NSS is considered active or asserted at low voltage level.
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6.3 Physical interface with 4 signals
Figure 6.2 illustrates the SPI interface using 4 signals, bi-directional SPI_NSS.
MAST ER SLAVE
SP I_MISO
SP I_MOS I
SP I_C LK
VDD
R
SS_MI SS_SI
SP I_NS S
SS _MO SS_SO
VSS
VSS
Figure 6.2: SPI electrical interface with 4 signals, bi-directional SPI_NSS
The SPI interface with 4 signals describes two sets of signals:
• The three generic and legacy SPI signals as SPI_MOSI (Master Output Slave Input), SPI_MISO (Master Input
Slave Output) and SPI_CLK (clock). These signals can be shared between several SPI slaves as a bus.
• The SPI_NSS (Negative Slave Select) signal used for the selection of a slave endpoint among N slaves sharing
the same bus and for the slave to initiate a MAC access request to notify the master to initiate a data transfer.
SPI_NSS is considered active or asserted at low voltage level. SPI_NSS requires a bidirectional IO implementing an
Open Drain (OD) interface for both master and slave. This configuration allows driving the SPI_NSS signal to low
voltage level by both master and slave without electrical contention.
A pull-up resistor allows to keep SPI_NSS at high state level (i.e. idle state) when SS_MO and SS_SO are not asserted.
The SPI_NSS signal is at low state when either SS_MO or SS_SO are asserted.
NOTE: Despite the current industry de-facto SPI specification which defines SPI_NSS signal as unidirectional,
driven by the master, in the present document the SPI_NSS in the 4 signals configuration is bidirectional.
Table 6.1: Definition of the signals
Signal Description
SS_MO Internal master output signal for SPI_NSS assertion. SS_MO is at high state level for generating a
SPI_NSS signal assertion (i.e. low level state)
SS_SO Internal slave output signal for SPI_NSS assertion. SS_SO is at high state level for generating a SPI_NSS
signal assertion (i.e. low level state)
SS_MI Internal master input signal indicating SPI_NSS status. SS_MI is at high state level when the SPI_NSS
signal is not asserted
SS_SI Internal slave input signal indicating SPI_NSS status. SS_SI is at high state level when the SPI_NSS signal
is not asserted
SPI_NSS SPI_NSS signal: low state level when asserted

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6.4 Electrical characteristics
6.4.1 DC characteristics
The SPI Electrical specification interface shall be defined for VDD operational voltage classes B and C as defined in
ETSI TS 103 666-1 [1], clause 6.2.2.3.
Table 6.2: DC characteristics for operational voltage class B
Parameter Symbol Min Max Unit Note/Test condition
Input high voltage VIH 0,7 × VDD VDD + 0,5 V
Input low voltage VIL -0,5 0,3 × VDD V
Output high voltage VOH 0,9 × VDD V IOH = -100 uA
Output low voltage VOL 0,1 × VDD V IOL = 1,0 mA
SPI_NSS Low Level Output current IOL -1 - mA VOL = 0,3 V
(see note)
Maximal SPI_NSS line capacitance Cl - 20 pF
(see note)
NOTE: Applicable for the physical interface with 4 signals.

Table 6.3: DC characteristics for operational voltage class C
Parameter Symbol Min Max Unit Note/Test condition
Input high voltage VIH 0,7 × VDD VDD + 0,3 V
Input low voltage VIL -0,3 0,3 × VDD V
Output high voltage VOH 0,9 × VDD V IOH = -100 uA
Output low voltage VOL 0,1 × VDD V IOL = 1,0 mA
SPI_NSS Low Level Output current IOL -1 - mA VOL = 0,3 V
(see note)
Maximal SPI_NSS line capacitance Cl - 20 pF
(see note)
NOTE: Applicable for the physical interface with 4 signals.

The value of the resistor R in figure 6.2 shall be selected for a resultant maximum current lower than or equal to the
minimum between the absolute IOL values of the master and the slave.
6.4.2 Data transfer mode, AC characteristics
The SPI interface shall implement the SPI mode 0 according to the industry de-facto SPI specification.
SPI mode 0 is determined by CPOL = 0 and CPHA = 0 where:
• CPOL: defines the SPI_CLK idle state.
• CPOL = 0 implies that the SPI_CLK is at input low voltage while it is idle.
• CPHA: defines the data sampling time.
• CPHA = 0 implies that data sampling is done on the rising edges of the SPI_CLK for both SPI_MISO and
SPI_MOSI.
SPI_NSS is considered active or asserted at low voltage level.
Data availability timings with reference to SPI_CLK are shown in figure 6.3.
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Release 15 12 ETSI TS 103 713 V15.1.0 (2020-02)

Figure 6.3: SPI timing diagram
Table 6.4: AC characteristics for 1,8 V and 3,3 V (SPI Slave, Mode 0: CPOL = 0 and CPHA = 0)
Symbol Definition Value
(MIN values unless MAX specified)
Max SPI_CLK is specified by Slave
fCLK SPI_CLK frequency
at initialization in MCT_READY
tCLKL SPI_CLK low time 0,45 × tCLK
tCLKH SPI_CLK high time 0,45 × tCLK
tSU Data setup time to clock rising edge 5 ns
tH SPI_MOSI hold time/Data hold time to clock rising edge 3 ns
tHO SPI_MISO hold time/Output hold time to clock falling edge 0 ns
tCSS SPI_CS# setup time (1,8 V) 63 ns
tCSS SPI_CS# setup time (3,3 V) 33 ns
tCSH Hold time clock falling edge to SPI_CS# inactive 0,5 × tCLK
tCS SPI_CS# inactive time (1,8 V) 60 ns
tCS SPI_CS# inactive time (3,3 V) 30 ns
tCSV SPI_MISO valid delay time from SPI_CS# active (1,8 V) 58 ns (MAX)
tCSV SPI_MISO valid delay time from SPI_CS# active (3,3 V) 28 ns (MAX)
0 ns (MIN)
tV SPI_MISO valid delay time from clock falling edge
0,7 × tCLKL (MAX)
0 ns (MIN)
tCSDO SPI_MISO Output disable time from SPI_CS# inactive (1,8 V)
60 ns (MAX)
0 ns (MIN)
tCSDO SPI_MISO Output disable time from SPI_CS# inactive (3,3 V)
30 ns (MAX)
The values indicated in table 6.4 are reference values for generic SPI slaves. If the concrete slave device supports better
timing parameters, a system design may choose to configure the master for these timing values in order to achieve
better performance.
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7 Data Link Layer
7.1 Overview
Clause 9.1 in ETSI TS 102 613 [2] shall apply.
7.2 MAC Layer
7.2.1 Overview
The MAC phase is the initial handshake phase between SPI master and SPI slave followed by SPI data transfer phase.
7.2.2 Timing
7.2.2.1 Timing definitions
Table 7.1 describes the timing parameters of the MAC layer. In addition to these MAC timings, the timing requirements
listed in AC electrical characteristics shall apply for all MAC diagrams in the following clauses.
Table 7.1: MAC timing parameters
Symbol Definition Value (min)/ Description
Reference
MAC phase time prior to data transfer start.
Reported in
T1 Slave Ready Time This time is needed for the SPI slave to be ready for the
MCT_READY
data transfer and is reported in MCT_READY.
T2 Slave Request Time 1 μs SPI_NSS or SPI_IRQ assertion min pulse width.
Time from SPI_NSS assertion by master for slave
Slave Resume Time from Reported in resume to data transfer start.
T3
power saving mode MCT_READY T3 value shall be used by master in MAC phase instead
of T1 when the slave is in power saving mode.

7.2.2.2 T1 = Slave Ready Time
T1 is the MAC phase time required by the slave to get configured and enabled at the end of the MAC phase, ready for
the data transfer phase start (i.e. when the SPI_CLK can be started by master).
T1 is defined from the leading edge of the SPI_NSS or SPI_INT assertion by either master or slave to the data transfer
phase start.
The data transfer phase at the end of T1 is started by master by asserting SPI_NSS, if not already asserted depending on
the prior MAC phase, followed by the SPI_CLK start.
T1 is slave implementation dependant.
T1 is determined by the slave and includes T2 and any slave-specific internal latencies. Slave shall provide a T1 value
that covers the worst–case time it needs between the moment of sampling SPI_NSS to the time when slave becomes
ready for the data transfer.
Master shall allow at least the time T1 requested by slave between the start of the MAC phase initiated by either master
or slave and the point in time when the data transfer phase starts. Master may use a higher value than T1, and it may
vary T1 from one MAC phase to another.
7.2.2.3 T2 = Slave Request Time
T2 is the duration of an SPI_NSS or SPI_INT pulse generated by the slave for a MAC access request.
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Release 15 14 ETSI TS 103 713 V15.1.0 (2020-02)
The minimum value of T2 is 1 μs.
In order to sense the interrupts originating either from slave SPI_NSS or SPI_INT assertion, the master shall be
configured for edge-triggered interrupts.
NOTE: The leading edges of the MAC access request signals of the slave should assert internal interrupt of the
master.
7.2.2.4 T3 = Slave resume time from power saving mode
T3 is the slave resume time from power saving mode. It is slave implementation dependant. Slave reports at
initialization in MCT_READY the minimum value of T3 required for slave to become ready for SPI access. Whenever
master needs to resume the slave from power saving mode it should use during the MAC phase at least the time T3
instead of the MAC SLAVE_READY_TIME T1.
7.2.3 5 signals MAC layer
7.2.3.1 Initiation of the data transfer from the master
In this case at the start of a MAC phase master asserts the SPI_NSS and slave asserts the SPI_INT for making a MAC
access request.
Figure 7.1 illustrates the initiation of the data transfer by the master.

Figure 7.1: Initiation of the data transfer from the Master
The master shall run the following procedure:
1) Master asserts SPI_NSS then goes to the step 2.
2) Master waits for min T1 seconds then goes to the step 3. In use-cases when it is certain slave is not expected to
initiate a MAC access request by SPI_INT assertion (e.g. at first access during SPI initialization) master may
skip this step.
3) Master starts the bidirectional data transfer by toggling the SPI_CLK signal.
4) Master de-asserts SPI_NSS after data transfer completion i.e. SPI_CLK stopped.
7.2.3.2 Initiation of the data transfer from the slave
Figure 7.2 illustrates the initiation by slave of a MAC access request for a data transfer to be performed by the master.
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Release 15 15 ETSI TS 103 713 V15.1.0 (2020-02)

Figure 7.2: Initiation of the data transfer from the slave
The Slave runs the following procedure:
1) If the SPI_NSS signal is at the high level state by reading SPI_NSS_SI then the slave goes to the step 2.
2) The Slave asserts SPI_INT by generating an SPI_INT pulse with a minimum width of T2 seconds then goes to
the step 3. Master will generate an SPI access as a consequence of the SPI_INT assertion by slave.
3) Slave configures the SPI block and waits for data transfer from the master.
4) Master starts data transfer at a time greater than T1 following the leading edge of SPI_INT by asserting
SPI_NSS and then starts SPI_CLK. At data transfer completion master enters step 5.
5) After data transfer completion and SPI_CLK stop, the master de-asserts SPI_NSS.
7.2.3.3 Simultaneous initiation of a data transfer from both master and slave
Figure 7.3 illustrates a simultaneous initiation from the master and the slave.
T
DATA TRANSFER
T
SPI_NSS
SPI_INT
Figure 7.3: Simultaneous initiation of the data transfer from both master and slave
Both endpoints request a data transfer and run simultaneously their respective procedures. From the master perspective
the resulting procedure is equivalent to the initiation from the master.
Slave makes a MAC access request by asserting SPI_INT according to the procedure described in clause 7.2.3.2 and
waits for master to generate the access for data transfer.
The gap time T1 - T2 shall be long enough for the slave to prepare the SPI block for the data transfer.
7.2.3.4 MAC activation
The MAC activation procedure shall be the following if the SPI bus is not shared with other peripheral:
• The master shall set the SPI_MOSI to high impedance and the SPI_CLK at the low state level. Master
SPI_NSS output shall be set to high impedance.
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• The master shall drive the VDD power line ON.
7.2.3.5 MAC deactivation
The MAC deactivation procedure shall be the following if the SPI bus is not shared with other peripheral:
• The master shall set the SPI_MOSI to high impedance and the SPI_CLK at the low state level. Master
SPI_NSS output shall be set to high impedance.
• The master shall drive the VDD power line OFF.
7.2.4 4 signals MAC layer
7.2.4.1 Introduction
Considering a slave SPI block is normally always enabled to be ready for an access from master when selected by
SPI_NSS assertion, before a slave asserts SPI_NSS for a MAC access request it shall disable its SPI block. This is
necessary in order to avoid self-selection e.g. driving MISO in contention with MISO signals of other slaves potentially
selected at the same time on the same bus.
7.2.4.2 Initiation of the data transfer from the master
Figure 7.4 illustrates the initiation of the data transfer by the master.

Figure 7.4: Initiation of the data transfer from the master
The Master shall perform the following procedure:
1) The master checks if the SPI_NSS signal is at the high state level by reading SS_MI then goes to the step 2
otherwise loops on the step 1.
2) The master asserts SS_MO (to drive SPI_NSS signal to the low state) then goes to the step 3.
3) The master waits for T1 seconds then goes to the step 4. If master is certain that slave will not initiate a MAC
access request by asserting SPI_NSS then master may skip this step.
4) The master starts the bidirectional data transfer by toggling the SPI_CLK signal.
5) After data transfer completion i.e. SPI_CLK stop, master de-asserts SPI_NSS.
7.2.4.3 Initiation of the data transfer from the slave
Figure 7.5 illustrates the initiation of the data transfer from slave.
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Release 15 17 ETSI TS 103 713 V15.1.0 (2020-02)

Figure 7.5: Slave initiates a MAC access request
The slave runs the following procedure:
1) If the SPI_NSS signal is found at the high level state by reading SS_SI then the slave goes to the step 2.
2) The slave disables its SPI cell then goes to the step 3.
3) The slave asserts SS_SO to drive SPI_NSS to the low level state for at least T2 seconds then goes to step 4.
4) The slave enables its SPI Interface and waits for master to initiate the data transfer.
5) The SS_MI signal generates an internal interrupt for the master, triggered on SPI_NSS falling edge. This
interrupt initiates a data transfer procedure: master asserts SS_MO after at least T1 following the SPI_NSS
assertion by the slave for the MAC access request.
6) SPI_CLK starts after the SPI_NSS assertion by the master in the previous step, data transfer is performed.
7) After data transfer completion i.e. SPI_CLK stop, master de-asserts SPI_NSS.
7.2.4.4 Simultaneous initiation of the data transfer from both master and slave
Figure 7.6 illustrates a simultaneous initiation from the master and the slave.

Figure 7.6: Simultaneous initiation of the data transfer from both master and slave
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Release 15 18 ETSI TS 103 713 V15.1.0 (2020-02)
Both endpoints initiate a MAC phase for data transfers and run simultaneously their respective procedures. From a
master perspective the resulting procedure is equivalent to the initiation from the master. Slave initiates a MAC access
request and waits for the access start from master as per the timings defined. The time T1 - T2 shall be long enough for
the slave to enable the SPI block.
7.2.4.5 Slave-driven Flow Control
In certain use-cases and depending on the SPI block design, a slave may assert SS_SO during a data transfer in progress
for flow control e.g. when slave needs to delay a subsequent master access as slave estimates it may not be ready for
handling receive and transmit FIFO data due to unforeseen events. It is assumed slave already prepared data to be sent
(if available) for the current data transfer before it started and the transfer completes normally. Such an assertion of
SS_SO while the master access is in progress is not a slave MAC access request and a slave frame shall not start
(MISO) in the middle of the current access, a frame shall be always aligned with the start of an access.
Irrespective of the MAC procedures defined the slave may assert the SPI_NSS signal after the start of the data transfer,
by asserting SS_SO for maintaining SPI_NSS asserted despite the SPI_NSS de-assertion by the master. As long as the
SPI_NSS signal is asserted and even if the data transfer is completed, the master cannot run the MAC initiation by the
master procedure as defined in clause 7.2.4.1.
Slave may assert SS_SO for flow control any time between the start of the master access for data transfer by SPI_NSS
assertion and the end of the data transfer i.e. before SPI_NSS de-assertion by master.
NOTE: Detection by the slave of a data transfer start for initiating flow control could be performed either by
sensing the assertion of the SPI_NSS by master or by detection of the first bytes transferred.
Figure 7.7 illustrates the waveforms for this procedure.
T1
DATA TRANSFER
T
SPI_NSS
SS_MO
SS_SO
Figure 7.7: Slave activates hardware flow control by assertion of SS_SO
7.2.4.6 MAC activation
The MAC activation procedure shall be the following if the SPI bus is not shared with other peripheral:
• The master shall set the SPI_MOSI to high impedance and the SPI_CLK at the low state level. The SS_MO
shall be at the low level then driving the SPI_NSS output to high impedance.
• The master shall drive the VDD power line ON.
7.2.4.7 MAC deactivation
The MAC deactivation procedure shall be the following if the SPI bus is not shared with other peripheral:
• The master shall set the SPI_MOSI to high impedance and the SPI_CLK at the low state level. The SS_MO
shall be at the low level then driving the SPI_NSS output to high impedance.
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Release 15 19 ETSI TS 103 713 V15.1.0 (2020-02)
• The master shall drive the VDD power line OFF.
7.3 Link Layer Frame
7.3.1 Overview
Master and slave exchange frames. The format of the frames generated by master and slave is determined by the link
layer and it is shown in figure 7.8.

Figure 7.8: Link Layer Frame structure
All bytes shall be transmitted with MSB first (most significant bit first). All fields of the frame are transferred with the
most significant byte first.
The link layer frame shall contain the following fields:
• LPDU length: length of the LPDU, 1 byte.
• LPDU (Link Protocol Data Unit): LPDU includes the LLC control byte as defined in clause 7.4.
• CRC informs about the integrity of the whole frame i.e. Length and LPDU. Detection of errors in a frame shall
be based on the 16-bit frame checking sequence as given in ISO/IEC 13239 [3]. The CRC polynomial is:
X16 + X12 + X5 + 1. Its initial value is 'FFFF'.
Link Layer Frames are exchanged between SPI master and slave during SPI accesses. The SPI master determines the
number of bytes exchanged in an SPI access. The maximum length of an access is MTU.
Link Layer frames (including header, LPDU and trailer) shall always be prepared with length less than or equal to
MTU.
MTU values are negotiated at SPI interface initialization as described in clause 7.6. The resultant MTU shall be the
smallest MTU value between the MTU of the master and the MTU of the slave. The MTU shall be the same
irrespective of the transfer direction.
Non-significant data (NSD) may be appended at the end of a master or slave link layer frame until the end of the SPI
access according to the rules described below, considering LPDU Length + 3 + NSD length ≤ MTU.
NSD shall consist of idle bytes set to the value 'FF' sent by:
• A master while retrieving a slave frame and not sending any frame.
• A slave while receiving a frame from master and not sending any frame.
Master frames, slave frames or remaining bytes of a slave frame (i.e. in a second SPI access for retrieving a slave
frame) shall always start aligned on the first bytes transmitted on SPI_MOSI and SPI_MISO at SPI_CLK start.
The LPDU Length value shall be compliant with the values indicated in table 7.2.
Master frames, slave frames or remaining bytes of a slave frame (i.e. in a second SPI access for retrieving a slave
frame) shall always start aligned on the first bytes transmitted on SPI_MOSI and SPI_MISO at SPI_CLK start.
The LPDU Length value shall be compliant with the values indicated in table 7.2.
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Release 15 20 ETSI TS 103 713 V15.1.0 (2020-02)
Table 7.2
LPDU Length LPDU
'00' RFU
'01' to
...