ETSI ETS 300 233/A1 ed.1 (1995-03)

Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate; Conformance Testing Principles

RE/TM-03046

Digitalno omrežje z integriranimi storitvami (ISDN) – Dostopovni digitalni oddelek za primarne funkcije ISDN

General Information

• Status: Published
• Publication Date: 15-Mar-1995
• Technical Committee: TM 3 - Interfaces, architecture and functional requirements of transport netw
• Current Stage: 12 - Completion
• Due Date: 01-Mar-1995
• Completion Date: 16-Mar-1995
• Ref Project: SIST ETS 300 233/A1 E1:2003 - Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate; Conformance Testing Principles

Standards Content (Sample)

SLOVENSKI STANDARD
SIST ETS 300 233/A1 E1:2003
01-december-2003
Digitalno omrežje z integriranimi storitvami (ISDN) – Dostopovni digitalni oddelek
za primarne funkcije ISDN
Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate;
Conformance Testing Principles
Ta slovenski standard je istoveten z: ETS 300 233/A1 Edition 1
ICS:
33.080 Digitalno omrežje z Integrated Services Digital
integriranimi storitvami Network (ISDN)
(ISDN)
SIST ETS 300 233/A1 E1:2003 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST ETS 300 233/A1 E1:2003

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SIST ETS 300 233/A1 E1:2003
ETS 300 233
AMENDMENT A1
March 1995
Source: ETSI TC-TM Reference: RE/TM-03046
ICS: 33.080
ISDN, primary rate access digital section, testing
Key words:
This amendment A1 modifies
the European Telecommunication Standard ETS 300 233 (1994)
Integrated Services Digital Network (ISDN);
Access digital section for ISDN primary rate
ETSI
European Telecommunications Standards Institute
ETSI Secretariat
F-06921 Sophia Antipolis CEDEX - FRANCE
Postal address:
650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE
Office address:
c=fr, a=atlas, p=etsi, s=secretariat - [e-mail]
X.400: Internet:
Tel.: [phone] - Fax: [phone]
Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the
foregoing restriction extend to reproduction in all media.
© European Telecommunications Standards Institute 1995. All rights reserved.
New presentation - see History box

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Whilst every care has been taken in the preparation and publication of this document, errors in content,
typographical or otherwise, may occur. If you have comments concerning its accuracy, please write to
"ETSI Editing and Committee Support Dept." at the address shown on the title page.

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Foreword
This amendment to ETS 300 233 (1994) has been produced by the Transmission and Multiplexing (TM)
Technical Committee of the European Telecommunications Standards Institute (ETSI).
This amendment provides the annex C, which was left "To be provided" in ETS 300 233 (1994).
Amendment
Page 74, annex C
Replace the current annex C "To be provided" with the following annex C.
Annex C (normative): Conformance test principles for the ISDN primary rate
access digital section
C.1 Scope and general information
C.1.1 Scope of this annex
This annex provides the test principles for the requirements of this ETS used to determine the compliance
of an implementation under test to this ETS.
This annex does not specify test related to:
- safety requirements;
- interface or equipment overvoltage protection requirements;
- immunity requirements against electromagnetic interferences;
- emission limitation requirements.
Detailed test equipment accuracy and the specification tolerance of the test devices is not a subject of this
annex. Where such details are provided then those test details are considered as being an informative
addition to the test description.
The test configurations given do not imply a specific realisation of test equipment, or arrangement, or the
use of specific test devices for conformance testing. However, any test configuration used shall provide
those test conditions specified under "system state", "stimulus" and "monitor" for each individual test.
C.1.2 General information
For conformance test of the access digital section two relevant test points have to be identified:
- the T reference point covered by ETS 300 011 [1];
- the V3 reference point.
This annex is applicable to interfaces T and V3 as appropriate. The field of application is given at the
beginning of each test.
As the transmission system is not specified in this ETS, only relevant signals inside the primary rate
stream need to be checked. The coding and the frame organization of this bit stream is outside the scope
of this ETS.

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C.1.2.1 Additional information to support the test
The V3 interface is required to be a standard CCITT Recommendation G.703 [8] interface (either 120 Ω
balanced or 75 Ω unbalanced) according to CCITT Recommendation Q.512 [4].
If the V3 reference point is not implemented as an interface, a suitable means such as either a local
exchange or a Conformance Test Adaptor (CTA) enabling the monitoring of the V1 reference point and
giving access to the B and D channels shall be provided by the manufacturer.
C.1.2.2 Abbreviations
For the purpose of this annex the following additional abbreviations apply:
FAS Frame Alignment Signal
IUT Item Under Test
MF Multiframe
MFAS Multiframe Alignment Signal
PRBS Pseudo Random Bit Sequence
Rx interface signal Receiver (of the IUT or simulator)
SMF Sub-Multiframe
Tx interface signal Transmitter of the IUT or simulator
C.1.2.3 Definitions
For the purpose of this annex the following additional definitions apply:
Primary rate access Digital Section (DS): the provision to transmit a digital signal of specified rate
between two consecutive reference points. The term should be qualified by the type of access supported,
or by a prefix denoting the V interface at the digital section boundaries. For example:
- basic rate access digital section;
- primary rate access digital section;
-V digital section.
5
Item Under Test (IUT): Implementation of interfaces related functions for:
- the user side interface (T), i.e. NT1; and
- the exchange side interface (V
), i.e. LT.
3
Simulator (terminal equipment, exchange): device generating a stimulus signal conforming to this ETS
to bring the IUT into the required operational state and monitoring the receive signal from the IUT. It can
either be a simulator for the user side or the exchange side of the interface.
C.1.3 Connection of the simulator to the IUT
For testing the electrical characteristics of the IUT, the simulator, or its relevant part, shall be connected
directly to the interconnecting points for the interface wiring at the IUT unless otherwise stated.
All other tests may be performed with interface wiring complying with the requirements given in CCITT
Recommendation G.703 [8] and in ETS 300 011 [1], table 1, clause 7.

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C.1.4 Allocation of test
One test definition may cover more than one requirement for one or both interface points (interface T or
V3). Requirements which do not need specific test definition are indicated by "N/R" (Not Relevant).
Requirements which are not relevant for this ETS and which require testing defined by other ETSs are
indicated by "N/A" (Not Applicable).
C.1.4.1 General
Table C.1: General requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Scope 1 N/R
Normative references 2 N/R
Definitions and abbreviations 3 N/R
Definitions 3.1 N/R
Abbreviations 3.2 N/R
C.1.4.2 Type of configuration and applications requirements
Table C.2: Type of configuration and applications requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Configuration and application 4 N/R
Configuration 4.1 N/R
Application 4.2 N/R
Modelling and relationship between 4.3 N/R
the access DS and the ET

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C.1.4.3 Functional characteristics requirements
Table C.3: Functional characteristics requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Function 5 N/R
B-channel 5.1 T and V3 C.2.1 and C.2.5.5
H0-channel 5.2 T and V3 C.2.1 and C.2.5.5
H1-channel 5.3 T and V3 C.2.1 and C.2.5.5
D-channel 5.4 T and V3 C.2.1
Bit timing 5.5 T and V3 C.2.5
Octet timing 5.6 T and V3 C.2.3, C.2.3.3, and
C.2.5.5
Frame alignment 5.7 T and V3 C.4.1
CRC-4 procedure 5.8 T and V3 C.4.2
M channel 5.9 T and V3 C.2.1
Power feeding 5.10 T C.5.1
Operation and maintenance of access 5.11 T and V3 C.3.1
digital section

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C.1.4.4 Signal delay and jitter requirements
Table C.4: Signal delay and jitter requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Signal transfer delay 6 T and V3 C.2.4
Jitter 7 N/R
Output/Input jitter at T reference point 7.1 T C.2.6.1 and C.2.6.3
Jitter at V3 reference point 7.2 V3 C.2.6.2
C.1.4.5 Operation and maintenance
Table C.5: Operation and maintenance requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Operation and maintenance 8 N/R
Control facilities 8.1 N/R
Loopbacks 8.1.1 N/R
Loopbacks implementation 8.1.1.1
i) V3 C.7.1
ii) V3 C.7.2
Loopback procedure 8.1.1.2 C.7
Monitoring 8.2 N/R
Functions 8.2.1 N/R
Defect conditions and consequent 8.2.2 N/R
action
Detection of defect conditions 8.2.2.1 N/R
(continued)

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Table C.5 (continued): Operation and maintenance requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Definition of defect indication signals 8.2.2.2
- NF T and V3 C.2.2
- Frames T and V3 C.6
- Substituted frames V3 C.3.1 and C.6.4
- LFA T and V3 C.3.1
- Loss of power in NT1 or LT T and V3 C.3.1 and C.6.6
- AUXP T and V3 C.6.8
Detection of defect indication signals 8.2.2.3
- LOS or LFA at line side of NT1 V3 C.8.3
- LOS at line side of LT V3 C.8.8
- Loss of power at NT1 V3 C.8.6
- AIS at line side of NT1 V3 C.2.5.1
- LOS at V3 V3 C.6.3
- LOS at T T and V3 C.6.2
- Loss of power at T T and V3 C.3.1
Definition of detection algorithm 8.2.2.4
- NOF T and V3 C.2.1
- LFA T and V3 C.4.3
- Loss of signal at T and V3 T and V3 C.3.1 and C.6.1
- AIS T and V3 C.3.1
- Loss of power in the NT1 T and V3 C.3.1 and C.6.6
- Loss of power in the LT T and V3 C.3.1
Consequent action 8.2.2.5 T and V3 C.6
Error performance monitoring 8.3 V3 C.4.2 and C.4.3
Operation and maintenance 9 N/R
procedures
Partitioning of function 9.1 N/R
Definitions of signals at T reference 9.2 N/R
point
Definitions of signals at V3 reference 9.3 N/R
point
(continued)

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Table C.5 (continued): Operation and maintenance requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
FEs related to operation and table 2
maintenance
- normal DS->ET V3 C.2.2 and C.6
- normal DS<-ET N/A
- unintentional loopback V3 C.3.1 and C.6
- LOS/LFA at TE (FC2) T and V3 C.3.1, C.4.1, and
C.6.2
- LOS at line side of NT1 or at T and V3 C.3.1 and C.6.3
V3 (FC3)
- LOS/LFA at V3 of ET (FCL) N/A
- LOS/LFA at T (FC4) T and V3 C.3.1 and C.6.4
- FC3 and FC4 simultaneously T and V3 C.3.1 and C.6.5
- Loss of power at NT1 T and V3 C.3.1 and C.6.6
- Loss of power at NT1 and T and V3 C.6.7 and C.6.2
LOS/LFA at TE simultaneously
- LOS at line side of LT V3 C.6.8 and C.3.1
- Reception of AIS at V3 of LT V3 C.3.1 and C.2.5.1
(reaction to FCDL or FCET)
- Reception of AIS at V3 of LT V3 C.2.5.1
and FC4 simultaneously
- Defect FCET in ET or FCDL N/A
between V3 and V3'
- Defect FCDLu between V3 N/A
and V3'
FEs related to loopback operation table 3
- loopback 1 command V3 C.7
- loopback 2 command V3 C.7
- loopback acknowledge V3 C.7
- loopback release command V3 C.7
(continued)

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Table C.5 (concluded): Operation and maintenance requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
FEs related to CRC-4 error detection table 4
- CRC error report from NT1 V3 C.4.3
- CRC error information from V3 C.4.3
ET
- CRC error report from TE V3 C.4.3
- CRC error detection at T of V3 C.4.3
NT1
- Simultaneously occurrence of V3 C.4.3
FE W and FE X
Definition of ET layer 1 state machine 9.5 N/R
DS states 9.5.1 N/R
DS states trans. table 9.5.2 N/R
Assumptions 9.5.2.1 N/R
Classification of DS states 9.5.2.2 N/R
Definition of notations 9.5.2.3 N/R
Notes to DS state table 9.5.2.4 N/R

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C.1.4.6 System management requirements
Table C.6: System management requirements
Functions Clause/ Relevant interface Test defined in
subclause T, V3, or T and V3
Introduction A.1 N/A
System management requirements A.2 N/A
General A.2.1 N/A
Error indications A.2.2 N/A
Loopback operations A.2.3 N/A
Information to be sent in the D A.2.4 N/A
channel during loopback operation
Configuration control A.2.5 N/A
Handling of CRC error information in A.3 N/A
the ET
Definition of ET layer 1 state machine A.4 N/A
ET layer 1 states A.4.1 N/A
PH and MPH primitives A.4.2 N/A
The repertoire of PH and MPH A.4.2.1 N/A
primitives
ET layer 1 state transition table A.4.3 N/A
Definition of notations A.4.3.1 N/A
Classification of ET states A.4.3.2 N/A

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C.2 Signal requirements
C.2.1 Access digital section transparent signal transfer
Test applicable at T and V3 reference points.
Purpose: To check the access digital section's transparent transfer of B-channel,
H0-channel, H1-channel, M-channel, D-channel, A-bit, Sa7-bit and Sa8-bit
between T and V3 reference points.
Test configuration:
T V3
TX
RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
TX RX
RX TX
POW ER
POW ER
SOURCE SINK
T V3
Figure C.1: Test configuration for access digital section transparent signal transfer
System state: State DS 1.11 (normal operation).
Stimulus: A PRBS is used to fill appropriate channels or bits under test.
Monitor: The IUT output signal at both T and V3 reference point.
Results: The monitored output signal has to match the stimulus signal.

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C.2.2 HDB3 coding and normal operational frame
Test applicable at T and V3 reference points.
Purpose: To check the coding, decoding, and the binary organization of normal
operational frame.
Test configuration:
T V3
TX RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
RX TX RX TX
POW ER
POW ER
SOURCE
SINK
T V3
Figure C.2: Test configuration for HDB3 coding and normal operational frame
System state: State DS 1.11 (normal operation):
- network timing and layer 1 services are available;
- the network side transmits and receives operational frames with
associated CRC bits and temporary CRC error information;
- the network side checks the received frames and the associated CRC
bits, and transmits to the user side operational frames containing the
CRC error information, if a CRC error is detected.
Stimulus: Normal operational frame sent continuously from the Simulators with valid time
15
slot 0 including active CRC and without CRC error. A PRBS 2 - 1 shall fill
continuously all the frame except time slot 0 (net bit rate 1 984 kbit/s).
Monitor: The coding and the frame structure of the signal sent from the IUT.
Results: The signal received shall be encoded according to the HDB3 coding rule
(annex A of CCITT Recommendation G.703 [8]). The frame shall comprise valid
time slot 0 with A bit set to ZERO, E bit set to ONE and including correct CRC
without CRC blocks in error.

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C.2.3 Frame structure
These tests check the frame composition.
C.2.3.1 Number of bits per time slot
This requirement cannot be verified via layer 1 procedures.
Test to be performed at higher protocol layers.
C.2.3.2 Number of time slots per frame
This requirement cannot be verified via layer 1 procedures.
Test to be performed at higher protocol layers.
C.2.3.3 Generation of frame alignment word
Test applicable at T and V3 reference point.
Purpose: To check the correct generation of frame alignment word, Multiframe (MF)
alignment word, CRC bits C1 to C4.
Test configuration:
T V3
TX
RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
RX
RX TX TX
POW ER POW ER
SOURCE SINK
T V3
Figure C.3: Test configuration for generation of frame alignment word
System state: State DS 1.11 (normal operation).
15
Stimulus: Normal operational frames with PRBS 2 - 1 in time slot 1 to 31.
15
A PRBS 2 - 1 shall fill continuously all the frame except time slot 0 (net bit rate
1 984 kbit/s).
Monitor: Correct frame alignment word, MF alignment word, CRC bits.
Results: No detection of incorrect frame alignment word, MF alignment word, and no
received Sub-Multiframes (SMFs) in error within 1 s measured in any state.
During this test the E bit is not considered.

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C.2.4 Signal transfer delay
Test applicable at T and V3 reference points.
Purpose: To test the mean one way delay between T and V3 interfaces in the two
directions of transmission.
Test configuration:
T V3
TX RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
RX TX RX TX
POW ER
POW ER
SOURCE
SINK
T V3
Figure C.4: Test configuration for signal transfer delay
System state: State DS 1.11 (normal operation):
- network timing and layer 1 services are available.
Stimulus: An appropriate sequence sent in the B channels.
Monitor: Measure the delay to receive this sequence in the B channels at the reception
side.
Results: Mean value < 1 250 μs.

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C.2.5 Timing considerations
C.2.5.1 AIS recognition
Test applicable at V3 reference point.
Purpose: To check the ability of the IUT to recognize AIS.
Test configuration:
T V3
TX RX TX RX
SIMULATOR
SIMULATOR
T
IUT V3
REF.POINT REF.POINT
TX RX
RX TX
POW ER
POW ER
SOURCE SINK
T V3
Figure C.5: Test configuration for timing considerations, AIS recognition
System state: State DS 6.66
Stimulus: AIS signal at V3 reference point with nominal clock frequency 2 048 kbit/s,
nominal clock frequency + 50 ppm, nominal clock frequency - 50 ppm.
The user side transmits, through the DS, to the network side operational frames
with associated CRC bits and RAI.
Monitor: The frames transmitted by the IUT.
Results: The IUT shall remain in state DS 6.66, therefore no change of error indication
shall occur.
AIS shall be detected at T reference point, FE M and associated CRC bits at V3
reference point.

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C.2.5.2 AIS generation
Test applicable at T reference point.
Purpose: To check the frequency of the AIS signal generated by the IUT.
Test configuration:
T V3
TX
RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
TX RX
RX TX
POW ER
POW ER
SOURCE SINK
T V3
Figure C.6: Test configuration for timing considerations, AIS generation
System state: State DS 4.32.
Stimulus: LOS of signal at V3 reference point (FV 3).
Monitor: The frequency of the signal generated by the IUT at the T reference point.
Results: The frequency has to be in the range 2 048 kbit/s ± 50 ppm.

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C.2.5.3 Synchronisation at V3 reference point
Test applicable at V3 reference point.
Purpose: The ability of the IUT to synchronize its timing on the signal received from the
network and its ability to transfer this timing at T reference point.
Test configuration:
T V3
TX RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
RX TX RX TX
POW ER
POW ER
SOURCE
SINK
T V3
Figure C.7: Test configuration for timing considerations, synchronisation at V3 reference point
System state: State DS 1.11 (normal operation):
- network timing and layer 1 services are available.
Stimulus: Normal operational frames with clock frequency variation from the nominal value
in the range 2 048 kbit/s ± 5 ppm.
15
A PRBS 2 - 1 shall fill continuously all the frame except time slot 0 (net bit rate
1 984 kbit/s).
Monitor: The frames transmitted by the IUT.
Results: 1) the IUT shall remain in state DS 1.11, no LFA/LOS shall be detected
at T and V3 reference point;
2) the frequency of the outgoing signal at each access has to follow
the frequency of the stimulating input signal.

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C.2.5.4 Synchronisation at T interface
Purpose: The ability of the IUT to synchronise to a frame signal at the T interface during
FC 2.
Test configuration:
T V3
TX
RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
TX RX
RX TX
POW ER
POW ER
SOURCE SINK
T V3
Figure C.8: Test configuration for timing considerations, synchronisation at T interface
System state: State DS 1.11 with FC 2:
- network timing at network side and layer 1 services are available.
Stimulus: NF at V3 reference point with nominal clock frequency.
NF at T reference point with A = 1 and clock frequency variation from the
nominal value of 2 048 kbit/s + 50 ppm and 2 048 kbit/s - 50 ppm.
15
A PRBS 2 - 1 shall fill continuously all the frame except time slot 0 (net bit rate
1 984 kbit/s).
Monitor: A bit, Sa5 bit and Sa6 bit at V3 reference point.
Results: Verify that A = 1, Sa5 = 1 and Sa6 = 00xx (x representing any value ONE or
ZERO).

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C.2.5.5 Octet Timing and B channels octet transparency
Test applicable at T and V3 reference points.
Purpose: To check the access digital section's transparent transfer of B-channel octets
between T and V3 reference points.
Test configuration:
T V3
TX RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
RX TX RX TX
POW ER
POW ER
SOURCE
SINK
T V3
Figure C.9: Test configuration for timing considerations, octet timing and B channels octet
transparency
System state: State DS 1.11 (normal operation).
Stimulus 1: Alternatively a fixed word is inserted in a selected B channel chosen in the range
from B to B and B to B . The stimulus is applied at the T reference point.
1 15 17 31
Stimulus 2: Alternatively a fixed word is inserted in a selected B channel chosen in the range
from B to B and B to B . The stimulus is applied at the V3 reference point.
1 15 17 31
Monitor 1: The words in the selected B channel at the V3 reference point.
Monitor 2: The words in the selected B channel at the T reference point.
Results: No bit errors.

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C.2.6 Jitter
C.2.6.1 Minimum tolerance to jitter and wander at inputs
Test applicable at T reference point.
Purpose: To check the ability of the IUT to tolerate on the 2 048 kbit/s incoming signal a
sinusoidal jitter/wander in accordance with ETS 300 011 [1], table 1,
subclause 5.4.2.
Test configuration:
T V3
JITTER
TX RX TX RX
MODULATOR
SIMULA TOR
SIMULATOR
T
IU T V3
RE F.POINT REF.POINT
RX TX RX
TX
POW ER
POW ER
SOURCE
SINK
T V3
Figure C.10: Test configuration for minimum tolerance to jitter and wander at inputs
System state: State DS 1.11 (normal operation):
- network timing and layer 1 services are available;
- the network side transmits and receives operational frames with
associated CRC bits and temporary CRC error information;
- the network side checks the received frames and the associated CRC
bits, and transmits to the user side operational frames containing the
CRC error information, if a CRC error is detected.
Stimulus: Normal operational frames with jitter/wander according to the table C.7
15
(reference: ETS 300 011 [1], table 1, subclause 5.4.2) and with a PRBS 2 - 1
15
in time slots 1 to 31. The PRBS 2 - 1 shall fill continuously all the frame except
time slot 0 (net bit rate 1 984 kbit/s).
Table C.7
A0 A1 A2 f0 f1 f2 f3 f4
-6
20,5 UI p-p 1,0 UI p-p 0,2 UI p-p 12x10 Hz 20 Hz 3,6 Hz 18 kHz 100 kHz
This test shall be performed twice with clock frequency varying from the nominal value + 5 ppm and
- 5 ppm.
Points A1 - f2 and A2 - f4 shall be measured. For the range between A0 - f0 to A1 - f1 the jitter behaviour
can be determined from the Q factor.
Monitor: The frames transmitted by the IUT.
Results: The IUT shall remain in state DS 1.11 (operational state), no LFA report shall be
detected by the simulator at V3 reference point.
NOTE 1: This test relies on the correct operation of the CRC error information report by the IUT.

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C.2.6.2 Output jitter at V3 reference point
Test applicable at V3 reference point.
Purpose: To measure the jitter generated by the IUT.
Test configuration:
T V3
TX
RX TX RX
SIMULATOR
SIMULATOR
T IUT V3
REF.POINT REF.POINT
TX RX
RX TX
POW ER
POW ER
SOURCE SINK
T V3
Figure C.11: Test configuration for output jitter at V3 reference point
System state: State DS 1.11 (normal operation).
Stimulus: Normal operational frames with jitter according to the table C.8, provided to the
synchronizing input of the IUT (i.e. connected at T reference point to the access
15
digital section) and with a PRBS 2 - 1 in time slots 1 to 31. The PRBS
15
2 - 1 shall fill continuously all the frame except time slot 0 (net bit rate
1 984 kbit/s) with frequency variation in the range 2 048 kbit/s ± 5 ppm (two
different measurements).
Table C.8
Modulating frequency Input jitter
UI peak to peak
40 Hz 1,1
100 kHz 0,11
Monitor: The jitter extracted from the signal transmitted by the IUT.
Results: The peak to peak jitter shall comply with the limits given in CCITT
Recommendation G.823 [6].

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C.2.6.3 Output jitter at T reference point
Test applicable at T reference point.
Purpose: To measure the jitter generated by the IUT.
Test configuration:
T V3
JITTE R
TX RX TX
MEASURE MEN T
UNIT
SIMULATOR
IUT V3
REF.POINT
RX
POW E R
POW ER
SO UR CE
SINK
T V3
Figure C.12: Test configuration for output jitter at T reference point
The jitter measurement shall be done using equipment that has an external timing reference to the jitter
measurement set which has no phase variation energy in the jitter region under test.
System state: State DS 1.11 (normal operation).
Stimulus: Normal operational frames without jitter provided by the simulator (i.e.
connected at V3 reference point to the access digital section) and with a PRBS
15 - 15 -
2 1 in time slots 1 to 31. The PRBS 2 1 shall fill continuously all the frame
except time slot 0 (net bit rate 1 984 kbit/s) with frequency variation in the range
2 048 kbit/s ± 5 ppm (two different measurements).
Monitor: The jitter extracted from the signal transmitted by the IUT.
Results: The peak to peak jitter shall comply with table C.9.
Table C.9
Measurement filter bandwidth Output jitter
Lower cut off Upper cut off UI peak to peak
(high pass) (low pass)
20 Hz 100 kHz
≤ 1UI
18 kHz 100 kHz
≤ 0,2 UI
C.3 State matrix
C.3.1 State matrix of the IUT
Test applicable at T and V3 reference point.
Purpose: The tests defined in this subclause intend to check the different stable states at
the IUT sides and the possible transitions between them. These tests are
performed by simulating the opposite side (and simulating internal fault in the
IUT), monitoring the IUT at the interfaces and verifying appropriate state
transition.
As a minimum, all transitions from and returning to normal state DS 1.11 shall
be tested in accordance with clauses C.6 and C.7.

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C.4 Interface procedure tests
Definition of test sequences
FAS Frame with correct Frame Alignment Signal (FAS), correct bits C1 to C4 and
correct CRC Multiframe Alignment Signal (MFAS) in time slot 0.
/FAS Frame with incorrect FAS, correct bits C1 to C4 and correct MFAS in time slot 0.
BIT 2 Bit 2 of time slot 0 not containing the FAS.
FRAME A Two consecutive frames having FAS in the first time slot 0, BIT 2 = 1 in the
second time slot 0 and no contiguous group of seven bits which simulates the
FAS in time slots 1 to 31.
FRAME B Two consecutive frames having FAS in the first time slot 0, BIT 2 = 1 in the
second time slot 0, simulated BIT 2 = 1 in the first time slot 31 and simulated
FAS (no corresponding MFAS) in the second time slot 31.
FRAME C Two consecutive frames having /FAS in the first time slot 0, BIT 2 = 1 in the
second time slot 0, simulated BIT 2 = 1 in the first time slot 31 and simulated
FAS (no corresponding MFAS) in the second time slot 31.
SMF A SMF having correct generation of C1 to C4 bits.
SMF B SMF having incorrect generation of C1 to C4 bits.
MF A MF having correct FAS, BIT 2 = 1, MFAS and correct C1 to C4 bits.
MF B MF having correct FAS, BIT 2 = 1, but incorrect MFAS and correct C1 to C4 bits.
# n # indicates that the
...