IEC 61691-6:2009
(Main)Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.
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IEC 61691-6
Edition 1.0 2009-12
™
IEEE Std 1076.1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
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IEC 61691-6
Edition 1.0 2009-12
™
IEEE Std 1076-1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XH
ICS 25.040, 35.060 ISBN 978-0-7381-6283-6
– i –
IEEE Std 1076.1-2007(E)
CONTENTS
Foreword .v
IEEE introduction .viii
0. Overview. 1
0.1 Purpose and scope. 1
0.2 Normative references. 1
0.3 Structure and terminology of this standard.2
1. Design entities and configurations. 5
1.1 Entity declarations . 5
1.2 Architecture bodies . 10
1.3 Configuration declarations. 12
2. Subprograms and packages. 19
2.1 Subprogram declarations . 19
2.2 Subprogram bodies . 22
2.3 Subprogram overloading. 24
2.4 Resolution functions . 27
2.5 Package declarations. 27
2.6 Package bodies. 29
2.7 Conformance rules. 30
3. Types and natures . 31
3.1 Scalar types . 32
3.2 Composite types. 38
3.3 Access types. 43
3.4 File types. 46
3.5 Protected types. 48
3.6 Natures . 51
4. Declarations . 55
4.1 Type declarations. 55
4.2 Subtype declarations . 56
4.3 Objects . 57
4.4 Attribute declarations. 75
4.5 Component declarations. 76
4.6 Group template declarations . 77
4.7 Group declarations. 77
4.8 Nature declaration. 78
5. Specifications. 81
5.1 Attribute specification. 81
5.2 Configuration specification. 83
5.3 Disconnection specification. 91
5.4 Step limit specification . 93
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.
– ii –
IEEE Std 1076.1-2007(E)
6. Names . 97
6.1 Names . 97
6.2 Simple names. 98
6.3 Selected names. 99
6.4 Indexed names . 101
6.5 Slice names . 102
6.6 Attribute names. 102
7. Expressions . 105
7.1 Expressions . 105
7.2 Operators. 106
7.3 Operands . 115
7.4 Static expressions. 121
7.5 Universal expressions . 123
7.6 Linear forms. 124
8. Sequential statements. 127
8.1 Wait statement . 127
8.2 Assertion statement. 129
8.3 Report statement . 130
8.4 Signal assignment statement. 130
8.5 Variable assignment statement . 135
8.6 Procedure call statement . 137
8.7 If statement. 137
8.8 Case statement . 138
8.9 Loop statement. 139
8.10 Next statement . 140
8.11 Exit statement. 140
8.12 Return statement . 140
8.13 Null statement . 141
8.14 Break statement. 141
9. Concurrent statements. 143
9.1 Block statement. 143
9.2 Process statement. 144
9.3 Concurrent procedure call statements. 145
9.4 Concurrent assertion statements . 146
9.5 Concurrent signal assignment statements . 147
9.6 Component instantiation statements . 151
9.7 Generate statements . 157
9.8 Concurrent break statement . 158
10. Scope and visibility. 159
10.1 Declarative region. 159
10.2 Scope of declarations . 160
10.3 Visibility . 161
10.4 Use
...
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