Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions

IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

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Status
Published
Publication Date
13-Dec-2009
Drafting Committee
Current Stage
DELPUB - Deleted Publication
Completion Date
08-Jun-2021
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IEC 61691-6
Edition 1.0 2009-12

IEEE Std 1076.1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions


IEC 61691-6:2009(E) IEEE Std 1076.1-2007(E)

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IEC 61691-6
Edition 1.0 2009-12

IEEE Std 1076-1
INTERNATIONAL
STANDARD


Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XH
ICS 25.040, 35.060 ISBN 978-0-7381-6283-6

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– i –
IEC 61691-6:2009(E)
IEEE Std 1076.1-2007(E)
CONTENTS
Foreword .v
IEEE introduction .viii
0. Overview. 1
0.1 Purpose and scope. 1
0.2 Normative references. 1
0.3 Structure and terminology of this standard.2
1. Design entities and configurations. 5
1.1 Entity declarations . 5
1.2 Architecture bodies . 10
1.3 Configuration declarations. 12
2. Subprograms and packages. 19
2.1 Subprogram declarations . 19
2.2 Subprogram bodies . 22
2.3 Su
...

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