IEC 60424-5:2009
(Main)Ferrite cores - Guide on the limits of surface irregularities - Part 5: Planar-cores
Ferrite cores - Guide on the limits of surface irregularities - Part 5: Planar-cores
IEC 60424-5:2009 gives guidance on allowable limits of surface irregularities applicable to planar-cores in accordance with the relevant generic specification. This standard is considered as a sectional specification useful in the negotiation between ferrite core manufacturers and users about surface irregularities.
Noyaux de ferrite - Guide relatif aux limites des irrégularités de surface - Partie 5: Noyaux planaires
La CEI 60424-5:2009 donne des lignes directrices relatives aux limites admissibles pour les irrégularités de surface applicables aux noyaux planaires conformément à la spécification générique applicable. La présente norme est considérée comme une spécification intermédiaire utile dans les négociations entre fabricants et utilisateurs de noyaux de ferrite concernant les irrégularités de surface.
General Information
Relations
Buy Standard
Standards Content (Sample)
IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
either IEC or IEC's member National Committee in the country of the requester.
If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication,
please contact the address below or your local IEC member National Committee for further information.
IEC Central Office
3, rue de Varembé
CH-1211 Geneva 20
Switzerland
Email: inmail@iec.ch
Web: www.iec.ch
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.
About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.
ƒ Catalogue of IEC publications: www.iec.ch/searchpub
The IEC on-line Catalogue enables you to search by a variety of criteria (reference number, text, technical committee,…).
It also gives information on projects, withdrawn and replaced publications.
ƒ IEC Just Published: www.iec.ch/online_news/justpub
Stay up to date on all new IEC publications. Just Published details twice a month all new publications released. Available
on-line and also by email.
ƒ Electropedia: www.electropedia.org
The world's leading online dictionary of electronic and electrical terms containing more than 20 000 terms and definitions
in English and French, with equivalent terms in additional languages. Also known as the International Electrotechnical
Vocabulary online.
ƒ Customer Service Centre: www.iec.ch/webstore/custserv
If you wish to give us your feedback on this publication or need further assistance, please visit the Customer Service
Centre FAQ or contact us:
Email: csc@iec.ch
Tel.: +41 22 919 02 11
Fax: +41 22 919 03 00
IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
N
ICS 29.100.10 ISBN 978-2-88910-190-0
– 2 – 60424-5 © IEC:2009(E)
CONTENTS
FOREWORD.3
1 Scope.5
2 Normative references .5
3 Limits of surface irregularities.6
3.1 Chips and ragged edges.6
3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2
and 3).6
3.1.2 Chips and ragged edges on other surfaces.7
3.2 Cracks.10
3.3 Flash.10
3.4 Pull-out .10
Figure 1 – Chip location for planar EL-core.6
Figure 2 – Chip location for low profile E-core.6
Figure 3 – Chip location for low profile ER-core .6
Figure 4 – Cracks and pull-out location for planar EL-core .10
Figure 5 – Cracks and pull-out location for low profile E-core.11
Figure 6 – Cracks and pull-out location for low profile ER-core .11
Figure 7 – Reference dimensions for EL-core .11
Figure 8 – Reference dimensions for E-core .12
Figure 9 – Reference dimensions for ER-core.13
Table 1 – Allowable areas of chips in mm for planar EL-core.7
Table 2 – Allowable areas of chips in mm for low profile E-core .8
Table 3 – Allowable areas of chips in mm for low profile ER-core .8
Table 4 – Area and length reference for visual inspection .9
Table 5 – Limits of cracks for planar EL-core .12
Table 6 – Limits of cracks for low profile E-core.13
Table 7 – Limits of cracks for low profile ER-core .14
60424-5 © IEC:2009(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –
Part 5: Planar-cores
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)“). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60424-5 has been prepared by IEC technical committee 51:
Magnetic components and ferrite materials.
The text of this standard is based on the following documents:
FDIS Report on voting
51/947/FDIS 51/950/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 60424 series, under the general title Ferrite cores – Guide on the
limits of surface irregularities, can be found on the IEC website.
– 4 – 60424-5 © IEC:2009(E)
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.
60424-5 © IEC:2009(E) – 5 –
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –
Part 5: Planar-cores
1 Scope
This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable
to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1.
The relations between the main dimensions of planar E-, ER- and EL-cores differ from those
of standard cores. For example, the width of planar cores is larger while the total height is
much smaller. Also the thickness of the legs is in most cases smaller than compared to
standard cores. Therefore the concept of fixed reference dimensions to determine the length
of crack limits yield crack lengths which are not acceptable for this type of core. This part of
IEC 60424 follows another concept which relates the crack length to dimensions of the
surface on which the crack occurs.
Also the concept to determine the maximum area of chips based on the total mating surface
fails in the case of planar cores. The outer legs of planar cores are much thinner than those of
standard cores which makes overlapping and gluing much more difficult. A single chip of
maximum size on the outer leg may risk the functionality of the core set. Therefore this
standard uses as a reference the mating surface on which the chip occurs.
Windings of planar cores are often PCB’s which are glued to the inner surfaces of the planar
core. For this reason the inner surfaces of the planar cores need to have a better quality than
the inner surfaces of standard cores. This was taken into account by reducing the maximum
allowable area of pull outs in the inner surfaces.
This standard is considered as a sectional specification useful in the negotiation between
ferrite core manufacturers and users about surface irregularities.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60424-1, Ferrite cores – Guide on the limits of surface irregularities – Part 1: General
specification
IEC 62317-9, Ferrite cores – Dimensions – Part 9: Planar-cores
– 6 – 60424-5 © IEC:2009(E)
3 Limits of surface irregularities
3.1 Chips and ragged edges
3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2 and 3)
Mating surfaces
C1′
C1
Ragged edges
IEC 360/09
Figure 1 – Chip location for planar EL-core
Mating surfaces
C1′
C2
C1
Ragged edges
IEC 361/09
Figure 2 – Chip location for low profile E-core
Mating surfaces
C1′
C2
Wire slot area
C1
Ragged edges
IEC 362/09
Figure 3 – Chip location for low profile ER-core
Areas of the chips located on the mating surfaces (C1 and C1’ irregularities in Figures 1, 2
and 3) shall not exceed the following limits:
– the cumulative area of the chips shall be less than 4 % of the relevant mating surface. The
mating surface of each outer leg and centre post is considered separately; the allowable
areas are rounded to the figures in Table 4 (Area and length reference for visual
inspection) and the minimum allowable area is taken as 0,5 mm to be distinguishable to
the naked eye;
60424-5 © IEC:2009(E) – 7 –
– the total area of all chips on all mating surfaces shall not exceed the value given for
“overall chipping on the mating surface” in Tables 1, 2 or 3;
– the total length of the ragged edges shall be less than 25 % of the perimeter of the
relevant mating surface.
3.1.2 Chips and ragged edges on other surfaces
– the allowable chipping areas are doubled as compared to the limits for the whole mating
surfaces (see Table 1 for planar EL-corers, Table 2 for low profile E-cores, Table 3 for low
profile ER-cores);
– the total length of the ragged edges shall be less than 25 % of the perimeter of the smaller
adjoini
...
IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
Noyaux de ferrite – Guide relatif aux limites des irrégularités de surface –
Partie 5: Noyaux planaires
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by
any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either IEC or
IEC's member National Committee in the country of the requester.
If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication,
please contact the address below or your local IEC member National Committee for further information.
Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduite
ni utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopie
et les microfilms, sans l'accord écrit de la CEI ou du Comité national de la CEI du pays du demandeur.
Si vous avez des questions sur le copyright de la CEI ou si vous désirez obtenir des droits supplémentaires sur cette
publication, utilisez les coordonnées ci-après ou contactez le Comité national de la CEI de votre pays de résidence.
IEC Central Office
3, rue de Varembé
CH-1211 Geneva 20
Switzerland
Email: inmail@iec.ch
Web: www.iec.ch
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.
About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.
ƒ Catalogue of IEC publications: www.iec.ch/searchpub
The IEC on-line Catalogue enables you to search by a variety of criteria (reference number, text, technical committee,…).
It also gives information on projects, withdrawn and replaced publications.
ƒ IEC Just Published: www.iec.ch/online_news/justpub
Stay up to date on all new IEC publications. Just Published details twice a month all new publications released. Available
on-line and also by email.
ƒ Electropedia: www.electropedia.org
The world's leading online dictionary of electronic and electrical terms containing more than 20 000 terms and definitions
in English and French, with equivalent terms in additional languages. Also known as the International Electrotechnical
Vocabulary online.
ƒ Customer Service Centre: www.iec.ch/webstore/custserv
If you wish to give us your feedback on this publication or need further assistance, please visit the Customer Service
Centre FAQ or contact us:
Email: csc@iec.ch
Tel.: +41 22 919 02 11
Fax: +41 22 919 03 00
A propos de la CEI
La Commission Electrotechnique Internationale (CEI) est la première organisation mondiale qui élabore et publie des
normes internationales pour tout ce qui a trait à l'électricité, à l'électronique et aux technologies apparentées.
A propos des publications CEI
Le contenu technique des publications de la CEI est constamment revu. Veuillez vous assurer que vous possédez
l’édition la plus récente, un corrigendum ou amendement peut avoir été publié.
ƒ Catalogue des publications de la CEI: www.iec.ch/searchpub/cur_fut-f.htm
Le Catalogue en-ligne de la CEI vous permet d’effectuer des recherches en utilisant différents critères (numéro de référence,
texte, comité d’études,…). Il donne aussi des informations sur les projets et les publications retirées ou remplacées.
ƒ Just Published CEI: www.iec.ch/online_news/justpub
Restez informé sur les nouvelles publications de la CEI. Just Published détaille deux fois par mois les nouvelles
publications parues. Disponible en-ligne et aussi par email.
ƒ Electropedia: www.electropedia.org
Le premier dictionnaire en ligne au monde de termes électroniques et électriques. Il contient plus de 20 000 termes et
définitions en anglais et en français, ainsi que les termes équivalents dans les langues additionnelles. Egalement appelé
Vocabulaire Electrotechnique International en ligne.
ƒ Service Clients: www.iec.ch/webstore/custserv/custserv_entry-f.htm
Si vous désirez nous donner des commentaires sur cette publication ou si vous avez des questions, visitez le FAQ du
Service clients ou contactez-nous:
Email: csc@iec.ch
Tél.: +41 22 919 02 11
Fax: +41 22 919 03 00
IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
Noyaux de ferrite – Guide relatif aux limites des irrégularités de surface –
Partie 5: Noyaux planaires
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
N
CODE PRIX
ICS 29.100.10 ISBN 978-2-88910-190-0
– 2 – 60424-5 © IEC:2009
CONTENTS
FOREWORD.3
1 Scope.5
2 Normative references .5
3 Limits of surface irregularities.6
3.1 Chips and ragged edges.6
3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2
and 3).6
3.1.2 Chips and ragged edges on other surfaces.7
3.2 Cracks.10
3.3 Flash.10
3.4 Pull-out .10
Figure 1 – Chip location for planar EL-core.6
Figure 2 – Chip location for low profile E-core.6
Figure 3 – Chip location for low profile ER-core .6
Figure 4 – Cracks and pull-out location for planar EL-core .10
Figure 5 – Cracks and pull-out location for low profile E-core.11
Figure 6 – Cracks and pull-out location for low profile ER-core .11
Figure 7 – Reference dimensions for EL-core .11
Figure 8 – Reference dimensions for E-core .12
Figure 9 – Reference dimensions for ER-core.13
Table 1 – Allowable areas of chips in mm for planar EL-core.7
Table 2 – Allowable areas of chips in mm for low profile E-core .8
Table 3 – Allowable areas of chips in mm for low profile ER-core .8
Table 4 – Area and length reference for visual inspection .9
Table 5 – Limits of cracks for planar EL-core .12
Table 6 – Limits of cracks for low profile E-core.13
Table 7 – Limits of cracks for low profile ER-core .14
60424-5 © IEC:2009 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –
Part 5: Planar-cores
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)“). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60424-5 has been prepared by IEC technical committee 51:
Magnetic components and ferrite materials.
This bilingual version, published in 2009-07, corresponds to the English version.
The text of this standard is based on the following documents:
FDIS Report on voting
51/947/FDIS 51/950/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The French version of this standard has not been voted upon.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
– 4 – 60424-5 © IEC:2009
A list of all parts of the IEC 60424 series, under the general title Ferrite cores – Guide on the
limits of surface irregularities, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
60424-5 © IEC:2009 – 5 –
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –
Part 5: Planar-cores
1 Scope
This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable
to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1.
The relations between the main dimensions of planar E-, ER- and EL-cores differ from those
of standard cores. For example, the width of planar cores is larger while the total height is
much smaller. Also the thickness of the legs is in most cases smaller than compared to
standard cores. Therefore the concept of fixed reference dimensions to determine the length
of crack limits yield crack lengths which are not acceptable for this type of core. This part of
IEC 60424 follows another concept which relates the crack length to dimensions of the
surface on which the crack occurs.
Also the concept to determine the maximum area of chips based on the total mating surface
fails in the case of planar cores. The outer legs of planar cores are much thinner than those of
standard cores which makes overlapping and gluing much more difficult. A single chip of
maximum size on the outer leg may risk the functionality of the core set. Therefore this
standard uses as a reference the mating surface on which the chip occurs.
Windings of planar cores are often PCBs which are glued to the inner surfaces of the planar
core. For thi
...
Questions, Comments and Discussion
Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.