IEC 62386-102:2009

Digital addressable lighting interface - Part 102: General requirements - Control gear

IEC 62386-102:2009 specifies a protocol and methods of test for the control by digital signals of electronic control gear for use on a.c. or d.c. supplies. This Part 102 is intended to be used in conjunction with Part 101, which contains general requirements for the relevant product type (system), and with the appropriate part 2XX (particular requirements for control gear) containing clauses to supplement or modify the corresponding clauses in Parts 101 and 102 in order to provide the relevant requirements for each type of product. This International Standard, together with IEC 62386-101 and IEC 62386-201, replaces Clause E.4, "Control by digital signals", and Annex G, "Test procedures for ballasts with digital control interface according to Clause E.4", of IEC 60929:2006.

Interface d'éclairage adressable numérique - Partie 102: Exigences générales - Appareillages de commande

La CEI 62386-102:2009 spécifie un protocole et des méthodes d'essai pour la commande par signaux numériques des appareillages de commande électroniques destinés à être utilisés dans les alimentations alternatives ou continues. La présente Partie 102 est destinée à être utilisée conjointement avec la Partie 101 appropriée, qui contient les exigences générales pour le type de produit applicable (système), et avec la partie 2XX appropriée (exigences particulières pour les appareillages) qui comporte les articles complétant ou modifiant les articles correspondants de la Partie 101 et Partie 102, afin d'établir les règles complètes pour chaque type de produit. La présente Norme internationale, ainsi que la CEI 62386-101 et la CEI 62386-201, remplacent l'Article E.4 "Commande par signaux numériques" et l'Annexe G "Procédures d'essai pour les ballasts avec interface de commande numérique selon l'Article E.4" de la CEI 60929:2006.

General Information

• Status: Published
• Publication Date: 08-Jun-2009
• ICS: 29.140.50 - Lighting installation systems
• ICS: 29.140.99 - Other standards related to lamps
• Technical Committee: SC 34C - Auxiliaries for lamps
• Drafting Committee: PT 62386 - TC 34/SC 34C/PT 62386
• Current Stage: DELPUB - Deleted Publication
• Completion Date: 07-Nov-2014

Relations

• Revised: IEC 62386-102:2014 - Digital addressable lighting interface - Part 102: General requirements - Control gear
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 62386-102
®
Edition 1.0 2009-06
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE


Digital addressable lighting interface –
Part 102: General requirements – Control gear

Interface d’éclairage adressable numérique –
Partie 102: Exigences générales – Appareillages de commande

IEC 62386-102:2009

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IEC 62386-102
®
Edition 1.0 2009-06
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE


Digital addressable lighting interface –
Part 102: General requirements – Control gear

Interface d’éclairage adressable numérique –
Partie 102: Exigences générales – Appareillages de commande

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
XF
CODE PRIX
ICS 29.140.50; 29.140.99 ISBN 978-2-88910-687-5
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

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– 2 – 62386-102 © IEC:2009
CONTENTS
FOREWORD.7
INTRODUCTION.9
1 Scope.10
2 Normative references .10
3 Terms and definitions .10
4 General .12
5 Electrical specification.12
6 Interface power supply .12
7 Transmission protocol structure.12
7.1 General .12
7.2 Forward frame.12
7.2.1 Address byte ‘YAAA AAAS’ .12
7.2.2 Data byte ‘XXXX XXXX’.13
7.3 Backward frame .13
8 Timing .13
8.1 Information bit timing.13
8.2 Forward frame timing .14
8.3 Backward frame timing .15
8.4 Frame sequence timing .15
9 Method of operation .16
9.1 Logarithmic dimming curve, arc power levels and accuracy .16
9.2 Power-on.19
9.3 Interface-failure.19
9.4 Min and max level .19
9.5 Fade time and fade rate .20
9.6 Reaction to commands during error state .20
9.7 Behaviour during lamp preheating and lamp ignition time .21
9.8 Memory access and memory map .21
9.8.1 Memory access commands.21
9.8.2 Memory map.21
10 Declaration of variables .24
11 Definition of commands .25
11.1 Arc power control commands.25
11.1.1 Direct arc power control command:.25
11.1.2 Indirect arc power control commands .26
11.2 Configuration commands:.28
11.2.1 General configuration commands: .28
11.2.2 Arc power parameters settings: .28
11.2.3 System parameters settings .30
11.3 Query commands .30
11.3.1 Queries related to status information .30
11.3.2 Queries related to arc power parameter settings.32
11.3.3 Queries related to system parameter settings .32
11.3.4 Application extended commands .33
11.4 Special Commands .33

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62386-102 © IEC:2009 – 3 –
11.4.1 Terminate special processes .33
11.4.2 Download information to the DTR .34
11.4.3 Addressing commands .34
11.4.4 Extended special commands .35
11.5 Summary of the command set .38
12 Test procedures .40
12.0 General .40
12.1 Test sequences 'Physical operational parameters’.44
12.1.1 Test sequences 'Waveform' .44
12.1.2 Test sequence 'Frame structure timing' .53
12.1.3 Insulation test.54
12.1.4 Optional test sequences .54
12.1.5 Test sequence 'Response time' .56
12.2 Test sequences 'Configuration commands' .57
12.2.1 Test sequences 'General configuration commands'.57
12.2.2 Test sequences 'Arc power parameter settings' .70
12.2.3 Test sequences 'System parameter settings' .80
12.2.4 Test sequences 'Memory Access' .84
12.3 Test sequences 'Arc power control commands'.88
12.3.1 Test sequences 'Timing' .88
12.3.2 Test sequences 'Dimming curve'.90
12.3.3 Test sequences 'Arc power commands' .95
12.4 Test sequence 'Physical address allocation' .105
12.5 Test sequences 'Random address allocation' .106
12.5.1 Test sequences 'INITIALISE / TERMINATE'.106
12.5.2 Test sequences 'RANDOMISE' .112
12.5.3 Test sequences 'COMPARE / WITHDRAW' .115
12.5.4 Test sequences 'PROGRAM / VERIFY / QUERY SHORT ADDRESS' . 118
12.6 Test sequences 'Queries and reserved commands' .124
12.6.1 Test sequences 'Queries' .124
12.6.2 Test sequences 'Reserved commands' . 131
Annex A (informative) Examples of algorithms .136
Annex B (normative) List of device types .138
Bibliography.139

Figure 1 – Bi-phase coded "1".14
Figure 2 – Symbols for bi-phase levels: “1”;”0”.14
Figure 3 – Forward frame.14
Figure 4 – Forward frame timing .15
Figure 5 – Backward frame .15
Figure 6 – Backward frame timing.15
Figure 7 – Example of frame sequence timing.16
Figure 8 – Transition from forward to backward frames.16
Figure 9 – Transition from backward to forward and from forward to forward frames .16
Figure 10 – The logarithmic dimming curve with a minimum arc power of 0,1 %.17
Figure 11 – Configuration commands timing .28
Figure 12 – General test structure.40

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– 4 – 62386-102 © IEC:2009
Figure 13 – Activation state and test state .41
Figure 14 – Test sequence 'Current rating'.45
Figure 15 – Test sequence 'Voltage rating’ .46
Figure 16 – Test sequence 'Back channel rise time / fall time’.47
Figure 17 – Test sequence 'Transmission rate' .48
Figure 18 – Test sequence 'Pulse width' .50
Figure 19 – 'Code violation'.51
Figure 20 – Waveforms for test 'Code violation': .52
Figure 21 – Test sequence 'Frame structure timing' .53
Figure 22 – Test sequence 'Polarity' .54
Figure 23 – Test sequence 'Overvoltage protection' .55
Figure 24 – Test sequence 'Response time' .56
Figure 25 – Test sequence 'RESET'.57
Figure 26 – Test sequence 'RESET: timeout / command in-between' .59
Figure 27 – Test sequence '100 ms-timeout' .60
Figure 28 – Test sequence 'Commands in-between'.62
Figure 29 – Test sequence 'QUERY VERSION NUMBER' .64
Figure 30 – Test sequence 'STORE ACTUAL LEVEL IN THE DTR' .65
Figure 31 – Test sequence 'Persistent memory' .66
Figure 32 – Test sequence 'DTR1' .68
Figure 33 – Test sequence 'DTR2' .69
Figure 34 – Test sequence 'STORE THE DTR AS MAX LEVEL' .70
Figure 35 – Test sequence 'STORE THE DTR AS MIN LEVEL' .71
Figure 36 – Test sequence 'STORE THE DTR AS SYSTEM FAILURE LEVEL' .73
Figure 37 – Test sequence 'STORE THE DTR AS POWER ON LEVEL' .75
Figure 38 – Test sequence 'STORE THE DTR AS FADE TIME'.77
Figure 39 – Test sequence 'STORE THE DTR AS FADE RATE'.78
Figure 40 – Test sequence 'STORE THE DTR AS SCENE' / 'GO TO SCENE' .79
Figure 41 – Test sequence 'REMOVE FROM SCENE'.80
Figure 42 – Test sequence 'ADD TO GROUP' / 'REMOVE FROM GROUP' .81
Figure 43 – Test sequence 'STORE THE DTR AS SHORT ADDRESS'.83
Figure 44 – Test sequence 'Memory Bank 0'.84
Figure 45 – Test sequence 'Memory Bank 1'.85
Figure 46 – Test sequence 'Other Memory Banks' .86
Figure 47 – Test sequence 'ENABLE WRITE MEMORY' .87
Figure 48 – Test sequence 'FADE TIME'.88
Figure 49 – Test sequence 'FADE RATE'.89
Figure 50 – Test sequence 'Logarithmic dimming curve' .90
Figure 51 – Test sequence 'Dimming curve: DIRECT ARC POWER CONTROL'.91
Figure 52 – Test sequence 'Dimming curve: UP / DOWN' .92
Figure 53 – Test sequence 'Dimming curve: STEP UP / STEP DOWN'.93
Figure 54 – Test sequence 'Dimming curve: DAPC SEQUENCE' .94
Figure 55 – Test sequence 'OFF' .95

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62386-102 © IEC:2009 – 5 –
Figure 56 – Test sequence 'DIRECT ARC POWER CONTROL'.96
Figure 57 – Test sequence 'UP' .97
Figure 58 – Test sequence 'DOWN' .98
Figure 59 – Test sequence 'STEP UP' .99
Figure 60 – Test sequence 'STEP DOWN' .100
Figure 61 – Test sequence 'RECALL MAX LEVEL'.101
Figure 62 – Test sequence 'RECALL MIN LEVEL'.102
Figure 63 – Test sequence 'ON AND STEP UP' .103
Figure 64 – Test sequence 'STEP DOWN AND OFF' .104
Figure 65 – Test sequence 'Physical address allocation'.105
Figure 66 – Test sequence 'INITIALISE: 15 minutes timer'.106
Figure 67 – Test sequence 'TERMINATE' .107
Figure 68 – Test sequence 'INITIALISE: short address'.108
Figure 69 – Test sequence 'INITIALISE: no short address'. 109
Figure 70 – Test sequence 'INITIALISE: 100 ms timeout' .110
Figure 71 – Test sequence 'INITIALISE: command in-between'.111
Figure 72 – Test sequence 'RANDOMISE: reset values'.112
Figure 73 – Test sequence 'RANDOMISE: 100 ms timeout'.113
Figure 74 – Test sequence 'RANDOMISE: command in-between' .114
Figure 75 – Test sequence 'COMPARE' .115
Figure 76 – Test sequence 'WITHDRAW' .117
Figure 77 – Test sequence 'PROGRAM SHORT ADDRESS' .119
Figure 78 – Test sequence 'VERIFY SHORT ADDRESS' .120
Figure 79 – Test sequence' QUERY SHORT ADDRESS'.122
Figure 80 – Test sequence 'SEARCH ADDRESS: reset value' .123
Figure 81 – Test sequence 'QUERY DEVICE TYPE' .124
Figure 82 – Test sequence 'QUERY LAMP FAILURE' .125
Figure 83 – Test sequence 'QUERY LAMP POWER ON'.126
Figure 84 – Test sequence 'QUERY LIMIT ERROR'.127
Figure 85 – Test sequence 'QUERY POWER FAILURE'.128
Figure 86 – Test sequence 'QUERY STATUS: control gear ok' . 129
Figure 87 – Test sequence 'QUERY STATUS: fade running' .130
Figure 88 – Test sequence 'RESERVED: standard commands' .131
Figure 89 – Test sequence 'Application extended commands' . 132
Figure 90 – Test sequence 'RESERVED: special commands 1'. 133
Figure 91 – Test sequence 'RESERVED: special commands 2'. 134
Figure 92 – Test sequence 'Not supported device types'. 135

Table 1 – The logarithmic dimming curve with a minimum arc power of 0,1 %.18
Table 2 – Fade times and fade rates.20
Table 3 – Memory map of memory bank 0.22
Table 4 – Memory map of memory bank 1.23
Table 5 – Memory map of other memory banks.24

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– 6 – 62386-102 © IEC:2009
Table 6 – Declaration of variables.25
Table 7 – Summary of the command set .38
Table 8 – Timing combinations for test sequence 'Pulse width' .49
Table 9 – Parameters for test sequence 'RESET'.58
Table 10 – Parameters for test sequence '100 ms-timeout' .61
Table 11 – Parameters for test sequence 'Commands in-between'.63
Table 12 – Parameters for test sequence 'Persistent memory' .67
Table 13 – Parameters for test sequence 'DTR1' .68
Table 14 – Parameters for test sequence 'DTR2' .69
Table 15 – Parameters for test sequence 'STORE THE DTR AS MAX LEVEL' .70
Table 16 – Parameters for test sequence 'STORE THE DTR AS MIN LEVEL' .71
Table 17 – Parameters for test sequence 'STORE THE DTR AS SYSTEM FAILURE
LEVEL' .72
Table 18 – Parameters for test sequence 'STORE THE DTR AS POWER ON LEVEL'.74
Table 19 – Parameters for test sequence 'STORE THE DTR AS FADE TIME' .76
Table 20 – Parameters for test sequence 'STORE THE DTR AS FADE TIME' .78
Table 21 – Parameters for test sequence 'STORE THE DTR AS FADE TIME' .79
Table 22 – Parameters for test sequence 'ADD TO GROUP' / 'REMOVE FROM
GROUP'.81
Table 23 – Parameters for test sequence 'STORE THE DTR AS SHORT ADDRESS'.82
Table 24 – Parameters for test sequence 'ENABLE WRITE MEMORY'.87
Table 25 – Parameters for test sequence 'FADE TIME' .88
Table 26 – Parameters for test sequence 'FADE RATE' .89
Table 27 – Parameters for test sequence 'Logarithmic dimming curve'.90
Table 28 – Parameters for test sequence 'Dimming curve: DAPC SEQUENCE'.94
Table 29 – Parameters for test sequence 'DIRECT ARC POWER CONTROL' .96
Table 30 – Parameters for test sequence 'COMPARE' .115
Table 31 – Parameters for test sequence 'COMPARE' .116
Table 32 – Parameters for test sequence 'PROGRAM SHORT ADDRESS' . 118
Table 33 – Parameters for test sequence 'QUERY SHORT ADDRESS' . 121
Table 34 – Parameters for test sequence 'QUERY LIMIT ERROR' .127
Table 35 – Parameters for test sequence 'RESERVED: standard commands' . 131
Table 36 – Parameters for test sequence 'RESERVED: special commands 1' . 133
Table 37 – Parameters for test sequence 'RESERVED: special commands 2' . 134
Table B.1 – List of device types .138

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62386-102 © IEC:2009 – 7 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

DIGITAL ADDRESSABLE LIGHTING INTERFACE –

Part 102: General requirements –
Control gear


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