IEC 63373:2022

Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices

IEC 63373:2022 In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. IEC 63373:2022 provides guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following:
a) GaN enhancement and depletion-mode discrete power devices;
b) GaN integrated power solutions;
c) the above in wafer and package levels.
The prescribed test methods can be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.

Lignes directrices pour les méthodes d’essai de résistance dynamique à l’état passant des dispositifs de conversion de puissance fondés sur les HEMT en GaN

IEC 63373:2022 En règle générale, l’essai de résistance dynamique à l’état passant est une mesure des phénomènes de piégeage de charge dans les transistors de puissance en GaN. L'IEC 63373:2022 donne des lignes directrices pour l’essai de résistance dynamique à l’état passant des solutions de transistors de puissance latéraux en GaN. Les méthodes d’essai peuvent être appliquées aux éléments suivants:
a) dispositifs de puissance discrets en GaN à mode d’enrichissement et de déplétion;
b) solutions de puissance intégrées en GaN;
c) dispositifs et solutions ci-dessus au niveau des plaquettes et des boîtiers.
Les méthodes d’essai spécifiées peuvent être utilisées pour la caractérisation des dispositifs, les essais de production, les évaluations de fiabilité et les évaluations de l’application des dispositifs de conversion de puissance en GaN. Le présent document n’est pas destiné à couvrir les mécanismes sous-jacents de la résistance dynamique à l’état passant et sa représentation symbolique pour les spécifications du produit.

General Information

• Status: Published
• Publication Date: 09-Feb-2022
• ICS: 31.080.99 - Other semiconductor devices
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 5 - TC 47/WG 5
• Current Stage: PPUB - Publication issued
• Start Date: 10-Mar-2022
• Completion Date: 10-Feb-2022

Standards Content (Sample)

IEC 63373
®

Edition 1.0 2022-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside


Dynamic on-resistance test method guidelines for GaN HEMT based power
conversion devices

Lignes directrices pour les méthodes d’essai de résistance dynamique à l’état
passant des dispositifs de conversion de puissance fondés sur les HEMT en
GaN

IEC 63373:2022-02(en-fr)

---------------------- Page: 1 ----------------------
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IEC 63373

®


Edition 1.0 2022-02




INTERNATIONAL



STANDARD




NORME


INTERNATIONALE
colour

inside










Dynamic on-resistance test method guidelines for GaN HEMT based power

conversion devices



Lignes directrices pour les méthodes d’essai de résistance dynamique à l’état

passant des dispositifs de conversion de puissance fondés sur les HEMT en

GaN















INTERNATIONAL

ELECTROTECHNICAL

COMMISSION


COMMISSION

ELECTROTECHNIQUE


INTERNATIONALE




ICS 31.080.99 ISBN 978-2-8322-1076-6




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® Registered trademark of the International Electrotechnical Commission
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– 2 – IEC 63373:2022 © IEC 2022
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms, definitions, symbols and abbreviated terms . 6
3.1 Terms and definitions . 6
3.2 Symbols and abbreviated terms . 6
4 Test circuits and waveforms . 7
4.1 General . 7
4.2 Inductive and resistive switching methods . 7
4.3 Pulsed current-voltage (I-V) method . 10
5 Requirements . 12
Bibliography . 14

Figure 1 – Inductive-resistive load “double-pulse” test circuit for hard-switching
evaluation . 8
Figure 2 – Depiction of the hard-switching “double-pulse” test circuit (showing its
similarity to a boost converter) . 8
Figure 3 – Simplified flowchart for inductive and/or resistive switching based dynamic
on-resistance test . 9
Figure 4 – Representative continuous-pulse hard-switching waveforms for measuring
dynamic on-resistance using the test circuits in Figure 1 and Figure 2 . 10
Figure 5 – Example test circuit for soft-switching on-resistance measurement (the gate
and drain terminals are pulsed with independent voltage signals) . 10
Figure 6 – Simplified flowchart for soft switching based dynamic on-resistance test . 11
Figure 7 – Illustrative timing diagram for measuring dynamic ON-resistance under
OFF-state stress in soft-switching mode . 12

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IEC 63373:2022 © IEC 2022 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES
FOR GaN HEMT BASED POWER CONVERSION DEVICES

FOREWORD
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IEC 63373 has been prepared by IEC technical committee 47: Semiconductor devices. It is an
International Standard.
1
This standard is based upon JEP173 [1]. It is used with permission of the copyright holder,
JEDEC Solid State Technology Association.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2690/CDV 47/2735/RVC

Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
___________
1
 Numbers in square brackets refer to the Bibliography.

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– 4 – IEC 63373:2022 © IEC 2022
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
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IEC 63373:2022 © IEC 2022 – 5 –
INTRODUCTION
This document is intended for use in the GaN power semiconductor and related power electronic
industries, and provides guidelines for measuring the dynamic ON-resistance of GaN power
devices.
Gallium Nitride (GaN) lateral power High Electron Mobility Transistor (HEMT) conducts through
a two-dimensional electron gas (2DEG) in ON-state operation. Due to the various stress
conditions that the device encounters during power electronic switching applications, some
charge could get trapped in specific regions of the transistor structure. The trapped electrons
cause an increased ON-resistance when operated in a switching environment. This
phenomenon is known as current collapse and the ON-resistance at switching operation is
called dynamic ON-resistance in order to distinguish from DC ON-resistance. Increased
dynamic ON-resistance translates to higher power loss, thereby reducing overall system
efficiency. Not verifying the dynamic ON-resistance characteristic can put GaN device reliability
at risk [2].
The test methods provided in this document can be used as a guideline for measuring dynamic
ON-resistance of GaN power device, focused on lateral HEMT technologies. These three test
methods can be applied for datasheet, process control, technology development, final tests and
other usage. Parasitic effects impact high precision measurements and wafer level tests can
minimize parasitic effects. Additionally, self-heating can impact the package level tests
depending upon the package thermal characteristics.

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– 6 – IEC 63373:2022 © IEC 2022
DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES
FOR GaN HEMT BASED POWER CONVERSION DEVICES



1 Scope
In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN
power transistors. This publication provides guidelines for testing dynamic ON-resistance of
GaN lateral power transistor solutions. The test methods can be applied to the following:
a) GaN enhancement and depletion-mode discrete power devices [3];
b) GaN integrated power solutions;
c) the above in wafer and package levels.
The prescribed test methods can be used for device characterization, production testing,
reliability evaluations and application assessments of GaN power conversion devices. This
document is not intended to cover the underlying mechanisms of dynamic ON-resistance and
its symbolic representation for product specifications.
2 Normative references
There are no normative references in this document.
3 Terms, definitions, symbols and abbreviated terms
3.1 Terms and definitions
No terms and definitions are listed in this document.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.2 Symbols and abbreviated terms
Symbol or abbreviation Name or term
DUT Device Under Test
Supply voltage
V
DD
Drain to Source Voltage of DUT
V
DS
Gate to Source Voltage of DUT
V
GS
D1 Free-wheeling diode
Inductance
L
Resistance
R
Capacitance
C
Drain current of DUT in ON-state
I
D
Drain to Source Voltage of DUT in ON-state
V
DS(ON)
Drain to Source Resistance of DUT in ON-state
R
DS(ON)

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IEC 63373:2022 © IEC 2022 – 7 –
Symbol or abbreviation Name or term
Drain to source voltage of DUT in OFF-state
V
DS(OFF)
Gate to source voltage of DUT in ON-state
V
GS(ON)
Gate to source voltage of DUT in OFF-state
V
GS(OFF)
OFF-state pulse width
t
off
ON-state pulse width
t
on
measurement timing in ON-pulse
t
m,on
Soft-switching delay time between the OFF and ON pulse or vice-versa, with
t
dn
n = 1 or 2
Frequency
f
Number of pulses
N
Case temperature
T
C
Instantaneous peak power, applicable for only hard switching
P
Peak
Energy dissipated per pulse, applicable for only hard switching
E
Pulse

4 Test circuits and waveforms
4.1 General
GaN power transistors typically are being targeted for both hard and soft-switching topologies
for power conversion applications.
Hard switching conditions refer to the overlap of the voltage and current waveforms when the
power device switches either from ON-to-OFF or OFF-to-ON states. Typical hard-switching
topologies include totem-pole Power Factor Correction (PFC) boost converters, buck converters,
motor control inverter and single ended fly-back circuits.
Soft switching conditions refer to conditions where there is no or minimal overlap of the voltage
and current waveforms when the GaN power device switches between the ON- and OFF-states.
Typical soft-switching topologies include Zero Voltage Switching (ZVS) converters, LLC
converters, Active Clamp Fly-back (ACF), etc.
Resistive load switching is another type that is not typically seen in the power electronic
applications whose overlap of voltage and current waveforms fall in between the hard and soft
switching types. However, the easier implementation of this switching type makes it attractive
for the device level characterization and testing purposes.
As described above, current-voltage loci are the crux that determines the switching type. The
loci of above three switching types are explained with great detail in here [4]. The following 4.2
and 4.3 cover the dynamic ON-resistance measurement methods for these three switching
types.
Minimizing parasitic effects when performing high precision measurements is recommended.
Wafer level tests can be used to minimize parasitic effects when performing high precision
measurements. For package level tests, the impact of package thermal characteristics should
be considered so as to minimize any device under test (DUT) self-heating implications.
4.2 Inductive and resistive switching methods
A hard-switching inductive and resistive loaded test vehicle that is analogous to what is
generally termed the “double-pulse” tester in power electronic applications [2] is shown in

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– 8 – IEC 63373:2022 © IEC 2022
Figure 1. Another depiction of the double-pulse tester is shown in Figure 2, which illustrates
that the double-pulse tester is equivalent to a boost converter with the input tied to the output
[5]; note that R = 0 in this depiction.
Load

Figure 1 – Inductive-resistive load “double-pulse” test circuit for hard-switching
evaluation

Figure 2 – Depiction of the hard-switching “double-pulse” test circuit (showing its
similarity to a boost converter)
When a power transistor switches at high voltages, measuring the drain-to-source ON-state
voltage with a passive probe in combination with an oscilloscope can be quite challenging, as
the oscilloscope’s dynamic-range precision may not be adequate. As an example, consider a
device with an ON-state voltage of 0,5 V at 1 A of drain current switching from 400 V in the
OFF-state. An 8-bit oscilloscope configured to measure the 400 V OFF-state voltage will have
8
a resolution of 1,562 5 V (= 400/2 ), which is not sufficient to measure the 0,5 V ON-state
voltage. The measurable voltage has an error of more than 3 times the actual voltage in this
example and this further increase to 30 times to detect a 10 % dynamic ON-state voltage drift.
To circumvent such problems, a circuit may be employed to clamp the high OFF-state voltage
on a low-voltage measurement probe without compromising the ON-state voltage.
Since the clamped sampling circuit reduces the voltage swing quite significantly on the
measurement probe, the dynamic ON-state voltage of the power transistor can be effectively
measured, from which its dynamic ON-resistance is calculated using Ohm’s law. Some
examples of voltage clamp sampling circuits are reported in [6] and [7].

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IEC 63373:2022 © IEC 2022 – 9 –
It is to be noted that if R = 0 in Figure 1 (which makes the circuits of Figure 1 and Figure 2
Load
identical), the circuit is nothing but a standard power electronics double-pulse or boost test
circuit. The hard-switching circuits presented in Figure 1 and Figure 2 provide the flexibility of
running tests either in single-pulse, double-pulse or continuous-pulse modes. They provide high
impedance on the drain, which lowers V without the need for an additional synchronized
DS
tester resource. A high impedance may also be achieved by setting L = 0 and using a high-
value resistor making this a pure resistive switching. The single and double-pulse test modes
are often advantageous in production environments where fast switching characterization is
needed, whereas the continuous-pulse test mode is beneficial for longer-term device
characterization and reliability evaluation. The flow chart for inductive and/or resistive switching
load-based measurement is presented in Figure 3, and Figure 4 shows the representative hard-
switching waveforms of a GaN power transistor in the Figure 1 and Figure 2 test circuits when
subjected to continuous gate pulses. In a pure resistive switching load test circuit, the DUT
current in ON-state stays constant unlike the inductive load circuit where the current increases
linearly with time. A high-performance clamp circuit design may be required to measure the
drain-to-source dynamic ON-resistance in <1 µs after the device transitions from the OFF-state
to the ON-state. The R is evaluated dynamically during the period when the transistor
DS(ON)
gate is ON as R = V /I .
DS(ON) DS(ON) D

Figure 3 – Simplified flowchart for inductive and/or resistive switching based dynamic
on-resistance test

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– 10 – IEC 63373:2022 © IEC 2022

Figure 4 – Representative continuous-pulse hard-switching waveforms for measuring
dynamic on-resistance using the test circuits in Figure 1 and Figure 2
4.3 Pulsed current-voltage (I-V) method
The pulsed I-V technique is analogous to soft switching, which is widely used in GaN RF
electronics. This method involves pulsing the gate and drain voltage signals independently, and
hence is branded as a classic “double pulse” technique in the RF world, thus potentially leading
to confusion since this term is used in the power electronics world to refer to a hard-switching
test, as discussed above. Using this approach, a few manufacturers have developed systems
to fulfil power electronic requirements [8]. Figure 5 and Figure 6 provide simplified test setup
and test flow respectively for soft switching.

Figure 5 – Example test circuit for soft-switching on-resistance measurement
(the gate and drain terminals are pulsed with independent voltage signals)

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IEC 63373:2022 © IEC 2022 – 11 –

Figure 6 – Simplified flowchart for soft switching based dynamic on-resistance test
As illustrated in Figure 7, the gate is initially pulsed ON while the drain is pulsed to a low value
V such that the transistor is in the linear region of operation, where the ON-resistance
DS(ON)
may be evaluated as R = V /I . After a pause t where gate and drain voltage are
DS(ON) DS(ON) D d1
both zero, the drain is set to a high stress value while the gate remains OFF for a time toff.
Subsequently, after a second wait period t where both gate and drain are again both zero,
d2
the ON-state gate and drain signals are repeated and the R is again measured. This
DS(ON)
measured R is compared to the initially measured value to see if any change has occurred
DS(ON)
due to the high drain voltage stress. This procedure may be repeated, with the drain stress
voltage stepped to a higher value between each R measurement. Note that the stress
DS(ON)
time t , represents both the DC and pulsed states. As an example, the DC state can correspond
off
to reliability stress time in qualification. On the other hand, the pulsed state may correspond to
soft-switching applications. Similar methods may be employed with continuous switching of both
gate and drain pulses with a definite frequency. The soft switching test methods described
above may be applied for wafer and package level characterization, and reliability evaluations.

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– 12 – IEC 63373:2022 © IEC 2022

NOTE Measurement windows are interleaved with stress periods.
Figure 7 – Illustrative timing diagram for measuring dynamic ON-resistance under OFF-
state stress in soft-switching mode
5 Requirements
The list below provides the critical parameters whose numerical values are required to be
recorded:
V Supply voltage;
DD
T Case temperature;
C
Drain current of DUT in ON-state;
I
D
t OFF-state pulse width;
off
t ON-state pulse width;
on
t Measurement timing in ON-pulse;
m,on
t Delay time between the OFF and ON pulse or vice-versa, with n = 1 or 2, applicable only
dn
for soft switching;
f Frequency;
N Number of pulses;
P Instantaneous peak power (optional), applicable only for hard switching;
Peak
E Energy dissipated per pulse (optional), applicable only for hard switching.
Pulse
For a desired target DUT case temperature ‘T ’, it is recommended to minimize self-heating
C
effect to avoid any of its impact on dynamic ON-resistance measurement data. Choosing a low
turn-on duty cycle in the test method will allow the case temperature to be very close to the
DUT junction temperature.

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IEC 63373:2022 © IEC 2022 – 13 –
During all the continuous mode operating tests, it is recommended to note down the time stamps
at which the measurements are performed once the test begins for appropriate interpretation of
results over time.
Provided that the test includes non-continuous switching such as the single-pulse mode or the
traditional double-pulse test mode, it is required that individual ON and OFF pulse widths for
such tests be specified.

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– 14 – IEC 63373:2022 © IEC 2022
Bibliography
[1] JEP173, “DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES FOR GaN HEMT
BASED POWER CONVERSION DEVICES, VERSION 1.0” January 2019
[2] S. Kaneko, M. Kuroda, M. Yanagihara, A. Ikoshi, H. Okita, T. Morita, K. Tanaka, M.
Hikita, Y. Uemoto, S. Takahashi and T. Ueda, “Current-collapse-free Operations up to
850 V by GaN-GIT utilizing Hole Injection from Drain,” Proc. 2015 IEEE ISPSD, pp 41 –
44
[3] Kevin J. Chen, Oliver Häberlen, Alex Lidow, Chun lin Tsai, Tetsuzo Ueda, Yasuhiro
Uemoto, and Yifeng Wu, “GaN-on-Si Power Technology: Devices and Applications,”
IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 779 – 795, March 2017
[4] Jungwoo Joh, Naveen Tipirneni, Sameer Pendharkar, and Srikanth Krishnan, “Current
Collapse in GaN Heterojunction Field Effect Transistors for High-voltage Switching
Applications,” Proc. 2014 IEEE IRPS, pp 6C.5.1 - 6C.5.4
[5] S. R. Bahl, D. Ruiz and D. Seup Lee, “Product-level Reliability of GaN Devices,” Proc.
2016 IEEE IRPS, pp 4A-3-1 - 4A-3-6
[6] J. Everts, P. Jacqmaer, R. Gelagaev, J. Das, M. Germain, J. Van den Keybus and J.
Driesen, “A Hard Switching VIENNA Boost Converter for Characterization of
AlGaN/GaN/AlGaN Power DHFETs,” Proc. 2010 PCIM Europe
[7] B. Lu, T. Palacios, D. Risbud, S. Bahl and D. I. Anderson, “Extraction of Dynamic On-
re
...