IEC 61691-3-3:2001

Behavioural languages - Part 3-3: Synthesis in VHDL

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

General Information

• Status: Withdrawn
• Publication Date: 27-Jun-2001
• Withdrawal Date: 31-May-2011
• ICS: 35.240.50 - IT applications in industry
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 2 - TC 91/WG 2
• Current Stage: WPUB - Publication withdrawn
• Completion Date: 01-Jun-2011

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD
61691-3-3
First edition
2001-06
Behavioural languages –
Part 3-3:
Synthesis in VHDL
Reference number
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60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
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INTERNATIONAL IEC
STANDARD
61691-3-3
First edition
2001-06
Behavioural languages –
Part 3-3:
Synthesis in VHDL
 IEC 2001  Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
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– 2 – 61691-3-3  IEC:2001(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
_________
BEHAVIOURAL LANGUAGES –
Part 3-3: Synthesis in VHDL
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
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Organization for Standardization (ISO) in accordance with conditions determined by agreement between the
two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
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Committees in that sense.
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Standards transparently to the maximum extent possible in their national and regional standards. Any
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equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61691-2-3 has been prepared by IEC technical committee 93:
Design automation.
This standard is based on IEEE Std 1076-3 (1997: Synthesis packages
The text of this standard is based on the following documents:
FDIS Report on voting
93/132/FDIS 93/142/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This standard does not follow the rules for the structure of international standards given in
Part 3 of the ISO/IEC Directives.
IEC 61691 consists of the following parts, under the general title: Behavioural languages:
1)
IEC 61691-1:1997, VHDL language reference manual
IEC 61691-2:2001, Part 2: VHDL multilogic system for model interoperability
———————
1)
The edition 2 with the title: VHSIC hardware description language VHDL (1076a) (under consideration) will
replace it.
61691-3-3  IEC:2001(E) – 3 –
IEC 61691-3-1, Part 3-1: Analog description in VHDL (under consideration)
IEC 61691-3-2:2001, Part 3-2: Mathematical operation in VHDL
IEC 61691-3-4, Part 3-4: Timing expressions in VHDL (under consideration)
IEC 61691-3-5, Part 3-5: Library utilities in VHDL (under consideration)
The committee has decided that the contents of this publication will remain unchanged until
2004. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
– 4 – 61691-3-3  IEC:2001(E)
INTRODUCTION
This standard, 61691-3-3, supports the synthesis and verification of hardware designs, by
defining vector types for representing signed or unsigned integer values and providing
standard interpretations of widely used scalar VHDL values.
This standard includes package bodies, as described in annex A, which are available in
electronic format either on a diskette affixed to the back cover, or as a downloadable file from
the IEC Web Store.
61691-3-3 © IEC:2001(E) - 5 -
BEHAVIOURAL LANGUAGES -
Part 3-3: Synthesis in VHDL
1. Overview
1.1 Scope
This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL
source code. It includes the following:
a) The hardware interpretation of values belonging to the BIT and BOOLEAN types defined by IEEE
Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.
b) A function (STD_MATCH) that provides “don’t care” or “wild card” testing of values based on the
STD_ULOGIC type.
c) Standard functions for representing sensitivity to the edge of a signal.
d) Two packages that define vector types for representing signed and unsigned arithmetic values, and
that define arithmetic, shift, and type conversion operations on those types.
This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages
for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.
1.2 Terminology
The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard
and from which no deviation is permitted (shall equals is required to). The word should is used to indicate
that a certain course of action is preferred but not necessarily required; or that (in the negative form) a cer-
tain course of action is deprecated but not prohibited (should equals is recommended that). The word may
indicates a course of action permissible within the limits of the standard (may equals is permitted).
A synthesis tool is said to accept a VHDL construct if it allows that construct to be legal input; it is said to
interpret the construct (or to provide an interpretation of the construct) by producing something that repre-
sents the construct. A synthesis tool is not required to provide an interpretation for every construct that it
accepts, but only for those for which an interpretation is specified by this standard.
Information on references can be found in Clause 2.

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1.3 Conventions
This standard uses the following conventions:
a) The body of the text of this standard uses boldface to denote VHDL reserved words (such as
downto) and upper case to denote all other VHDL identifiers (such as REVERSE_RANGE or
FOO).
b) The text of the VHDL packages defined by this standard, as well as the text of VHDL examples
and code fragments, is represented in a fixed-width font. All such text represents VHDL reserved
words as lower case text and all other VHDL identifiers as upper case text.
c) In the body of the text, italics denote words or phrases that are being defined by the paragraph in
which they occur.
d) VHDL code fragments not supported by this standard are denoted by an italic fixed-width font.
2. References
This standard shall be used in conjunction with the following publications. When the following standards
are superseded by an approved revision, the revision shall apply.
IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual (ANSI).
IEEE Std 1164-1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability
(Std_logic_1164) (ANSI).
3. Definitions
Terms used in this standard, but not defined in this clause, are assumed to be from IEEE Std 1076-1993 and
IEEE Std 1164-1993.
3.1 argument: An expression occurring as the actual value in a function call or procedure call.
3.2 arithmetic operation: An operation for which the VHDL operator is +, -, *, /, mod, rem, abs, or **.
3.3 assignment reference: The occurrence of a literal or other expression as the waveform element of a sig-
nal assignment statement or as the right-hand side expression of a variable assignment statement.
3.4 don’t care value: The enumeration literal ‘-’ of the type STD_ULOGIC defined by IEEE Std 1164-
1993.
3.5 equality relation: A VHDL relational expression in which the relational operator is =.
3.6 high-impedance value: The enumeration literal ‘Z’ of the type STD_ULOGIC defined by IEEE Std
1164-1993.
3.7 inequality relation: A VHDL relational expression in which the relational operator is /=.
3.8 logical operation: An operation for which the VHDL operator is and, or, nand, nor, xor, xnor, or not.
3.9 metalogical value: One of the enumeration literals ‘U’, ‘X’, ‘W’, or ‘-’ of the type STD_ULOGIC
defined by IEEE Std 1164-1993.
IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway,
NJ 08855-1331, USA.
61691-3-3 © IEC:2001(E) - 7 -
3.10 ordering relation: A VHDL relational expression in which the relational operator is <, <=, >, or >=.
3.11 shift operation: An operation for which the VHDL operator is sll, srl, sla, sra, rol, or ror.
3.12 standard logic type: The type STD_ULOGIC defined by IEEE Std 1164-1993, or any type derived
from it, including, in particular, one-dimensional arrays of STD_ULOGIC or of one of its subtypes.
3.13 synthesis tool: Any system, process, or tool that interprets VHDL source code as a description of an
electronic circuit in accordance with the terms of this standard and derives an alternate description of that
circuit.
3.14 user: A person, system, process, or tool that generates the VHDL source code that a synthesis tool pro-
cesses.
3.15 vector: A one-dimensional array.
3.16 well-defined: Containing no metalogical or high-impedance element values.
4. Interpretation of the standard logic types
This clause defines how a synthesis tool shall interpret values of the standard logic types defined by IEEE
Std 1164-1993 and of the BIT and BOOLEAN types defined by IEEE Std 1076-1993. Simulation tools,
however, shall continue to interpret these values according to the standards in which the values are defined.
4.1 The STD_LOGIC_1164 values
IEEE Std 1164-1993 defines the standard logic type:
type STD_ULOGIC is ( ’U’, -- Uninitialized
’X’, -- Forcing Unknown
’0’, -- Forcing 0
’1’, -- Forcing 1
’Z’, -- High Impedance
’W’, -- Weak Unknown
’L’, -- Weak 0
’H’, -- Weak 1
’-’ -- Don’t care
);
The logical values ‘1’, ‘H’, ‘0’, and ‘L’ are interpreted as representing one of two logic levels, where each
logic level represents one of two distinct voltage ranges in the circuit to be synthesized.
IEEE Std 1164-1993 also defines a resolution function named RESOLVED and a subtype STD_LOGIC that
is derived from STD_ULOGIC by using RESOLVED. The resolution function RESOLVED treats the values
‘0’ and ‘1’ as forcing values that override the weak values ‘L’ and ‘H’ when multiple sources drive the same
signal.
The values ‘U’, ‘X’, ‘W’, and ‘-’ are metalogical values; they define the behavior of the model itself rather
than the behavior of the hardware being synthesized. The value ‘U’ represents the value of an object before
it is explicitly assigned a value during simulation; the values ‘X’ and ‘W’ represent forcing and weak values,
respectively, for which the model is not able to distinguish between logic levels.
The value ‘-’ is also called the don’t care value. This standard treats it in the same way as the other metalog-
ical values except when it is furnished as an argument to the STD_MATCH functions in the

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61691-3-3 © IEC:2001(E)
IEEE.NUMERIC_STD package. The STD_MATCH functions use ‘-’ to implement a “match all” or “wild
card” matching.
The value ‘Z’ is called the high-impedance value, and represents the condition of a signal source when that
source makes no effective contribution to the resolved value of the signal.
4.2 Static constant values
Wherever a synthesis tool accepts a reference to a locally static or globally static named constant, it shall
treat that constant as th
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