IEC TS 62878-2-4:2015

Device embedded substrate - Part 2-4: Guidelines - Test element groups (TEG)

IEC TS 62878-2-4:2015 describes the test element group devices useful when measuring basic properties of device embedded substrates. It is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.

Substrat avec appareil(s) intégré(s) - Partie 2-4: Directives - Groupes d'éléments d'essai (TEG)

L'IEC TS 62878-2-4:2015 décrit les appareils du groupe d'éléments d'essai utiles pour mesurer les propriétés de base des substrats avec appareil(s) intégré(s). Il est applicable aux substrats avec appareil(s) intégré(s) fabriqués à partir de matériaux de base organiques, y compris par exemple les appareils actifs ou passifs, les composants discrets formés lors du processus de fabrication d'une carte de câblage électronique, ainsi que les composants de feuilles minces.

General Information

• Status: Published
• Publication Date: 26-Mar-2015
• ICS: 31.180 - Printed circuits and boards
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 6 - TC 91/WG 6
• Current Stage: PPUB - Publication issued
• Start Date: 27-Mar-2015
• Completion Date: 15-Mar-2015

Standards Content (Sample)

IEC TS 62878-2-4 ®
Edition 1.0 2015-03
TECHNICAL
SPECIFICATION
SPECIFICATION
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-4: Guidelines – Test element groups (TEG)

Substrat avec appareil(s) intégré(s) –
Partie 2-4: Directives – Groupes d'éléments d'essai (TEG)

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IEC TS 62878-2-4 ®
Edition 1.0 2015-03
TECHNICAL
SPECIFICATION
SPECIFICATION
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-4: Guidelines – Test element groups (TEG)

Substrat avec appareil(s) intégré(s) –

Partie 2-4: Directives – Groupes d'éléments d'essai (TEG)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-2435-9

– 2 – IEC TS 62878-2-4:2015 © IEC 2015
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references. 7
3 Terms, definitions and abbreviations . 7
3.1 Terms and definitions . 7
3.2 Abbreviations . 7
4 Test conditions and sample preparation . 7
4.1 General . 7
4.2 Test conditions . 7
4.2.1 Classification of tests and evaluation . 7
4.2.2 Measuring environment . 8
4.2.3 Test methods . 8
4.3 Test specimens and number of specimens . 8
4.3.1 Specimen. 8
4.3.2 Number of specimens. 9
4.3.3 Test report . 9
5 TEG . 9
5.1 Preparation of the TEG. 9
5.2 Structures of TEG . 17
5.3 Test pattern guide . 18
5.3.1 Test items . 18
5.3.2 Area array arrangement of TEG for an active device . 19
5.3.3 Peripheral arrangement of TEG . 20
5.3.4 TEG size for active devices . 23
5.3.5 TEG for passive devices. 24
5.3.6 Complex test pattern for the area arrangement, TEG-A . 24
5.3.7 Complex pattern for area arrangement of TEG-B . 27
5.3.8 Complex test pattern for peripheral arrangement . 29
5.3.9 Complex test pattern for passive components . 30
5.3.10 Guide of measurement terminals of a complex test pattern for an active
device . 33
5.3.11 Terminal arrangement using complex patterns . 34
Bibliography . 36

Figure 1 – Area array arrangement – TEG for conductor resistivity and via-to-via
insulation . 10
Figure 2 – Area array arrangement – TEG for insulation measurement of resistance
between conductors and insulation resistance between layers . 11
Figure 3 – Chip arrangement in a shot . 12
Figure 4 – Shot arrangement in a wafer . 13
Figure 5 – Pitch chip specification of peripheral terminal of 60µm TEG . 14
Figure 6 – Peripheral arrangement of TEG for complex tests . 15
Figure 7 – Chip arrangement in a shot . 16
Figure 8 – Shot arrangement in a wafer . 16
Figure 9 – Structure of test board and pad connection . 17

Figure 10 – Structure of a test board and via connection . 17
Figure 11 – Area array arrangement . 19
Figure 12 – Peripheral arrangement of TEG . 21
Figure 13 – Example of pad arrangement of peripherals . 22
Figure 14 – TEG size of active device . 23
Figure 15 – TEG for passive device . 24
Figure 16 – Test pattern for conduction and insulation resistance between vias (seen
from L6). 25
Figure 17 – Complex test patterns for conduction and via-to-via insulation . 26
Figure 18 – Test patterns for insulation between conductor and between layers in an
area array arrangement . 27
Figure 19 – Complex test patterns for L1 to L6 for insulation between conductors and
layers . 28
Figure 20 – L1 to L6 complex test patterns for the peripheral arrangement . 29
Figure 21 – Conduction test patterns for L1 to L6 of passive components . 30
Figure 22 – Insulation test patterns between terminals for L1 to L6 of passive
components . 31
Figure 23 – Interlayer insulation test patterns of L1 to L6 of passive components . 32
Figure 24 – Terminal arrangement (1) for measurement and evaluation using complex
pattern for an active device . 33
Figure 25 – Terminal arrangement (2) for measurement and evaluation using complex
pattern for an active device . 34
Figure 26 – Terminal arrangement for measurement and evaluation using complex
pattern for passive device . 35
Figure 27 – Terminal arrangement for measurement and evaluation using complex
pattern for device embedded substrate . 35

Table 1 – Application and embedded device . 8
Table 2 – Measuring environment . 8
Table 3 – Test items . 18
Table 4 – Terminal dimensions . 20
Table 5 – Detailed dimensions of the peripheral arrangement of TEG . 21
Table 6 – Detailed dimensions of the peripheral arrangement of pad connections . 22
Table 7 – Dimension of passive device TEG . 24
Table 8 – Dimensions of the area array arrangement of TEG-A . 25
Table 9 – Dimensions of TEG-B for the area array arrangement . 27

– 4 – IEC TS 62878-2-4:2015 © IEC 2015
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDED SUBSTRATE –
Part 2-4: Guidelines – Test element groups (TEG)

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
The main task of IEC technical committees is to prepare International Standards. In
exceptional circumstances, a technical committee may propose the publication of a Technical
Specification when
• the required support cannot be obtained for the publication of an International Standard,
despite repeated efforts, or
• the subject is still under technical development or where, for any other reason, there is the
future but no immediate possibility of an agreement on an International Standard.
Technical Specifications are subject to review within three years of publication to decide
whether they can be transformed into International Standards.
IEC TS 62878-2-4, which is a Technical Specification, has been prepared by IEC technical
committee 91: Electronics assembly technology

The text of this Technical Specification is based on the following documents:
Enquiry draft Report on voting
91/1144/DTS 91/1165A/RVC
Full information on the voting for the approval of this Technical Specification can be found in
the report on voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62878 series, published under the general title Device embedded
substrate, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• transformed into an International standard,
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
– 6 – IEC TS 62878-2-4:2015 © IEC 2015
INTRODUCTION
This part of IEC 62878 provides guidance with respect to device embedded substrate,
fabricated by embedding discrete active and passive electronic devices into one or multiple
inner layers of a substrate with electric connections by means of vias, conductor plating,
conductive paste, and printing. Within the IEC 62878 series,
• IEC 62878-1-1 specifies the test methods,
• IEC TS 62878-2-1 gives a general description of the technology,
• IEC TS 62878-2-3 provides guidance on design, and
• IEC TS 62878-2-4 specifies the test element groups.
The device embedded substrate may be used as a substrate to mount SMDs to form
electronic circuits, as conductor and insulator layers may be formed after embedding
electronic devices.
The purpose of the IEC 62878 series is to achieve a common understanding with respect to
structures, test methods, design and fabrication processes and the use of the device
embedded substrate in industry.

DEVICE EMBEDDED SUBSTRATE
Part 2-4: Guidelines – Test element groups (TEG)

1 Scope
This part of IEC 62878 describes the test element group devices useful when measuring basic
properties of device embedded substrates.
This part of IEC 62878 is applicable to device embedded substrates fabricated by use of
organic base material, which include for example active or passive devices, discrete
components formed in the fabrication process of electronic wiring board, and sheet formed
components.
The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic
modules defined as an M-type business model in IEC 62421.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
IEC 62878-1-1, Device embedded substrate – Part 1-1: Generic specification – Test methods
3 Terms, definitions and abbreviations
3.1 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60194 apply.
3.2 Abbreviations
AABUS as agreed between user and supplier
AV audiovisual
L/S line and space
SMD surface mount device
4 Test conditions and sample preparation
4.1 General
Clause 4 describes the test conditions for device embedded boards to be used in electronics
equipment and reliability, and Clause 5 describes the test element group (hereafter referred to
as TEG) to be used as dummy test chips, as well as test patterns used in TEGs.
4.2 Test conditions
4.2.1 Classification of tests and evaluation
Subclause 4.2.1 describes the classification of test levels in various applications. The
environment in which products are used is divided into
___________
To be published.
– 8 – IEC TS 62878-2-4:2015 © IEC 2015
• consumer applications (portable and non-portable), and
• industrial and automotive applications (AV/information, car operation control, and engine
control).
Evaluation tests are divided into tests for package, module board and mother board. In this
part of IEC 62878, “mother board” indicates the main board to which packages or modules are
assembled. Three ranks are specified for evaluation levels for embedded devices (passive
and active), board materials, assembly methods, and specification and characteristics of
embedding devices. Evaluation levels are to be agreed between user and supplier (hereafter
referred to as AABUS). Table 1 shows the above mentioned classification of user environment
for each application.
Table 1 – Application and embedded device
Products Package Module Mother board
– Consumer (portable and non-portable)
Applications – Industrial
– Automotive (audiovisual information, car operation control and engine control)
Passive ○ ○ ○ ○ ○ ○
Device
Active ○ ○ ○ ○ ○ ○
4.2.2 Measuring environment
The test environment adopted in the tests described in IEC 62878-1-1 is specified in 4.2.2.
Tests are performed, unless otherwise specified, in the standard atmospheric pressure of
86 kPa to 106 kPa and air flow of smaller than 1 m/s. If it is difficult to test a specimen in the
standard condition, a test may be carried out in a condition other than the standard condition
when there is no question in evaluating test results. The test shall be carried out with the
conditions shown in Table 2 when there is no question concerning the test result, or it shall be
specifically requested by the user and supplier.
Table 2 – Measuring environment
Temperature Humidity Pressure
Classification Remarks
°C % kPa
Common 15 to 35 25 to 75 86 to 106
Use the standard
Class 1 23 ± 1 50 ± 5 testing condition,
23/50 86 to 106
if not specified
Standard
Class 2
23 ± 2 50 ± 10
condition
AABUS
Class 1 27 ± 1 65 ± 5
27/65 86 to 106
e.g. in a tropical
Class 2 27 ± 1 65 ± 5
area
Evaluation Common 20 ± 2 60 to 70 86 to 106

4.2.3 Test methods
Test methods using TEG are as described in this part of IEC 62878. These test methods
especially comprise electrical and mechanical tests. Tests for other items described in this
part of IEC 62878 may be carried out AABUS.
4.3 Test specimens and number of specimens
4.3.1 Specimen
Test specimen is either a) or b) as listed below. The surface of a specimen shall not be
contaminated by grease, sweat or other foreign objects.

a) Actual device embedded board
Cut a specimen for the test from the product of a shape and size as specified by individual
specifications using a method that does not affect the performance of the specimen.
b) Test pattern specimen
Use TEG and applicable circuit for the test of an embedded device itself. Prepare a test
pattern specimen of a board and embedded device(s) using the same material as that
used in the actual device embedded board. Use the same procedure to prepare a test
device as for the embedded device.
4.3.2 Number of specimens
The number of specimens used in a test shall be either a) or b) as specified by the
manufacturing status below. The agreement between user and supplier, if there is any, shall
have priority.
a) Test production
n ≥ 5 of the unit AABUS.
b) Volume production
n ≥ 10 of the unit AABUS.
4.3.3 Test report
The test items shall be chosen from the list stated below AABUS, and the items shall be
included in the test report:
a) date of the test;
b) test location;
c) name, type and size of the embedded device;
d) material, size and layer structure of the test board;
e) assembly technique of the embedded device (interconnection, embedding, etc.);
f) design specification and product specification of the test board;
g) test equipment (specifications of the test system and equipment, jigs, material, shape,
etc.);
h) test condition (temperature, humidity, applied voltage, current, number of repetitions, time,
etc.);
i) graphs and figures showing relations between test condition and result;
j) defect mode (photographs, etc.).
5 TEG
5.1 Preparation of the TEG
For the testing of device embedded substrate, TEG made up of neutral aluminium wiring is
prepared. It is recommended that the passive device be replaced by a copper wiring board or
that a zero ohm jumper resistor be used.
Examples of TEG are shown in Figure 1 and Figure 2. TEG-A is a sample of daisy chain to
investigate connectivity. TEG-B is to measure leakage current and capacitance.

– 10 – IEC TS 62878-2-4:2015 © IEC 2015
3,0 mm
1,35 mm (9 ×0,15 mm) 1,2 mm (8 ×0,15 mm)
IEC
a) TEG-A – Entire view of TEG of 150 µm pitch chip

50 µm
90 µm
100 µm
IEC
b) Detail of pad
Specification of TEG-A 150 µm pitch chip
Name: SIPOS-TEG SB0501 Distance between pad edges: 50 µm
Pad pitch: 150 µm Chip size: 3,0 mm × 3,0 mm
Daisy chain pad: 180
Number of pads: 324 (18 × 18)
Pad size: 100 µm × 100 µm (aluminium wiring) Independent pad: 144
Scribe width: 100 µm Pad opening: φ = 90 µm (pad opening)

Figure 1 – Area array arrangement – TEG for conductor
resistivity and via-to-via insulation
3,0 mm
2,55 mm (17 × 0,15 mm)
150 µm
3,0 mm
0,35 mm 0,78 mm 1,0 mm 0,4 mm
0,03 mm
2,55 mm (17 × 0,15 mm)
IEC
a) TEG-B Entire view of TEG of 150 µm pitch chip
760 µm (19 × 40 µm (L/S = 20/20))
50 µm
IEC
b) Detail of comb pattern
Specification of TEG-B 150 µm pitch chip
Name: SIPOS-TEG SB0601 Chip size: 3,0 mm × 3,0 mm
Pad pitch: 150 µm Number of pads: 68
Pad size: 100 µm × 100 µm (aluminium wiring) Pad opening: φ = 90 µm (pad opening)
Size of comb pattern: L/S = 20 µm/20 µm Number of comb patterns: 20 (10 × 2)
Dimension of inter-layer insulation pattern: φ = 1,0 mm (octagonal)
Figure 2 – Area array arrangement – TEG for insulation measurement of
resistance between conductors and insulation resistance between layers
3,0 mm
2,25 mm
60 µm
60 µm
0,3525 mm
– 12 – IEC TS 62878-2-4:2015 © IEC 2015
Figure 3 and Figure 4 show chip arrangement in a shot and shot arrangement in a wafer,
respectively.
A
B
18,0 mm (6 chips ×3,0 mm)
C D
IEC
Key
A Area arrangement: TEG-A of 150 µm pad pitch
B
Area arrangement: TEG-A of 300 µm pad pitch
C
Area arrangement: TEG-B of 150 µm pad pitch
D Area arrangement: TEG-B of 300 µm pad pitch

Figure 3 – Chip arrangement in a shot

18,0 mm (6 chips ×3,0 mm)
A
B
IEC
Key
A Wafer
B Shot
Shot size: 18,0 mm × 18,0 mm
Number of shots: 76 shots per wafer (8 in (203,2 mm) wafer)
Figure 4 – Shot arrangement in a wafer
Figure 5 shows the pitch chip specification of peripheral terminal of 60 µm TEG. Details of the
peripheral terminal and interconnection are shown in Figure 6.

– 14 – IEC TS 62878-2-4:2015 © IEC 2015
3,0 mm
0,35 mm 0,973 mm 1,0 mm 0,4 mm
0,10 mm
2,58 mm (43 × 0,06 mm)
IEC
a) Entire view of pitch chip of peripheral terminal of 60 µm

60 µm
IEC
b) Details of peripheral terminal

Specification of TEG-B 150µm pitch chip
Name: SIPOS-TEG SB0401
Chip size: 3,0 mm × 3,0 mm
Pad pitch: 60 µm Number of pads: 168
Pad size: 46 µm × 40 µm (aluminium wiring) Pad opening: 40 µm × 40 µm (pro opening)
Scribe width: 100 µm Size of comb pattern: L/S = 20 µm/20 µm
Number of comb patterns: 70 (35 × 2) Inter-layer insulation pattern: φ = 1,0 mm (octagonal)
Insulation measurement pattern between vias: right
Daisy chain pad: 30 pads for upper/lower
and left sides
Figure 5 – Pitch chip specification of peripheral terminal of 60µm TEG
3,0 mm
2,38 mm
46 µm
40 µm
20 µm
0,3835 mm
966 µm (69 × 14 µm (L/S = 7/7))
24 µm
IEC
a) Details of comb pattern for insulation measurement between conductors
100 µm
46 µm
IEC
b) Details of a pad for insulation measurement between layers

20 µm
20 µm
20 µm
20 µm
IEC
c) Details of a pad for insulation measurement between vias

Figure 6 – Peripheral arrangement of TEG for complex tests
Figure 7 and Figure 8 show chip arrangement in a shot and shot arrangement in a wafer,
respectively.
24 µm
24 µm
20 µm
20 µm
14 µm
– 16 – IEC TS 62878-2-4:2015 © IEC 2015
A
B
18,0 mm (6 chips × 3,0 mm)
C D
IEC
Key
A Peripheral arrangement: TEG-A at 60µm pad pitch
B
Peripheral arrangement: TEG-A at 80µm pad pitch
C Peripheral arrangement: TEG-B at 100µm pad pitch
D Peripheral arrangement: TEG-B at 40µm pad pitch
Figure 7 – Chip arrangement in a shot
A
B
IEC
Key
A Wafer
B Shot
Shot size: 18,0 mm × 18,0 mm
Number of shots: 76 shots per wafer (8 in (203,2 mm) wafer)
Figure 8 – Shot arrangement in a wafer
18,0 mm (6 chips × 3,0 mm)
5.2 Structures of TEG
Structures of test specimen embedded boards are shown in Figure 9 and Figure 10. The
specimen is connected to terminals in a board as in the case of an actual embedded device.
The test pattern is formed as a complex test pattern including connections of an actual
embedded device. It is desirable to use a test pattern which can be divided into sections for
embedded device connections and wiring within the base for easier analysis. The layer
structure is named as L1 and L2 from the front surface, L3 and L4 for the TEG layers, and L5
and L6 as the layers for test. The TEG for the actual embedded device is described in this
part of IEC 62878 for the case of single sided wiring as it is difficult to make through holes in
a bare chip in a specimen.
B
C
A
L1
L2
(L3)
(L4)
L5
L6
E
E D
IEC
Key
A TEG
B Area to be tested in device embedded board
C Surface test circuit
D Connection actually used
E Area to be tested for printed wiring board
Figure 9 – Structure of test board and pad connection
B
C A
L1
L2
(L3)
(L4)
L5
L6
D
E E
IEC
Key
A TEG
B Area to be tested in device embedded board
C Surface test circuit
D Connection actually used
E Area to be tested for a printed wiring board
Figure 10 – Structure of a test board and via connection

– 18 – IEC TS 62878-2-4:2015 © IEC 2015
5.3 Test pattern guide
5.3.1 Test items
Table 3 lists the items to be tested. For details of test items and methods, refer to
IEC 62878-1-1 . The evaluation test of a device embedded board in this part of IEC 62878 is
given for a specimen embedding a TEG. The evaluation is made for connections of a TEG and
electronic wiring board terminals using various test patterns. The test for individual device
embedded boards is carried out with a specimen using a recommended TEG and a complex
test pattern.
Table 3 – Test items
Subclause of
IEC 62878-1-
Embedded
1:2015
No Test patterns Test Remarks
device
specifying
the test
methods
1 Visual inspection and microsectioning  4.2.2, 4.2.3
2 Land dimension and land width (annular  4.2.5
ring)
3 Figures 11 to 27 Conductor resistance ○ 4.3.1
4 Figures 11 to 27 Withstanding current and voltage ○ Specification 4.3.3, 4.3.4
of
embedded
device
5 Figures 11 to 27 Insulation resistance ○ 4.3.5
6 Figures 11 to 27 Insulation and conduction of circuit  4.3.6
7 Pulling strength of conductor  4.4.1
8 Pulling strength of un-plated through hole  4.4.2
9 Pulling strength of plated through hole  4.4.3
10 Pulling strength of pad of land pattern  4.4.4
11 Adhesivity of plated foil  4.4.5
12 Adhesivity of solder resist and symbol mark  4.4.6
13 Film hardness (solder resist, symbol mark)  4.4.7
14 Figures 11 to 27 High and low temperatures ○ 4.5.1
15 Figures 11 to 27 Thermal shock (high and low temperatures) ○ 4.5.2
16 Figures 11 to 27 Resistance to humidity ○ 4.5.4
17 Figures 11 to 27 Resistance to migration ○ 4.6.1
18 Figures 11 to 27 Vibration ○
19 Figures 11 to 27 Drop test ○
20 Figures 11 to 27 Bending ○
21 Figures 11 to 27 Screwing ○
22 Flammability
23 Resistance to solvent
24 Solderability
25 Resistance to soldering heat
26 Resistance to soldering heat of solder
resist and symbol mark
___________
To be published.
5.3.2 Area array arrangement of TEG for an active device
Figure 11 shows the area array arrangement of TEG for active devices. Table 4 gives the
detailed dimensions of the terminals.
l
p p
2 1
d
A
IEC
Key
A centre section
Figure 11 – Area array arrangement

– 20 – IEC TS 62878-2-4:2015 © IEC 2015
Table 4 – Terminal dimensions
Device Terminal Number of Number of TEG size Size of side Pad diameter
pitch rows terminals
p p
l d
1 2
full grid mm
µm µm µm
26 676 3,0 250
100 60
a
52 6,0 250
2 704
Bare die
18 324 3,0 225
150 90
a
36 6,0 225
1 296
14 196 3,0 200
Bare die
28 784 6,0 300
200 120
WL-CSP
a
42 9,0 200
1 764
10 100 3,0 375
250 20 400 6,0 375 150
30 900 9,0 375
8 64 3,0 450
WL-CSP
300 16 256 6,0 450 180
PKG
24 576 9,0 450
5 25 3,0 500
500 10 100 6,0 500 300
15 225 9,0 500
a
When the number of pins is over 1 000, it is possible to decrease the number of pins in the centre section (A)
if agreed between user and supplier.

5.3.3 Peripheral arrangement of TEG
Figure 12 shows the peripheral arrangement of the TEG for an active device and Table 5
gives the details of the terminal pitch of each peripheral. The peripheral is the narrow pitch
arrangement. Use of the test pattern using connecting pads is recommended to the board on
which a device is mounted, as illustrated in Figure 13. It may be difficult to form vias and to
use stacked via formations due to the narrow pitch. The design of the connecting pads is to
be AABUS.
l
p p
2 1
d
IEC
Figure 12 – Peripheral arrangement of TEG
Table 5 – Detailed dimensions of the peripheral arrangement of TEG
Device Terminal Number of Number of TEG size Edge Pad diameter
pitch rows terminals
p  l p d
1 2
µm  mm µm µm
64 256 3,0
40 128 512 6,0 200 26
192 768 9,0
42 168 3,0
60 84 336 6,0 210 40
126 504 9,0
Bare die
30 120 3,0
80 60 240 6,0 260 50
90 360 9,0
24 96 3,0
100 48 192 6,0 250 70
72 288 9,0
NOTE 2-row, 3-row, or staggered arrangement of peripherals shall be AABUS.

– 22 – IEC TS 62878-2-4:2015 © IEC 2015
l
p d
w
l
p
IEC
Figure 13 – Example of pad arrangement of peripherals
An example of doubling the pitch of peripheral terminals is shown in Table 6.
Table 6 – Detailed dimensions of the peripheral arrangement of pad connections
Device Terminal TEG size Number of Number of Pad range Pad pitch Pad Conductor
pitch rows terminals diameter width
p l  l p d w
1 1 2 2
µm mm  mm µm µm µm
3,0 64 256 5,20
40 6,0 128 512 10,32 80 48 20
9,0 192 768 15,44
3,0 42 172 5,16
60 6,0 84 336 10,20 120 72 30
9,0 126 504 15,24
3,0 30 120 4,96
80 6,0 60 240 9,76 160 100 40
9,0 90 360 14,56
3,0 24 96 4,80
100 6,0 48 192 9,80 200 120 60
9,0 72 288 14,60
Bare die
5.3.4 TEG size for active devices
The standard TEG size is shown in Figure 14. The basic size is 3,0 mm × 3,0 mm as shown in
Figure 14 a). The size of 4 elements is 6,0 mm × 6,0 mm as in Figure 14 b) below. And the
size of 9 elements is 9,0 mm × 9,0 mm as in Figure 14 c) below. For b) and c), each 3,0 mm ×
3,0 mm element is connected to the printed wiring board.
IEC
a) 3,0 mm × 3,0 mm
IEC
b) 6,0 mm × 6,0 mm
9,0 mm
6,0 mm
3,0 mm
IEC
c) 9,0 mm × 9,0 mm
Figure 14 – TEG size of active device

– 24 – IEC TS 62878-2-4:2015 © IEC 2015
5.3.5 TEG for passive devices
Use of a TEG with a zero ohm jumper resistor is recommended as a passive device. The
arrangement of a pad is shown in Figure 15 and the dimensions are specified in Table 7.
Via/land connection dimensions are AABUS. The resistance of 50 mΩ for a zero ohm jumper
resistor is specified.
E F
c
a d
b
IEC
Key
E pad
F solder resist
Figure 15 – TEG for passive device
Table 7 – Dimension of passive device TEG
Dimensions in millimetres
Dimension
Size
a b c d
0,4 × 0,2 0,20 0,60 0,25 0,20
0,30 1,00 0,35 0,35
0,6 × 0,3
1,0 × 0,5 0,50 1,60 0,60 0,55
1,00 3,00 1,20 1,00
1,6 × 0,8
5.3.6 Complex test pattern for the area arrangement, TEG-A
Figure 16 shows the test pattern for the test of conduction and insulation resistance between
vias. Detailed dimensions of TEG-A are given in Table 8 and the patterns of L1 to L6 in
Figure 17.
w
w
IEC
Figure 16 – Test pattern for conduction and insulation
resistance between vias (seen from L6)
Table 8 – Dimensions of the area array arrangement of TEG-A
Dimensions in micrometres
Device type Terminal pitch Conductor position Conductor width Conductor width
p p w w
1 2 1 2
100 100 20 40
Bare die
150 150 30 60
Bare die
200 200 40 80
WL-CSP
250 250 50 100
WL-CSP
300 300 60 120
PKG
500 500 100 200
NOTE Dimension may be changed according to test method and test condition.

p
1 p
– 26 – IEC TS 62878-2-4:2015 © IEC 2015
B
A
IEC IEC
a) L1 (first layer) b) L2 (second layer)

IEC IEC
c) L3 (third layer) d) L4 (fourth layer)
(applicable to double-sided TEG)

IEC IEC
e) L5 (fifth layer) f) L6 (sixth layer)

Key
A Conduction test
B Insulation between pins
Figure 17 – Complex test patterns for conduction and via-to-via insulation

5.3.7 Complex pattern for area arrangement of TEG-B
Figure 18 shows the complex pattern for insulation test between conductors and between
layers in the area array arrangement. Detailed dimensions of TEG-B for an active device are
given in
Table 9, and the patterns of L1 to L6 are specified in Figure 19.
p
s
w
A
B
d
w
IEC
Key
A Insulation test between conductors
B Insulation test between layers
Figure 18 – Test patterns for insulation between conductor
and between layers in an area array arrangement

Table 9 – Dimensions of TEG-B for the area array arrangement
Dimensions in micrometres
Device Terminal Position Width Width Gap Gap Width Size
pitch
l ,l w w s s w
p d
1 2 1 2 1 2 3
40 100 16 5 5 16 100 1 000
Bare die
60 100 24 7 7 24 100 1 000
(peripheral)
80 100 32 10 10 32 100 1 000
100 100 40 12 12 40 100 1 000
Bare die
150 150 60 18 18 60 100 1 000
Bare die
200 200 80 24 24 80 100 1 000
WL-CSP
250 250 100 30 30 100 100 1 000
WL-CSP
300 300 120 36 36 120 120 1 000
PKG
500 500 220 67,5 67,5 220 220 1 000

l l
w 1 2
s
l l
1 2
– 28 – IEC TS 62878-2-4:2015 © IEC 2015
IEC IEC
a) L1 (first layer) b) L2 (second layer)

IEC
IEC
c) L3 (third layer) d) L4 (fourth layer)
(applicable to two-sided TEG)
IEC IEC
e) L5 (fifth layer) f) L6 (sixth layer)
Figure 19 – Complex test patterns for L1 to L6
for insulation between conductors and layers

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