IEC TS 62878-2-4:2015

Device embedded substrate - Part 2-4: Guidelines - Test element groups (TEG)

IEC TS 62878-2-4:2015 describes the test element group devices useful when measuring basic properties of device embedded substrates. It is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.

Substrat avec appareil(s) intégré(s) - Partie 2-4: Directives - Groupes d'éléments d'essai (TEG)

L'IEC TS 62878-2-4:2015 décrit les appareils du groupe d'éléments d'essai utiles pour mesurer les propriétés de base des substrats avec appareil(s) intégré(s). Il est applicable aux substrats avec appareil(s) intégré(s) fabriqués à partir de matériaux de base organiques, y compris par exemple les appareils actifs ou passifs, les composants discrets formés lors du processus de fabrication d'une carte de câblage électronique, ainsi que les composants de feuilles minces.

General Information

• Status: Published
• Publication Date: 26-Mar-2015
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.180 - Printed circuits and boards
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 6 - TC 91/WG 6
• Current Stage: PPUB - Publication issued
• Start Date: 15-Mar-2015
• Completion Date: 27-Mar-2015

Standards Content (Sample)

IEC TS 62878-2-4 ®
Edition 1.0 2015-03
TECHNICAL
SPECIFICATION
SPECIFICATION
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-4: Guidelines – Test element groups (TEG)

Substrat avec appareil(s) intégré(s) –
Partie 2-4: Directives – Groupes d'éléments d'essai (TEG)

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IEC TS 62878-2-4 ®
Edition 1.0 2015-03
TECHNICAL
SPECIFICATION
SPECIFICATION
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-4: Guidelines – Test element groups (TEG)

Substrat avec appareil(s) intégré(s) –

Partie 2-4: Directives – Groupes d'éléments d'essai (TEG)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-2435-9

– 2 – IEC TS 62878-2-4:2015 © IEC 2015
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references. 7
3 Terms, definitions and abbreviations . 7
3.1 Terms and definitions . 7
3.2 Abbreviations . 7
4 Test conditions and sample preparation . 7
4.1 General . 7
4.2 Test conditions . 7
4.2.1 Classification of tests and evaluation . 7
4.2.2 Measuring environment . 8
4.2.3 Test methods . 8
4.3 Test specimens and number of specimens . 8
4.3.1 Specimen. 8
4.3.2 Number of specimens. 9
4.3.3 Test report . 9
5 TEG . 9
5.1 Preparation of the TEG. 9
5.2 Structures of TEG . 17
5.3 Test pattern guide . 18
5.3.1 Test items . 18
5.3.2 Area array arrangement of TEG for an active device . 19
5.3.3 Peripheral arrangement of TEG . 20
5.3.4 TEG size for active devices . 23
5.3.5 TEG for passive devices. 24
5.3.6 Complex test pattern for the area arrangement, TEG-A . 24
5.3.7 Complex pattern for area arrangement of TEG-B . 27
5.3.8 Complex test pattern for peripheral arrangement . 29
5.3.9 Complex test pattern for passive components . 30
5.3.10 Guide of measurement terminals of a complex test pattern for an active
device . 33
5.3.11 Terminal arrangement using complex patterns . 34
Bibliography . 36

Figure 1 – Area array arrangement – TEG for conductor resistivity and via-to-via
insulation . 10
Figure 2 – Area array arrangement – TEG for insulation measurement of resistance
between conductors and insulation resistance between layers . 11
Figure 3 – Chip arrangement in a shot . 12
Figure 4 – Shot arrangement in a wafer . 13
Figure 5 – Pitch chip specification of peripheral terminal of 60µm TEG . 14
Figure 6 – Peripheral arrangement of TEG for complex tests . 15
Figure 7 – Chip arrangement in a shot . 16
Figure 8 – Shot arrangement in a wafer . 16
Figure 9 – Structure of test board and pad connection . 17

Figure 10 – Structure of a test board and via connection . 17
Figure 11 – Area array arrangement . 19
Figure 12 – Peripheral arrangement of TEG . 21
Figure 13 – Example of pad arrangement of peripherals . 22
Figure 14 – TEG size of active device . 23
Figure 15 – TEG for passive device . 24
Figure 16 – Test pattern for conduction and insulation resistance between vias (seen
from L6). 25
Figure 17 – Complex test patterns for conduction and via-to-via insulation . 26
Figure 18 – Test patterns for insulation between conductor and between layers in an
area array arrangement . 27
Figure 19 – Complex test patterns for L1 to L6 for insulation between conductors and
layers . 28
Figure 20 – L1 to L6 complex test patterns for the peripheral arrangement . 29
Figure 21 – Conduction test patterns for L1 to L6 of passive components . 30
Figure 22 – Insulation test patterns between terminals for L1 to L6 of passive
components . 31
Figure 23 – Interlayer insulation test patterns of L1 to L6 of passive components . 32
Figure 24 – Terminal arrangement (1) for measurement and evaluation using complex
pattern for an active device . 33
Figure 25 – Terminal arrangement (2) for measurement and evaluation using complex
pattern for an active device . 34
Figure 26 – Terminal arrangement for measurement and evaluation using complex
pattern for passive device . 35
Figure 27 – Terminal arrangement for measurement and evaluation using complex
pattern for device embedded substrate .
...