IEC 62142:2005

Verilog (R) register transfer level synthesis

Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

General Information

• Status: Withdrawn
• Publication Date: 26-Jun-2005
• Withdrawal Date: 03-Aug-2010
• ICS: 25.040.99 - Other industrial automation systems
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 2 - TC 91/WG 2
• Current Stage: WPUB - Publication withdrawn
• Completion Date: 04-Aug-2010

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD 62142
First edition
2005-06
IEEE

1364.1 ®
Verilog register transfer level synthesis

Reference number
IEC 62142(E):2005
IEEE Std. 1364.1(E):2002
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INTERNATIONAL IEC
STANDARD 62142
First edition
2005-06
IEEE

1364.1 ®
Verilog register transfer level synthesis

© IEEE 2005  Copyright - all rights reserved
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No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
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Commission Electrotechnique Internationale
International Electrotechnical Commission
Международная Электротехническая Комиссия

– 2 – IEC 62142:2005(E)
IEEE 1364.1-2002(E)
CONTENTS
FOREWORD . 4

IEEE Introduction . 7

1. Overview. 8

1.1 Scope . 8

1.2 Compliance to this standard . 8

1.3 Terminology . 9

1.4 Conventions. 9

1.5 Contents of this standard . 9

1.6 Examples .10

2. References.10
3. Definitions.10
4. Verification methodology .11
4.1 Combinational logic verification.12
4.2 Sequential logic verification.12
5. Modeling hardware elements.13
5.1 Modeling combinational logic .13
5.2 Modeling edge-sensitive sequential logic .14
5.3 Modeling level-sensitive storage devices.17
5.4 Modeling three-state drivers.18
5.5 Support for values x and z.20
5.6 Modeling read-only memories (ROM) .20
5.7 Modeling random access memories (RAM) .22
6. Pragmas.23
6.1 Synthesis attributes.23
6.2 Compiler directives and implicit-synthesis defined macros .34
6.3 Deprecated features .35
7. Syntax .36
7.1 Lexical conventions.36
7.2 Data types.41
7.3 Expressions.46

7.4 Assignments .48
7.5 Gate and switch level modeling .49
7.6 User-defined primitives (UDPs).52
7.7 Behavioral modeling .53
7.8 Tasks and functions.59
7.9 Disabling of named blocks and tasks .62
7.10 Hierarchical structures.62
7.11 Configuring the contents of a design.68
7.12 Specify blocks .70
7.13 Timing checks .70
7.14 Backannotation using the standard delay format .70
7.15 System tasks and functions .70
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

IEEE 1364.1-2002(E)
7.16 Value change dump (VCD) files.70

7.17 Compiler directives .70

7.18 PLI.71

Annex A (informative) Syntax summary .72

A.1 Source text.72
A.2 Declarations.74
A.3 Primitive instances . 79

A.4 Module and generated instantiation . 81

A.5 UDP declaration and instantiation. 82

A.6 Behavioral statements . 83
A.7 Specify section . 87
A.8 Expressions. 92
A.9 General .96
Annex B (informative) Functional mismatches.100
B.1 Non-deterministic behavior.100
B.2 Pragmas .100
B.3 Using `ifdef .101
B.4 Incomplete sensitivity list.102
B.5 Assignment statements mis-ordered.103
B.6 Flip-flop with both asynchronous reset and asynchronous set.104
B.7 Functions .104
B.8 Casex .105
B.9 Casez .105
B.10 Making x assignments.106
B.11 Assignments in variable declarations. 107
B.12 Timing delays. 107
Annex C (informative) List of Participants .108

Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

– 4 – IEC 62142:2005(E)
IEEE 1364.1-2002(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION

___________ ®
VERILOG REGISTER TRANSFER LEVEL SYNTHESIS

FOREWORD
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...