Fibre optic active components and devices - Package and interface standards - Part 19: Photonic chip scale package

IEC 62148-19: 2019 covers the photonic chip scale package. The purpose of this document is to specify adequately the physical requirements of optical transmitters and receivers that will enable mechanical interchangeability of transmitters and receivers.
Keywords: physical interface for photonic chip scale packages

Composants et dispositifs actifs fibroniques - Normes de boîtier et d’interface - Partie 19 : Boîtier à puce photonique

L'IEC 62148-19: 2019 couvre les boîtiers à puces photoniques. L'objectif du présent document est de spécifier les exigences physiques des modules d'émission et de réception optique qui permettent l'interchangeabilité mécanique des émetteurs et transmetteurs.
Mots-clés: interface physique des boîtiers à puces photoniques

General Information

Status
Published
Publication Date
01-May-2019
Current Stage
PPUB - Publication issued
Start Date
02-May-2019
Completion Date
24-May-2019

Overview

IEC 62148-19:2019 is an international standard established by the International Electrotechnical Commission (IEC) that focuses on fibre optic active components and devices, specifically relating to package and interface standards. This Part 19 document defines the physical requirements for photonic chip scale packages (CSPs) used in optical transmitters and receivers. The primary goal is to promote mechanical interchangeability of photonic components by specifying a standardized physical interface and package outline.

Photonic chip scale packages are crucial in the rapidly evolving field of silicon photonics and fibre optic communication, offering compact integration and high performance. IEC 62148-19:2019 ensures manufacturers and users have a common reference for design, enabling seamless integration and replacement of optical modules within systems.

Key Topics

  • Scope and Purpose: Standardizes the physical interface of photonic chip scale packages to allow mechanical interchangeability of transmitters and receivers.
  • Classification: Defines types of devices covered under the photonic CSP category.
  • General Block Diagram: Illustrates silicon photonics-based chip scale package structure.
  • Electrical Interface:
    • Terminal numbering and function definitions.
    • High-speed electrical interface considerations.
  • Optical Interface:
    • Specifications for free space optical beam conditions.
    • Optical terminal assignments with detailed pitch layout.
  • Outline and Footprint:
    • Package outline dimensions for multiple channel configurations.
    • Recommended PCB pattern layouts for integration.
  • Specific Configurations:
    • Defined standards for 4-channel, 8-channel, and 12-channel transceivers, transmitters, and receivers.
    • Includes detailed electrical and optical terminal assignments and block diagrams.
    • Mechanical drawings with dimensions for mounting and integration.

Applications

IEC 62148-19:2019 is highly relevant for industries and professionals involved in the design, manufacture, and deployment of fibre optic components and systems, including:

  • Telecommunications: Enabling compact, high-performance optical transceivers in fibre optic networks.
  • Data Centers: Facilitating dense integration of photonic devices for high-speed, energy-efficient data transmission.
  • Silicon Photonics Development: Supporting the standardization of packaging used in advanced silicon photonics chips.
  • Optical Module Manufacturers: Providing a reference for mechanical and electrical interfaces, ensuring compatibility and interchangeability.
  • System Integrators: Assisting in selecting standardized photonic chip components that fit established footprints and interfaces.
  • Test and Measurement Equipment: Ensuring consistent component specifications for accurate optical performance testing.

By following IEC 62148-19, organizations can reduce development time, ensure interoperability across suppliers, and support scalability to higher channel counts and complex photonic systems.

Related Standards

IEC 62148-19:2019 is part of a broader series dedicated to fibre optic active components and device packaging, including:

  • IEC 62148 Series: Covers general packaging and interface standards for fibre optic components.
  • Other parts in the IEC 62148 series that address different package types, mechanical standards, and electrical interfaces for various optical device configurations.
  • Coupled with standards from other organizations such as IEEE and ITU-T focusing on optical interfaces and communication protocols.

For additional terminology and electrotechnical vocabulary related to fibre optics, professionals can consult IEC’s Electropedia, the international online dictionary. The IEC webstore also provides access to the latest updates, corrigenda, and amendments to the IEC 62148 series.


Keywords: photonic chip scale package, IEC 62148-19, fibre optic active components, optical transmitters, optical receivers, mechanical interchangeability, silicon photonics packaging, optical module footprint, electrical interface, optical interface, fibre optic transceivers.

Standard

IEC 62148-19:2019 - Fibre optic active components and devices - Package and interface standards - Part 19: Photonic chip scale package

English and French language
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Frequently Asked Questions

IEC 62148-19:2019 is a standard published by the International Electrotechnical Commission (IEC). Its full title is "Fibre optic active components and devices - Package and interface standards - Part 19: Photonic chip scale package". This standard covers: IEC 62148-19: 2019 covers the photonic chip scale package. The purpose of this document is to specify adequately the physical requirements of optical transmitters and receivers that will enable mechanical interchangeability of transmitters and receivers. Keywords: physical interface for photonic chip scale packages

IEC 62148-19: 2019 covers the photonic chip scale package. The purpose of this document is to specify adequately the physical requirements of optical transmitters and receivers that will enable mechanical interchangeability of transmitters and receivers. Keywords: physical interface for photonic chip scale packages

IEC 62148-19:2019 is classified under the following ICS (International Classification for Standards) categories: 33.180.20 - Fibre optic interconnecting devices; 47.020.70 - Navigation and control equipment. The ICS classification helps identify the subject area and facilitates finding related standards.

IEC 62148-19:2019 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.

Standards Content (Sample)


IEC 62148-19 ®
Edition 1.0 2019-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Fibre optic active components and devices – Package and interface standards –
Part 19: Photonic chip scale package

Composants et dispositifs actifs fibroniques – Normes de boîtier et d'interface –
Partie 19: Boîtier à puce photonique

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IEC 62148-19 ®
Edition 1.0 2019-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Fibre optic active components and devices – Package and interface standards –

Part 19: Photonic chip scale package

Composants et dispositifs actifs fibroniques – Normes de boîtier et d'interface –

Partie 19: Boîtier à puce photonique

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 33.180.20 ISBN 978-2-8322-6869-8

– 2 – IEC 62148-19:2019 © IEC 2019
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references . 7
3 Terms, definitions and abbreviated terms . 7
3.1 Terms and definitions . 7
3.2 Abbreviated terms . 7
4 Classification . 8
5 Specification of photonic chip scale package . 8
5.1 General . 8
5.2 General block diagram (silicon photonics) . 8
5.3 Electrical interface . 9
5.3.1 General . 9
5.3.2 Numbering of electrical terminals . 9
5.4 Optical interface . 9
5.4.1 General . 9
5.4.2 Free space optical beam condition . 9
5.5 Outline and footprint . 9
5.5.1 General . 9
5.5.2 Drawing of footprint . 10
Annex A (normative) Specific configurations . 11
A.1 General . 11
A.2 4ch transceiver . 11
A.2.1 Block diagram . 11
A.2.2 Electrical terminal assignments . 12
A.2.3 Optical terminal assignments . 15
A.2.4 Outline drawing . 16
A.3 8ch transceiver . 18
A.3.1 Block diagram . 18
A.3.2 Electrical terminal assignments . 19
A.3.3 Optical terminal assignments . 23
A.3.4 Outline drawing . 24
A.4 12ch transmitter and receiver . 25
A.4.1 Block diagram . 25
A.4.2 Electrical terminal assignments . 27
A.4.3 Optical terminal assignments . 32
A.4.4 Outline drawing . 34
Bibliography . 38

Figure 1 – General block diagram for photonic chip scale package . 8
Figure 2 – Electrical terminal numbering assignment (top view) . 9
Figure 3 – Recommended pattern layout for PCB . 10
Figure 4 – Informative electrical strip line wiring for high speed electrical interface . 10
Figure A.1 – Block diagram for chip scale package of 4ch transceiver using silicon
photonics chip with optional pads for LD control. 12

Figure A.2 – Electrical terminal numbering assignment (top view) . 13
Figure A.3 – Optical terminal numbering assignment for 0,25 mm pitch optical interface
for 4ch transceiver (top view) . 16
Figure A.4 – Package outline drawing of 4ch transceiver . 17
Figure A.5 – Block diagram for chip scale package of 8ch transceiver using silicon

photonics chip with optional pads for LD control. 19
Figure A.6 – Electrical terminal numbering assignment (top view) . 20
Figure A.7 – Optical terminal numbering assignment for 0,125 mm pitch optical
interface for 8ch transceiver (top view) . 23
Figure A.8 – Package outline drawing of 8ch transceiver . 24
Figure A.9 – Block diagram for chip scale package of 12ch transmitter using silicon
photonics chip with optional pads for LD control. 26
Figure A.10 – Block diagram for the chip scale package of 12ch receiver with optional

pad for PD bias . 26
Figure A.11 – Electrical terminal numbering assignment (top view) . 27
Figure A.12 – Optical terminal numbering assignment for 0,125 mm pitch optical
interface for 12ch transmitter and receiver (top view) . 33
Figure A.13 – Package outline drawing of 12ch transmitter . 34
Figure A.14 – Package outline drawing of 12ch receiver . 36

Table 1 – Dimensions of recommended pattern layout for PCB . 10
Table A.1 – Specific configurations specified in Annex A . 11
Table A.2 – Terminal function definitions for a 4ch transceiver . 13
Table A.3 – Optical terminal function definitions for 4ch transceiver . 16
Table A.4 – Dimensions of the package outline of 4ch transceiver . 17
Table A.5 – Terminal function definitions for 8ch transceiver. 20
Table A.6 – Optical terminal function definitions for 8ch transceiver . 24
Table A.7 – Dimensions of the package outline of 8ch transceiver . 25
Table A.8 – Terminal function definitions for 12ch transmitter . 27
Table A.9 – Terminal function definitions for 12ch receiver . 30
Table A.10 – Optical terminal function definitions for 12ch transmitter . 33
Table A.11 – Optical terminal function definitions for 12ch receiver . 34
Table A.12 – Dimensions of the package outline of 12ch transmitter . 35
Table A.13 – Dimensions of the package outline of 12ch receiver . 36

– 4 – IEC 62148-19:2019 © IEC 2019
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FIBRE OPTIC ACTIVE COMPONENTS AND DEVICES –
PACKAGE AND INTERFACE STANDARDS –

Part 19: Photonic chip scale package

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
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indispensable for the correct application of this publication.
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rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62148-19 has been prepared by subcommittee 86C: Fibre optic
systems and active devices, of IEC technical committee 86: Fibre optics.
The text of this International Standard is based on the following documents:
FDIS Report on voting
86C/1574/FDIS 86C/1586/RVD
Full information on the voting for the approval of this International Standard can be found in the
report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62148 series, published under the general title Fibre optic active
components and devices – Package and interface standards, can be found on the IEC website.

The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
– 6 – IEC 62148-19:2019 © IEC 2019
INTRODUCTION
A photonic chip scale package is used to convert electrical signals into optical signals and vice-
versa. This document covers the physical interface for photonic chip scale packages. These
modules are designed for use with free space optics or multiple channel optical fibre connectors.

FIBRE OPTIC ACTIVE COMPONENTS AND DEVICES –
PACKAGE AND INTERFACE STANDARDS –

Part 19: Photonic chip scale package

1 Scope
This part of IEC 62148 covers the photonic chip scale package.
The purpose of this document is to specify adequately the physical requirements of optical
transmitters and receivers that will enable mechanical interchangeability of transmitters and
receivers.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 62148-1, Fibre optic active components and devices – Package and interface standards –
Part 1: General and guidance
3 Terms, definitions and abbreviated terms
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1.1
photonic chip scale package
chip O/E and/or E/O convertor, where electrical I/Os and optical I/Os are also included
3.2 Abbreviated terms
CSP chip scale package
O/E optical to electrical
E/O electrical to optical
I/O input/output
SIG signal
TX transmitter
RX receiver
MOD optical modulator
LD laser diode
– 8 – IEC 62148-19:2019 © IEC 2019
MMF multimode fibre
TIA transimpedance amplifier
PCB printed circuit board
PWB printed wiring board
PD photodiode
4 Classification
The photonic chip scale package specified in this document is classified as type 5 according to
the definitions of IEC 62148-1.
5 Specification of photonic chip scale package
5.1 General
Clause 5 specifies the physical requirements of a photonic chip scale package that will enable
mechanical interchangeability of modules complying with this document, both for the PCB and
for any panel mounting requirement.
5.2 General block diagram (silicon photonics)
The block diagram for the photonic chip scale package is shown in Figure 1, which contains N
channels of electrical inputs, M channels of electrical outputs, Q channels of optical outputs,
and R channels of optical inputs.
The functions of electrical to optical (E/O) conversion or/and optical to electrical (O/E)
conversion are provided by the package according to applications.
Channel numbers of electrical inputs N and optical outputs Q in E/O and optical inputs R and
electrical outputs M in O/E are determined according to a multiplexing scheme such as
wavelength multiplexing and serializer/deserializer.
Specific configurations for the photonic chip scale package are shown in Annex A.

Figure 1 – General block diagram for photonic chip scale package

5.3 Electrical interface
5.3.1 General
The electrical interface in this document defines only the basic functionality of each terminal.
5.3.2 Numbering of electrical terminals
Electrical terminal numbering assignments are shown in Figure 2. The location of reference
electrical terminal A1 is assigned at bottom left corner, and the direction of the package is
decided by the position of the optical interface shifted to the left of centre, as shown in Figure 2.

Figure 2 – Electrical terminal numbering assignment (top view)
5.4 Optical interface
5.4.1 General
The optical interface in this document defines only the basic functionality of each optical
terminal. The channel spacing of optical interface has two options of 0,25 mm and 0,125 mm.
5.4.2 Free space optical beam condition
The optical output beam from a surface of the photonic chip scale package is coupled to an
optical fibre or optical waveguide with free space optics, such as optical lenses or butt coupling,
to have a specific coupling efficiency designed by each vendor.
Dimension of optical terminals and beam profiles are characterized in accordance with the
vendor’s specification.
5.5 Outline and footprint
5.5.1 General
The footprint of the photonic chip scale package is determined by the number of channels of
the optical transmitter and/or receiver and the dimensions and pitch of the electrical terminals.
The electrical pad pitch and dimensions of the chip follow the general guidance for a chip scale
package (IEC 62148-21).
– 10 – IEC 62148-19:2019 © IEC 2019
Specific configurations for the photonic chip scale package are shown in Annex A.
5.5.2 Drawing of footprint
The recommended pattern layout for the PCB is shown in Figure 3, and informative electrical
wiring for a high speed electrical interface is shown in Figure 4. The dimensions of
recommended pattern layout for PCB are shown in Table 1.

NOTE e = 0,25 mm
Figure 3 – Recommended pattern layout for PCB

Figure 4 – Informative electrical strip line wiring for high speed electrical interface
Table 1 – Dimensions of recommended pattern layout for PCB
Dimensions
mm
Reference
Minimum Maximum
∅fx 0,13 0,17
Annex A
(normative)
Specific configurations
A.1 General
Specific configurations of chip scale package for multiple channel optical transmitter/receiver
applications are described in Annex A. With options for optical channel spacing of 0,25 mm and
0,125 mm, alternatives of 4-channel transceiver (transmitter and receiver), 8ch transceiver,
12ch transmitter, and 12ch receiver are specified in Clauses A.2 to A.4, as listed in Table A.1.
Table A.1 – Specific configurations specified in Annex A
Configuration Optical channel spacing
0,25 mm 0,125 mm
4ch transceiver A.2 -
8ch transceiver - A.3
12ch transmitter/
- A.4
12ch receiver
A.2 4ch transceiver
A.2.1 Block diagram
The block diagram of a 4ch transceiver is shown in Figure A.1.

– 12 – IEC 62148-19:2019 © IEC 2019

Figure A.1 – Block diagram for chip scale package of 4ch transceiver using silicon
photonics chip with optional pads for LD control
A.2.2 Electrical terminal assignments
Electrical terminal numbering assignments are shown in Figure A.2. Electrical terminals in the
outer two rows and columns (outer two lines) are used. The direction of the package is decided
by the position of the optical interface shifted to the left of centre, as shown in Figure A.2. The
terminal definitions are shown in Table A.2.

Figure A.2 – Electrical terminal numbering assignment (top view)
Table A.2 – Terminal function definitions for a 4ch transceiver
Terminal
Symbol Function
number
A1 GND Ground
A2 GND Ground
A3 GND Ground
A4 VLDDQ LD drive common
A5 VLDDP3 LD power supply 3 (external drive mode)
A6 VLDDP2 LD power supply 2 (external drive mode)
A7 VLDDP1 LD power supply 1 (external drive mode)
A8 GND Ground
A9 VDD Power supply
A10 GND Ground
A11 VPLD LD driver power supply
A12 VDD33 3,3 V power supply
A13 TMON Temperature monitor output
A14 GND Ground
A15 GND Ground
A16 GND Ground
A17 GND Ground
A18 GND Ground
B1 GND Ground
B2 GND Ground
B3 GND Ground
B4 VLDDQ LD drive common
B5 VLDDP3 LD power supply 3 (external drive mode)

– 14 – IEC 62148-19:2019 © IEC 2019
Terminal
Symbol Function
number
B6 VLDDP2 LD power supply 2 (external drive mode)
B7 VLDDP1 LD power supply 1 (external drive mode)
B8 GND Ground
B9 VDD Power supply
B10 GND Ground
B11 VPLD LD driver power supply
B12 VDD33 3,3 V power supply
B13 VDD Power supply
B14 GND Ground
B15 GND Ground
B16 GND Ground
B17 GND Ground
B18 DIP01 Non-inverted input channel 1
C17 GND Ground
C18 DIN01 Inverted input channel 1
D17 GND Ground
D18 DIP02 Non-inverted input channel 2
E17 GND Ground
E18 DIN02 Inverted input channel 2
F17 GND Ground
F18 DIP03 Non-inverted input channel 3
G17 GND Ground
G18 DIN03 Inverted input channel 3
H17 GND Ground
H18 DIP04 Non-inverted input channel 4
J17 GND Ground
J18 DIN04 Inverted input channel 4
K17 GND Ground
K18 DOP01 Non-inverted output channel 1
L17 GND Ground
L18 DON01 Inverted output channel 1
M17 GND Ground
M18 DOP02 Non-inverted output channel 2
N17 GND Ground
N18 DON02 Inverted output channel 2
P17 GND Ground
P18 DOP03 Non-inverted output channel 3
R17 GND Ground
R18 DON03 Inverted output channel 3
T17 GND Ground
T18 DOP04 Non-inverted output channel 4
U1 GND Ground
U2 GND Ground
Terminal
Symbol Function
number
U3 GND Ground
U4 GND Ground
U5 VPD PD bias voltage
U6 VPD PD bias voltage
U7 VDD Power supply
U8 VDD Power supply
U9 GND Ground
U10 VDD Power supply
U11 GND Ground
U12 GND Ground
U13 GND Ground
U14 GND Ground
U15 GND Ground
U16 GND Ground
U17 GND Ground
U18 DON04 Inverted output channel 4
V1 GND Ground
V2 MONOUT Optical power monitor output
V3 VDD33 3,3 V power supply
V4 GPIO General purpose I/O
V5 SCL 2-wire serial interface clock
V6 SDA 2-wire serial interface data
V7 VDD Power supply
V8 GND Ground
V9 VBIAS2 Bias voltage 2
V10 GND Ground
V11 VBIAS1 Bias voltage 1
V12 GND Ground
V13 GND Ground
V14 GND Ground
V15 GND Ground
V16 GND Ground
V17 GND Ground
V18 GND Ground
A.2.3 Optical terminal assignments
Optical terminal numbering assignments for a 0,25 mm pitch 4ch transceiver (4 optical inputs
and 4 optical outputs) are shown in Figure A.3. Direction of the package is decided by the
position of the optical interface shifted to the left of centre, as shown in Figure A.3. The optical
terminal function definitions are shown in Table A.3.

– 16 – IEC 62148-19:2019 © IEC 2019

Figure A.3 – Optical terminal numbering assignment for 0,25 mm pitch optical interface
for 4ch transceiver (top view)
Table A.3 – Optical terminal function definitions for 4ch transceiver
Terminal number Symbol Function
LA OPTOUT01 Optical output 1
LB OPTOUT02 Optical output 2
LC OPTOUT03 Optical output 3
LD OPTOUT04 Optical output 4
LE OPTIN01 Optical input 1
LF OPTIN02 Optical input 2
LG OPTIN03 Optical input 3
LH OPTIN04 Optical input 4
A.2.4 Outline drawing
Package outline drawing and dimensions of the package outline of a 4ch transceiver are shown
in Figure A.4 and Table A.4.
Dimensions in millimetres
Figure A.4 – Package outline drawing of 4ch transceiver
Table A.4 – Dimensions of the package outline of 4ch transceiver
Dimensions
mm
Reference Notes
Minimum Maximum
D 4,82 5,06
D1 0,28 0,41
E 4,82 5,06
E1 0,28 0,41
e - -
F 1,75 1,95
G 2,90 3,10
X 1,224 1,237
Y 0,923 0,935
A 0,76 0,80
A1 0,70 0,74
∅b - 0,13 Electrical I/O
– 18 – IEC 62148-19:2019 © IEC 2019
Dimensions
mm
Reference Notes
Minimum Maximum
a
- 0,035 Optical I/O (Tx)
∅b1
b
- 0,07 Optical I/O (Rx)
∅b2
x1 - 0,02
x2 - 0,005 Relative positional tolerance
x3 - 0,002 Relative positional tolerance
y - 0,01
y1 - 0,01
a
∅b1 is a vendor specific diameter of optical terminal to have a specific coupling efficiency designed by each
vendor. ∅b1 = 0,035 is specific for butt coupling case where the optical beam from optical output terminal is
butt coupled to MMF.
b
∅b2 is a vendor specific diameter of optical terminal to have a specific coupling efficiency designed by each
vendor. ∅b2 = 0,07 is specific for butt coupling case where a beam from MMF is butt coupled to optical input
terminal.
A.3 8ch transceiver
A.3.1 Block diagram
The block diagram for an 8ch transceiver is shown in Figure A.5.

Figure A.5 – Block diagram for chip scale package of 8ch transceiver using silicon
photonics chip with optional pads for LD control
A.3.2 Electrical terminal assignments
Electrical terminal numbering assignments are shown in Figure A.6. Electrical terminals in the
outer two rows and columns (outer two lines) are used. The direction of the package is decided
by the position of optical interface shifted to the left of centre, as shown in Figure A.6. The
terminal definitions are shown in Table A.5.

– 20 – IEC 62148-19:2019 © IEC 2019

Figure A.6 – Electrical terminal numbering assignment (top view)
Table A.5 – Terminal function definitions for 8ch transceiver
Terminal
Symbol Function
number
A1 GND Ground
A2 GND Ground
A3 GND Ground
A4 VLDDQ LD drive common
A5 VLDDP3 LD power supply 3 (external drive mode)
A6 VLDDP2 LD power supply 2 (external drive mode)
A7 VLDDP1 LD power supply 1 (external drive mode)
A8 GND Ground
A9 VDD Power supply
A10 GND Ground
A11 VPLD LD driver power supply
A12 VDD33 3,3 V power supply
A13 TMON Temperature monitor output
A14 GND Ground
A15 DIP01 Non-inverted input channel 1
A16 DIN01 Inverted input channel 1
A17 DIP02 Non-inverted input channel 2
A18 DIN02 Inverted input channel 2
A19 DIP03 Non-inverted input channel 3
A20 DIN03 Inverted input channel 3
B1 GND Ground
B2 GND Ground
B3 GND Ground
Terminal
Symbol Function
number
B4 VLDDQ LD drive common
B5 VLDDP3 LD power supply 3 (external drive mode)
B6 VLDDP2 LD power supply 2 (external drive mode)
B7 VLDDP1 LD power supply 1 (external drive mode)
B8 GND Ground
B9 VDD Power supply
B10 GND Ground
B11 VPLD LD driver power supply
B12 VDD33 3,3 V power supply
B13 VDD Power supply
B14 GND Ground
B15 GND Ground
B16 GND Ground
B17 GND Ground
B18 GND Ground
B19 GND Ground
B20 DIP04 Non-inverted input channel 4
C19 GND Ground
C20 DIN04 Inverted input channel 4
D19 GND Ground
D20 DIP05 Non-inverted input channel 5
E19 GND Ground
E20 DIN05 Inverted input channel 5
F19 GND Ground
F20 DIP06 Non-inverted input channel 6
G19 GND Ground
G20 DIN06 Inverted input channel 6
H19 GND Ground
H20 DIP07 Non-inverted input channel 7
J19 GND Ground
J20 DIN07 Inverted input channel 7
K19 GND Ground
K20 DIP08 Non-inverted input channel 8
L19 GND Ground
L20 DIN08 Inverted input channel 8
M19 GND Ground
M20 DOP01 Non-inverted output channel 1
N19 GND Ground
N20 DON01 Inverted output channel 1
P19 GND Ground
P20 DOP02 Non-inverted output channel 2
R19 GND Ground
R20 DON02 Inverted output channel 2

– 22 – IEC 62148-19:2019 © IEC 2019
Terminal
Symbol Function
number
T19 GND Ground
T20 DOP03 Non-inverted output channel 3
U19 GND Ground
U20 DON03 Inverted output channel 3
V19 GND Ground
V20 DOP04 Non-inverted output channel 4
W19 GND Ground
W20 DON04 Inverted output channel 4
Y19 GND Ground
Y20 DOP05 Non-inverted output channel 5
AA1 GND Ground
AA2 GND Ground
AA3 GND Ground
AA4 GND Ground
AA5 VPD PD bias voltage
AA6 VPD PD bias voltage
AA7 VDD Power supply
AA8 VDD Power supply
AA9 GND Ground
AA10 VDD Power supply
AA11 GND Ground
AA12 GND Ground
AA13 GND Ground
AA14 GND Ground
AA15 GND Ground
AA16 GND Ground
AA17 GND Ground
AA18 GND Ground
AA19 GND Ground
AA20 DON05 Inverted output channel 5
AB1 GND Ground
AB2 MONOUT Optical power monitor output
AB3 VDD33 3,3 V power supply
AB4 GPIO General purpose I/O
AB5 SCL 2-wire serial interface clock
AB6 SDA 2-wire serial interface data
AB7 VDD Power supply
AB8 GND Ground
AB9 VBIAS2 Bias voltage 2
AB10 GND Ground
AB11 VBIAS1 Bias voltage 1
AB12 GND Ground
AB13 GND Ground
Terminal
Symbol Function
number
AB14 GND Ground
AB15 DON08 Inverted output channel 8
AB16 DOP08 Non-inverted output channel 8
AB17 DON07 Inverted output channel 7
AB18 DOP07 Non-inverted output channel 7
AB19 DON06 Inverted output channel 6
AB20 DOP06 Non-inverted output channel 6

A.3.3 Optical terminal assignments
Optical terminal assignments for a 0,125 mm pitch 8ch transceiver (8 optical inputs and 8 optical
outputs) are shown in Figure A.7. Direction of the package is decided by the position of the
optical interface shifted to the left of centre, as shown in Figure A.7.The optical terminal function
definitions are shown in Table A.6.

Figure A.7 – Optical terminal numbering assignment for 0,125 mm pitch optical
interface for 8ch transceiver (top view)

– 24 – IEC 62148-19:2019 © IEC 2019
Table A.6 – Optical terminal function definitions for 8ch transceiver
Terminal number Symbol Function
LA OPTOUT01 Optical output 1
LB OPTOUT02 Optical output 2
LC OPTOUT03 Optical output 3
LD OPTOUT04 Optical output 4
LE OPTOUT05 Optical output 5
LF OPTOUT06 Optical output 6
LG OPTOUT07 Optical output 7
LH OPTOUT08 Optical output 8
LJ OPTIN01 Optical input 1
LK OPTIN02 Optical input 2
LL OPTIN03 Optical input 3
LM OPTIN04 Optical input 4
LP OPTIN05 Optical input 5
LR OPTIN06 Optical input 6
LT OPTIN07 Optical input 7
LU OPTIN08 Optical input 8
A.3.4 Outline drawing
Drawing and dimensions of the package outline of an 8ch transceiver are shown in Figure A.8
and Table A.7.
Dimensions in millimetres
Figure A.8 – Package outline drawing of 8ch transceiver

Table A.7 – Dimensions of the package outline of 8ch transceiver
Dimensions
mm
Reference Notes
Minimum Maximum
D 5,32 5,56
D1 0,28 0,41
E 5,82 6,06
E1 0,28 0,41
F 1,75 2,35
G 3,20 4,20
X 1,22 1,75
Y 1,25 1,50
A 0,76 0,80
A1 0,70 0,74
∅b - 0,13 Electrical I/O
a
- 0,035 Optical I/O (Tx)
∅b1
b
- 0,07 Optical I/O (Rx)
∅b2
x1 - 0,02
x2 - 0,005 Relative positional tolerance
x3 - 0,002
y - 0,01
y1 - 0,01
a
∅b1 is a vendor specific diameter of optical terminal to have a specific coupling efficiency designed by each
vendor. ∅b1 = 0,035 is specific for butt coupling case where the optical beam from optical output terminal is
butt coupled to MMF.
b
∅b2 is a vendor specific diameter of optical terminal to have a specific coupling efficiency designed by each
vendor. ∅b2 = 0,07 is specific for butt coupling case where a beam from MMF is butt coupled to optical input
terminal.
A.4 12ch transmitter and receiver
A.4.1 Block diagram
The block diagrams for a 12ch transmitter and a 12ch receiver are shown in Figures A.9 and
A.10, respectively.
– 26 – IEC 62148-19:2019 © IEC 2019

Figure A.9 – Block diagram for chip scale package of 12ch transmitter using silicon
photonics chip with optional pads for LD control

Figure A.10 – Block diagram for the chip scale package of 12ch receiver with optional
pad for PD bias
A.4.2 Electrical terminal assignments
Electrical terminal numbering assignments are shown in Figure A.11. Electrical terminals in the
outer two rows and columns (outer two lines) are used. The direction of the package is decided
by the position of optical interface shifted to the left of centre as shown in Figure A.11. The
terminal definitions for a 12ch transmitter and a 12ch receiver are shown in Tables A.8 and A.9,
respectively.
Figure A.11 – Electrical terminal numbering assignment (top view)
Table A.8 – Terminal function definitions for 12ch transmitter
Terminal
Symbol Function
number
A1 GND Ground
A2 GND Ground
A3 GND Ground
A4 VLDDQ LD drive common
A5 VLDDP3 LD power supply 3 (external drive mode)
A6 VLDDP2 LD power supply 2 (external drive mode)
A7 VLDDP1 LD power supply 1 (external drive mode)
A8 GND Ground
A9 VDD Power supply
A10 GND Ground
A11 VPLD LD driver power supply
A12 VDD33 3,3 V power supply
A13 TMON Temperature monitor output
A14 DIP01 Non-inverted input channel 01
A15 DIN01 Inverted input channel 01
A16 DIP02 Non-inverted input channel 02
A17 DIN02 Inverted input channel 02

– 28 – IEC 62148-19:2019 © IEC 2019
Terminal
Symbol Function
number
A18 GND Ground
B1 GND Ground
B2 GND Ground
B3 GND Ground
B4 VLDDQ LD drive common
B5 VLDDP3 LD power supply 3 (external drive mode)
B6 VLDDP2 LD power supply 2 (external drive mode)
B7 VLDDP1 LD power supply 1 (external drive mode)
B8 GND Ground
B9 VDD Power supply
B10 GND Ground
B11 VPLD LD driver power supply
B12 VDD33 3,3 V power supply
B13 VDD Power supply
B14 GND Ground
B15 GND Ground
B16 GND Ground
B17 GND Ground
B18 DIP03 Non-inverted input channel 03
C17 GND Ground
C18 DIN03 Inverted input channel 03
D17 GND Ground
D18 DIP04 Non-inverted input channel 04
E17 GND Ground
E18 DIN04 Inverted input channel 04
F17 GND Ground
F18 DIP05 Non-inverted input channel 05
G17 GND Ground
G18 DIN05 Inverted input channel 05
H17 GND Ground
H18 DIP06 Non-inverted input channel 06
J17 GND Ground
J18 DIN06 Inverted input channel 06
K17 GND Ground
K18 DIP07 Non-inverted input channel 07
L17 GND Ground
L18 DIN07 Inverted input channel 07
M17 GND Ground
M18 DIP08 Non-inverted input channel 08
N17 GND Ground
N18 DIN08 Inverted input channel 08
P17 GND Ground
P18 DIP09 Non-inverted input channel 09

Terminal
Symbol Function
number
R17 GND Ground
R18 DIN09 Inverted input channel 09
T17 GND Ground
T18 DIP10 Non-inverted input channel 10
U1 GND Ground
U2 GND Ground
U3 GND Ground
U4 GND Ground
U5 VDD Power supply
U6 VDD Power supply
U7 VDD Power supply
U8 VDD Power supply
U9 GND Ground
U10 VDD Power supply
U11 GND Ground
U12 GND Ground
U13 GND Ground
U14 GND Ground
U15 GND Ground
U16 GND Ground
U17 GND Ground
U18 DIN10 Inverted input channel 10
V1 GND Ground
V2 MONOUT Optical power monitor output
V3 VDD33 3,3 V power supply
V4 GPIO General purpose I/O
V5 SCL 2-wire serial interface clock
V6 SDA 2-wire serial interface data
V7 VDD Power supply
V8 GND Ground
V9 VBIAS2 Bias voltage 2
V10 GND Ground
V11 VBIAS1 Bias voltage 1
V12 GND Ground
V13 GND Ground
V14 DIN12 Inverted input channel 12
V15 DIP12 Non-inverted input channel 12
V16 DIN11 Inverted input channel 11
V17 DIP11 Non-inverted input channel 11
V18 GND Ground
– 30 – IEC 62148-19:2019 © IEC 2019
Table A.9 – Terminal function definitions for 12ch receiver
Terminal
Symbol Function
number
A1 GND Ground
A2 GND Ground
A3 GND Ground
A4 VPD PD bias voltage
A5 VPD PD bias voltage
A6 VDD Power supply
A7 VDD Power supply
A8 GND Ground
A9 VDD Power supply
A10 GND Ground
A11 GND Ground
A12 VDD33 3,3 V power supply
A13 TMON Temperature monitor output
A14 DOP01 Non-inverted output channel 01
A15 DON01 Inverted output channel 01
A16 DOP02 Non-inverted output channel 02
A17 DON02 Inverted output channel 02
A18 GND Ground
B1 GND Ground
B2 GND Ground
B3 GND Ground
B4 VPD PD bias voltage
B5 VPD PD bias voltage
B6 VDD Power supply
B7 VDD Power supply
B8 GND Ground
B9 VDD Power supply
B10 GND Ground
B11 GND Ground
B12 VDD33 3,3 V power supply
B13 VDD Power supply
B14 GND Ground
B15 GND Ground
B16 GND Ground
B17 GND Ground
B18 DOP03 Non-inverted output channel 03
C17 GND Ground
C18 DON03 Inverted output channel 03
D17 GND Ground
D18 DOP04 Non-inverted output channel 04
E17 GND Ground
E18 DON04 Inverted output channel 04

Terminal
Symbol Function
number
F17 GND Ground
F18 DOP05 Non-inverted output channel 05
G17 GND Ground
G18 DON05 Inverted output channel 05
H17 GND Ground
H18 DOP06 Non-inver
...

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