Fibre optic active components and devices - Package and interface standards - Part 19: Photonic chip scale package

IEC 62148-19: 2019 covers the photonic chip scale package. The purpose of this document is to specify adequately the physical requirements of optical transmitters and receivers that will enable mechanical interchangeability of transmitters and receivers.
Keywords: physical interface for photonic chip scale packages

Composants et dispositifs actifs fibroniques - Normes de boîtier et d’interface - Partie 19 : Boîtier à puce photonique

L'IEC 62148-19: 2019 couvre les boîtiers à puces photoniques. L'objectif du présent document est de spécifier les exigences physiques des modules d'émission et de réception optique qui permettent l'interchangeabilité mécanique des émetteurs et transmetteurs.
Mots-clés: interface physique des boîtiers à puces photoniques

General Information

Status
Published
Publication Date
01-May-2019
Current Stage
PPUB - Publication issued
Completion Date
02-May-2019
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IEC 62148-19
Edition 1.0 2019-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Fibre optic active components and devices – Package and interface standards –
Part 19: Photonic chip scale package

Composants et dispositifs actifs fibroniques – Normes de boîtier et d'interface –

Partie 19: Boîtier à puce photonique
IEC 62148-19:2019-05(en-fr)
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC 62148-19
Edition 1.0 2019-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Fibre optic active components and devices – Package and interface standards –
Part 19: Photonic chip scale package

Composants et dispositifs actifs fibroniques – Normes de boîtier et d'interface –

Partie 19: Boîtier à puce photonique
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 33.180.20 ISBN 978-2-8322-6869-8

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – IEC 62148-19:2019 © IEC 2019
CONTENTS

FOREWORD ........................................................................................................................... 4

INTRODUCTION ..................................................................................................................... 6

1 Scope .............................................................................................................................. 7

2 Normative references ...................................................................................................... 7

3 Terms, definitions and abbreviated terms ........................................................................ 7

3.1 Terms and definitions .............................................................................................. 7

3.2 Abbreviated terms ................................................................................................... 7

4 Classification ................................................................................................................... 8

5 Specification of photonic chip scale package ................................................................... 8

5.1 General ................................................................................................................... 8

5.2 General block diagram (silicon photonics) ............................................................... 8

5.3 Electrical interface .................................................................................................. 9

5.3.1 General ........................................................................................................... 9

5.3.2 Numbering of electrical terminals ..................................................................... 9

5.4 Optical interface ...................................................................................................... 9

5.4.1 General ........................................................................................................... 9

5.4.2 Free space optical beam condition ................................................................... 9

5.5 Outline and footprint ............................................................................................... 9

5.5.1 General ........................................................................................................... 9

5.5.2 Drawing of footprint ....................................................................................... 10

Annex A (normative) Specific configurations ........................................................................ 11

A.1 General ................................................................................................................. 11

A.2 4ch transceiver ..................................................................................................... 11

A.2.1 Block diagram ................................................................................................ 11

A.2.2 Electrical terminal assignments ..................................................................... 12

A.2.3 Optical terminal assignments ......................................................................... 15

A.2.4 Outline drawing ............................................................................................. 16

A.3 8ch transceiver ..................................................................................................... 18

A.3.1 Block diagram ................................................................................................ 18

A.3.2 Electrical terminal assignments ..................................................................... 19

A.3.3 Optical terminal assignments ......................................................................... 23

A.3.4 Outline drawing ............................................................................................. 24

A.4 12ch transmitter and receiver ................................................................................ 25

A.4.1 Block diagram ................................................................................................ 25

A.4.2 Electrical terminal assignments ..................................................................... 27

A.4.3 Optical terminal assignments ......................................................................... 32

A.4.4 Outline drawing ............................................................................................. 34

Bibliography .......................................................................................................................... 38

Figure 1 – General block diagram for photonic chip scale package ......................................... 8

Figure 2 – Electrical terminal numbering assignment (top view) .............................................. 9

Figure 3 – Recommended pattern layout for PCB .................................................................. 10

Figure 4 – Informative electrical strip line wiring for high speed electrical interface ............... 10

Figure A.1 – Block diagram for chip scale package of 4ch transceiver using silicon

photonics chip with optional pads for LD control.................................................................... 12

---------------------- Page: 4 ----------------------
IEC 62148-19:2019 © IEC 2019 – 3 –

Figure A.2 – Electrical terminal numbering assignment (top view) ......................................... 13

Figure A.3 – Optical terminal numbering assignment for 0,25 mm pitch optical interface

for 4ch transceiver (top view) ................................................................................................ 16

Figure A.4 – Package outline drawing of 4ch transceiver ...................................................... 17

Figure A.5 – Block diagram for chip scale package of 8ch transceiver using silicon

photonics chip with optional pads for LD control.................................................................... 19

Figure A.6 – Electrical terminal numbering assignment (top view) ......................................... 20

Figure A.7 – Optical terminal numbering assignment for 0,125 mm pitch optical

interface for 8ch transceiver (top view) ................................................................................. 23

Figure A.8 – Package outline drawing of 8ch transceiver ...................................................... 24

Figure A.9 – Block diagram for chip scale package of 12ch transmitter using silicon

photonics chip with optional pads for LD control.................................................................... 26

Figure A.10 – Block diagram for the chip scale package of 12ch receiver with optional

pad for PD bias ..................................................................................................................... 26

Figure A.11 – Electrical terminal numbering assignment (top view) ....................................... 27

Figure A.12 – Optical terminal numbering assignment for 0,125 mm pitch optical

interface for 12ch transmitter and receiver (top view) ............................................................ 33

Figure A.13 – Package outline drawing of 12ch transmitter ................................................... 34

Figure A.14 – Package outline drawing of 12ch receiver ....................................................... 36

Table 1 – Dimensions of recommended pattern layout for PCB ............................................. 10

Table A.1 – Specific configurations specified in Annex A ...................................................... 11

Table A.2 – Terminal function definitions for a 4ch transceiver .............................................. 13

Table A.3 – Optical terminal function definitions for 4ch transceiver ...................................... 16

Table A.4 – Dimensions of the package outline of 4ch transceiver ........................................ 17

Table A.5 – Terminal function definitions for 8ch transceiver................................................. 20

Table A.6 – Optical terminal function definitions for 8ch transceiver ...................................... 24

Table A.7 – Dimensions of the package outline of 8ch transceiver ........................................ 25

Table A.8 – Terminal function definitions for 12ch transmitter ............................................... 27

Table A.9 – Terminal function definitions for 12ch receiver ................................................... 30

Table A.10 – Optical terminal function definitions for 12ch transmitter .................................. 33

Table A.11 – Optical terminal function definitions for 12ch receiver ....................................... 34

Table A.12 – Dimensions of the package outline of 12ch transmitter ..................................... 35

Table A.13 – Dimensions of the package outline of 12ch receiver ......................................... 36

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– 4 – IEC 62148-19:2019 © IEC 2019
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FIBRE OPTIC ACTIVE COMPONENTS AND DEVICES –
PACKAGE AND INTERFACE STANDARDS –
Part 19: Photonic chip scale package
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international

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rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 62148-19 has been prepared by subcommittee 86C: Fibre optic

systems and active devices, of IEC technical committee 86: Fibre optics.
The text of this International Standard is based on the following documents:
FDIS Report on voting
86C/1574/FDIS 86C/1586/RVD

Full information on the voting for the approval of this International Standard can be found in the

report on voting indicated in the above table.

This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

A list of all parts in the IEC 62148 series, published under the general title Fibre optic active

components and devices – Package and interface standards, can be found on the IEC website.

---------------------- Page: 6 ----------------------
IEC 62148-19:2019 © IEC 2019 – 5 –

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to

the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
---------------------- Page: 7 ----------------------
– 6 – IEC 62148-19:2019 © IEC 2019
INTRODUCTION

A photonic chip scale package is used to convert electrical signals into optical signals and vice-

versa. This document covers the physical interface for photonic chip scale packages. These

modules are designed for use with free space optics or multiple channel optical fibre connectors.

---------------------- Page: 8 ----------------------
IEC 62148-19:2019 © IEC 2019 – 7 –
FIBRE OPTIC ACTIVE COMPONENTS AND DEVICES –
PACKAGE AND INTERFACE STANDARDS –
Part 19: Photonic chip scale package
1 Scope
This part of IEC 62148 covers the photonic chip scale package.

The purpose of this document is to specify adequately the physical requirements of optical

transmitters and receivers that will enable mechanical interchangeability of transmitters and

receivers.
2 Normative references

The following documents are referred to in the text in such a way that some or all of their content

constitutes requirements of this document. For dated references, only the edition cited applies.

For undated references, the latest edition of the referenced document (including any

amendments) applies.

IEC 62148-1, Fibre optic active components and devices – Package and interface standards –

Part 1: General and guidance
3 Terms, definitions and abbreviated terms
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1.1
photonic chip scale package

chip O/E and/or E/O convertor, where electrical I/Os and optical I/Os are also included

3.2 Abbreviated terms
CSP chip scale package
O/E optical to electrical
E/O electrical to optical
I/O input/output
SIG signal
TX transmitter
RX receiver
MOD optical modulator
LD laser diode
---------------------- Page: 9 ----------------------
– 8 – IEC 62148-19:2019 © IEC 2019
MMF multimode fibre
TIA transimpedance amplifier
PCB printed circuit board
PWB printed wiring board
PD photodiode
4 Classification

The photonic chip scale package specified in this document is classified as type 5 according to

the definitions of IEC 62148-1.
5 Specification of photonic chip scale package
5.1 General

Clause 5 specifies the physical requirements of a photonic chip scale package that will enable

mechanical interchangeability of modules complying with this document, both for the PCB and

for any panel mounting requirement.
5.2 General block diagram (silicon photonics)

The block diagram for the photonic chip scale package is shown in Figure 1, which contains N

channels of electrical inputs, M channels of electrical outputs, Q channels of optical outputs,

and R channels of optical inputs.

The functions of electrical to optical (E/O) conversion or/and optical to electrical (O/E)

conversion are provided by the package according to applications.

Channel numbers of electrical inputs N and optical outputs Q in E/O and optical inputs R and

electrical outputs M in O/E are determined according to a multiplexing scheme such as

wavelength multiplexing and serializer/deserializer.

Specific configurations for the photonic chip scale package are shown in Annex A.

Figure 1 – General block diagram for photonic chip scale package
---------------------- Page: 10 ----------------------
IEC 62148-19:2019 © IEC 2019 – 9 –
5.3 Electrical interface
5.3.1 General

The electrical interface in this document defines only the basic functionality of each terminal.

5.3.2 Numbering of electrical terminals

Electrical terminal numbering assignments are shown in Figure 2. The location of reference

electrical terminal A1 is assigned at bottom left corner, and the direction of the package is

decided by the position of the optical interface shifted to the left of centre, as shown in Figure 2.

Figure 2 – Electrical terminal numbering assignment (top view)
5.4 Optical interface
5.4.1 General

The optical interface in this document defines only the basic functionality of each optical

terminal. The channel spacing of optical interface has two options of 0,25 mm and 0,125 mm.

5.4.2 Free space optical beam condition

The optical output beam from a surface of the photonic chip scale package is coupled to an

optical fibre or optical waveguide with free space optics, such as optical lenses or butt coupling,

to have a specific coupling efficiency designed by each vendor.

Dimension of optical terminals and beam profiles are characterized in accordance with the

vendor’s specification.
5.5 Outline and footprint
5.5.1 General

The footprint of the photonic chip scale package is determined by the number of channels of

the optical transmitter and/or receiver and the dimensions and pitch of the electrical terminals.

The electrical pad pitch and dimensions of the chip follow the general guidance for a chip scale

package (IEC 62148-21).
---------------------- Page: 11 ----------------------
– 10 – IEC 62148-19:2019 © IEC 2019

Specific configurations for the photonic chip scale package are shown in Annex A.

5.5.2 Drawing of footprint

The recommended pattern layout for the PCB is shown in Figure 3, and informative electrical

wiring for a high speed electrical interface is shown in Figure 4. The dimensions of

recommended pattern layout for PCB are shown in Table 1.
NOTE e = 0,25 mm
Figure 3 – Recommended pattern layout for PCB

Figure 4 – Informative electrical strip line wiring for high speed electrical interface

Table 1 – Dimensions of recommended pattern layout for PCB
Dimensions
Reference
Minimum Maximum
∅fx 0,13 0,17
---------------------- Page: 12 ----------------------
IEC 62148-19:2019 © IEC 2019 – 11 –
Annex A
(normative)
Specific configurations
A.1 General

Specific configurations of chip scale package for multiple channel optical transmitter/receiver

applications are described in Annex A. With options for optical channel spacing of 0,25 mm and

0,125 mm, alternatives of 4-channel transceiver (transmitter and receiver), 8ch transceiver,

12ch transmitter, and 12ch receiver are specified in Clauses A.2 to A.4, as listed in Table A.1.

Table A.1 – Specific configurations specified in Annex A
Configuration Optical channel spacing
0,25 mm 0,125 mm
4ch transceiver A.2 -
8ch transceiver - A.3
12ch transmitter/
- A.4
12ch receiver
A.2 4ch transceiver
A.2.1 Block diagram
The block diagram of a 4ch transceiver is shown in Figure A.1.
---------------------- Page: 13 ----------------------
– 12 – IEC 62148-19:2019 © IEC 2019

Figure A.1 – Block diagram for chip scale package of 4ch transceiver using silicon

photonics chip with optional pads for LD control
A.2.2 Electrical terminal assignments

Electrical terminal numbering assignments are shown in Figure A.2. Electrical terminals in the

outer two rows and columns (outer two lines) are used. The direction of the package is decided

by the position of the optical interface shifted to the left of centre, as shown in Figure A.2. The

terminal definitions are shown in Table A.2.
---------------------- Page: 14 ----------------------
IEC 62148-19:2019 © IEC 2019 – 13 –
Figure A.2 – Electrical terminal numbering assignment (top view)
Table A.2 – Terminal function definitions for a 4ch transceiver
Terminal
Symbol Function
number
A1 GND Ground
A2 GND Ground
A3 GND Ground
A4 VLDDQ LD drive common
A5 VLDDP3 LD power supply 3 (external drive mode)
A6 VLDDP2 LD power supply 2 (external drive mode)
A7 VLDDP1 LD power supply 1 (external drive mode)
A8 GND Ground
A9 VDD Power supply
A10 GND Ground
A11 VPLD LD driver power supply
A12 VDD33 3,3 V power supply
A13 TMON Temperature monitor output
A14 GND Ground
A15 GND Ground
A16 GND Ground
A17 GND Ground
A18 GND Ground
B1 GND Ground
B2 GND Ground
B3 GND Ground
B4 VLDDQ LD drive common
B5 VLDDP3 LD power supply 3 (external drive mode)
---------------------- Page: 15 ----------------------
– 14 – IEC 62148-19:2019 © IEC 2019
Terminal
Symbol Function
number
B6 VLDDP2 LD power supply 2 (external drive mode)
B7 VLDDP1 LD power supply 1 (external drive mode)
B8 GND Ground
B9 VDD Power supply
B10 GND Ground
B11 VPLD LD driver power supply
B12 VDD33 3,3 V power supply
B13 VDD Power supply
B14 GND Ground
B15 GND Ground
B16 GND Ground
B17 GND Ground
B18 DIP01 Non-inverted input channel 1
C17 GND Ground
C18 DIN01 Inverted input channel 1
D17 GND Ground
D18 DIP02 Non-inverted input channel 2
E17 GND Ground
E18 DIN02 Inverted input channel 2
F17 GND Ground
F18 DIP03 Non-inverted input channel 3
G17 GND Ground
G18 DIN03 Inverted input channel 3
H17 GND Ground
H18 DIP04 Non-inverted input channel 4
J17 GND Ground
J18 DIN04 Inverted input channel 4
K17 GND Ground
K18 DOP01 Non-inverted output channel 1
L17 GND Ground
L18 DON01 Inverted output channel 1
M17 GND Ground
M18 DOP02 Non-inverted output channel 2
N17 GND Ground
N18 DON02 Inverted output channel 2
P17 GND Ground
P18 DOP03 Non-inverted output channel 3
R17 GND Ground
R18 DON03 Inverted output channel 3
T17 GND Ground
T18 DOP04 Non-inverted output channel 4
U1 GND Ground
U2 GND Ground
---------------------- Page: 16 ----------------------
IEC 62148-19:2019 © IEC 2019 – 15 –
Terminal
Symbol Function
number
U3 GND Ground
U4 GND Ground
U5 VPD PD bias voltage
U6 VPD PD bias voltage
U7 VDD Power supply
U8 VDD Power supply
U9 GND Ground
U10 VDD Power supply
U11 GND Ground
U12 GND Ground
U13 GND Ground
U14 GND Ground
U15 GND Ground
U16 GND Ground
U17 GND Ground
U18 DON04 Inverted output channel 4
V1 GND Ground
V2 MONOUT Optical power monitor output
V3 VDD33 3,3 V power supply
V4 GPIO General purpose I/O
V5 SCL 2-wire serial interface clock
V6 SDA
...

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