IEC 62530:2021
(Main)SystemVerilog - Unified Hardware Design, Specification, and Verification Language
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.
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IEC 62530
®
Edition 3.0 2021-07
™
IEEE Std 1800
INTERNATIONAL
STANDARD
SystemVerilog – Unified Hardware Design, Specification, and Verification
Language
IEC 62530:2021-07(en) IEEE Std 1800-2017
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IEC 62530
®
Edition 3.0 2021-07
IEEE Std 1800™
INTERNATIONAL
STANDARD
SystemVerilog – Unified Hardware Design, Specification, and Verification
Language
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01; 35.060 ISBN 978-2-8322-9977-7
Warning! Make sure that you obtained this publication from an authorized distributor.
® Registered trademark of the International Electrotechnical Commission
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IEC 62530:2021 © IEC 2021
IEEE Std 1800 ™-2017
Contents
Part One: Design and Verification Constructs
1. Overview. 38
1.1 Scope. 38
1.2 Purpose. 38
1.3 Content summary. 38
1.4 Special terms. 39
1.5 Conventions used in this standard . 39
1.6 Syntactic description. 40
1.7 Use of color in this standard . 40
1.8 Contents of this standard. 41
1.9 Deprecated clauses.
...
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