IEC 62530:2021

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

General Information

• Status: Published
• Publication Date: 25-Jul-2021
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.060 - Languages used in information technology
• Technical Committee: TC 91 - Electronics assembly technology
• Current Stage: PPUB - Publication issued
• Start Date: 04-Jun-2021
• Completion Date: 26-Jul-2021

Relations

• Revises: IEC 62530:2011 - SystemVerilog - Unified Hardware Design, Specification, and Verification Language
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 62530 ®
Edition 3.0 2021-07
™
IEEE Std 1800
INTERNATIONAL
STANDARD
SystemVerilog – Unified Hardware Design, Specification, and Verification
Language
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IEC 62530 ®
Edition 3.0 2021-07
IEEE Std 1800™
INTERNATIONAL
STANDARD
SystemVerilog – Unified Hardware Design, Specification, and Verification

Language
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01; 35.060 ISBN 978-2-8322-9977-7

IEEE Std 1800 ™-2017
Contents
Part One: Design and Verification Constructs
1. Overview. 38
1.1 Scope. 38
1.2 Purpose. 38
1.3 Content summary. 38
1.4 Special terms. 39
1.5 Conventions used in this standard . 39
1.6 Syntactic description. 40
1.7 Use of color in this standard . 40
1.8 Contents of this standard. 41
1.9 Deprecated clauses. 44
1.10 Examples. 44
1.11 Prerequisites. 44
2. Normative references. 45
3. Design and verification building blocks . 47
3.1 General. 47
3.2 Design elements. 47
3.3 Modules . 47
3.4 Programs . 48
3.5 Interfaces. 49
3.6 Checkers. 50
3.7 Primitives . 50
3.8 Subroutines . 50
3.9 Packages. 50
3.10 Configurations . 51
3.11 Overview of hierarchy . 51
3.12 Compilation and elaboration. 52
3.13 Name spaces . 54
3.14 Simulation time units and precision. 55
4. Scheduling semantics. 59
4.1 General. 59
4.2 Execution of a hardware model and its verification environment . 59
4.3 Event simulation . 59
4.4 Stratified event scheduler. 60
4.5 SystemVerilog simulation reference algorithm . 65
4.6 Determinism. 65
4.7 Nondeterminism. 66
4.8 Race conditions. 66
This is a copyrighted Published by IEC under licence IEEE Standard. For personal from IEEE. © 2017 IEEE. or standards development All rights reserved.use only.
IEEE Std 1800 ™-2017
4.9 Scheduling implication of assignments . 66
4.10 PLI callback control points . 68
5. Lexical conventions . 69
5.1 General. 69
5.2 Lexical tokens . 69
5.3 White space. 69
5.4 Comments . 69
5.5 Operators. 69
5.6 Identifiers, keywords, and system names . 70
5.7 Numbers. 71
5.8 Time literals . 76
5.9 String literals. 76
5.10 Structure literals. 78
5.11 Array literals . 79
5.12 Attributes . 79
5.13 Built-in methods . 81
6. Data types . 83
6.1 General. 83
6.2 Data types and data objects. 83
6.3 Value set . 83
6.4 Singular and aggregate types . 84
6.5 Nets and variables. 85
6.6 Net types . 86
6.7 Net declarations . 97
6.8 Variable declarations . 100
6.9 Vector declarations . 102
6.10 Implicit declarations . 103
6.11 Integer data types . 104
6.12 Real, shortreal, and realtime data types . 105
6.13 Void data type. 105
6.14 Chandle data type. 105
6.15 Class. 106
6.16 String data type . 106
6.17 Event data type. 112
6.18 User-defined types . 112
6.19 Enumerations . 114
6.20 Constants. 119
6.21 Scope and lifetime . 126
6.22 Type compatibility. 128
6.23 Type operator. 131
6.24 Casting . 132
6.25 Parameter
...