IEC 60747-15:2010

Semiconductor devices - Discrete devices - Part 15: Isolated power semiconductor devices

IEC 60747-15:2010 gives the requirements for isolated power semiconductor devices excluding devices with incorporated control circuits. These requirements are additional to those given in other parts of IEC 60747 for the corresponding non-isolated power devices. The main changes with respect to previous edition are listed below.
a) Clause 3, 4 and 5 were re-edited and some of them were combined to other sub clauses.
b) Clause 6, 7 were re-edited as a part of "Measuring methods" with amendment of suitable addition and deletion.
c) Clause 8 was amended by suitable addition and deletion.
d) Annex C, D and Bibliography were deleted.
This publication is to be read in conjunction with IEC 60747-1:2006.

Dispositifs à semiconducteurs - Dispositifs discrets - Partie 15: Dispositifs de puissance à semiconducteurs isolés

La CEI 60747-15:2010 donne les exigences relatives aux dispositifs de puissance à semi-conducteurs isolés avec circuits de commande intégrés. Ces exigences s'ajoutent à celles données dans d'autres parties de la CEI 60747 pour les dispositifs de puissance non-isolés correspondants. Les modifications principales par rapport à l'édition précédente sont les suivantes:
a) Les Articles 3, 4 et 5 ont été réédités et certains ont été associés à d'autres paragraphes.
b) Les Articles 6 et 7 ont été réédités et font partie des "Méthodes de mesure" avec les ajouts et suppressions correspondants.
c) L'Article 8 a été modifié par les ajouts et suppressions appropriés correspondants.
d) Les Annexes C, D et la Bibliographie ont été supprimées.
Cette publication doit être lue conjointement avec la CEI 60747-1:2006.

General Information

• Status: Published
• Publication Date: 15-Dec-2010
• ICS: 31.080.99 - Other semiconductor devices
• Technical Committee: SC 47E - Discrete semiconductor devices
• Drafting Committee: WG 3 - TC 47/SC 47E/WG 3
• Current Stage: DELPUB - Deleted Publication
• Start Date: 22-Oct-2024
• Completion Date: 29-Jul-2022

Relations

• Revises: IEC 60747-15:2003 - Discrete semiconductor devices - Part 15: Isolated power semiconductor devices
• Effective Date: 05-Sep-2023
• Revised: IEC 60747-15:2024 - Semiconductor devices - Part 15: Discrete devices - Isolated power semiconductor devices
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 60747-15 ®
Edition 2.0 2010-12
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Discrete devices –
Part 15: Isolated power semiconductor devices

Dispositifs à semiconducteurs – Dispositifs discrets –
Partie 15: Dispositifs de puissance à semiconducteurs isolés

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IEC 60747-15 ®
Edition 2.0 2010-12
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Discrete devices –
Part 15: Isolated power semiconductor devices

Dispositifs à semiconducteurs – Dispositifs discrets –
Partie 15: Dispositifs de puissance à semiconducteurs isolés

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
T
CODE PRIX
ICS 31.080.99 ISBN 978-2-88912-310-0
– 2 – 60747-15 Ó IEC:2010
CONTENTS
FOREW ORD . 4
1 Sc o pe . 6
2 Normative references . 6
3 Terms and definitions . 7
4 Letter symbols . 8
4.1 Ge n eral . 8
4.2 Additional subscripts/symbols . 8
4.3 List letter symbols . 8
4.3.1 Voltages and currents . 8
4.3.2 Mechanical symbols . 8
4.3.3 Other symbols . 9
5 Essential ratings (limiting values) and characteristics . 9
5.1 Ge n eral . 9
5.2 Ratings (limiting values). 9
5.2.1 Isolation voltage (V ) . 9
isol
5.2.2 Peak case non-rupture current (I or I ) (where appropriate). 9
RSMC CNR
5.2.3 Terminal current (I ) (where appropriate), . 9
tRMS
5.2.4 Total power dissipation (P ) . 9
tot
5.2.5 Temperatures . 9
5.2.6 Mechanical ratings . 10
5.2.7 Climatic ratings (where appropriate) . 10
5.3 Characteristics . 10
5.3.1 Mechanical characteristics . 10
5.3.2 Parasitic inductance (L ) . 11
p
5.3.3 Parasitic capacitances (C ) . 11
p
5.3.4 Partial discharge inception voltage (V or V ) (where
iM i(RMS)
appropriate) . 11
5.3.5 Partial discharge extinction voltage (V or V ) (where
eM e(RMS)
appropriate) . 11
5.3.6 Thermal resistances . 11
5.3.7 Transient thermal impedance (Z ) . 12
th
6 Measurement methods . 12
6.1 Verification of isolation voltage rating between terminals and base plate
(V ) . 12
isol
6.2 Methods of measurement . 13
6.2.1 Partial discharge inception and extinction voltages (V ) (V ) . 13
i e
6.2.2 Parasitic inductance (L ) . 13
p
6.2.3 Parasitic capacitance terminal to case (C ) . 15
p
6.2.4 Thermal characteristics . 16
7 Acceptance and reliability . 18
7.1 General requirements . 18
7.2 List of endurance tests . 19
7.3 Acceptance defining criteria . 19
7.4 Type tests and routine tests . 19
7.4.1 Type tests . 19
7.4.2 Routine tests . 20
Annex A (informative) Test method of peak case non-rupture current . 21

60747-15 Ó IEC:2010 – 3 –
Annex B (informative) Measuring method of the thickness of thermal compound paste . 24
Bibliography . 25

Figure 1 – Basic circuit diagram for isolation breakdown withstand voltage test (“high
pot test”) with V . 12
isol
Figure 2 – Circuit diagram for measurement of parasitic inductances (L ) . 14
p
Figure 3 – Wave forms . 15
Figure 4 – Circuit diagram for measurement of parasitic capacitance C . 16
p
Figure 5 – Cross-section of an isolated power device with reference points for
temperature measurement of T and T . 17
c s
Figure A.1 – Circuit diagram for test of peak case non-rupture current I . 21
CNR
Figure B.1 – Example of a measuring gauge for a layer of thermal compound paste of
a thickness between 5 mm and 150 mm . 24

Table 1 – Endurance tests . 19
Table 2 – Acceptance defining characteristics for endurance and reliability tests . 19
Table 3 – Minimum type and routine tests for isolated power semiconductor devices . 20

– 4 – 60747-15 Ó IEC:2010
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
DISCRETE DEVICES –
Part 15: Isolated power semiconductor devices

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60747-15 has been prepared by subcommittee 47E: Discrete
semiconductor devices, of IEC technical committee 47: Semiconductor devices.
This second edition of IEC 60747-15 cancels and replaces the first edition published in 2003.
The main changes with respect to previous edition are listed below.
a) Clause 3, 4 and 5 were re-edited and some of them were combined to other sub clauses.
b) Clause 6, 7 were re-edited as a part of “Measuring methods” with amendment of suitable
addition and deletion.
c) Clause 8 was amended by suitable addition and deletion.
d) Annex C, D and Bibliography were deleted.

60747-15 Ó IEC:2010 – 5 –
The text of this standard is based on the following documents:
FDIS Report on voting
47E/403/FDIS 47E/407/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
This International Standard is to be read in conjunction with IEC 60747-1:2006.
A list of all the parts in the IEC 60747 series, under the general title Semiconductor devices –
Discrete devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
– 6 – 60747-15 Ó IEC:2010
SEMICONDUCTOR DEVICES –
DISCRETE DEVICES –
Part 15: Isolated power semiconductor devices

1 Scope
This part of IEC 60747 gives the requirements for isolated power semiconductor devices
excluding devices with incorporated control circuits. These requirements are additional to
those given in other parts of IEC 60747 for the corresponding non-isolated power devices.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60270, High-voltage test techniques – Partial discharge measurements
IEC 60664-1:2007, Insulation coordination for equipment within low-voltage systems – Part 1:
Principles, requirements and tests
IEC 60721-3-3:1994, Classification of environmental conditions – Part 3-3: Classification of
groups of environmental parameters and their severities – Stationary use at weather
protected locations
IEC 60747-1:2006, Semiconductor devices – Part 1: General
IEC 60747-2, Semiconductor devices – Discrete devices and integrated circuits – Part 2:
Rectifier diodes
IEC 60747-6, Semiconductor devices – Part 6: Thyristors
IEC 60747-7, Semiconductor discrete devices and integrated circuits – Part 7: Bipolar
transistors
IEC 60747-8, Semiconductor devices – Part 8: Field-effect transistors
IEC 60747-9, Semiconductor devices – Discrete devices – Part 9: Insulated-gate bipolar
transistors (IGBTs)
IEC 60749-5, Semiconductor devices – Mechanical and climatic test methods – Part 5:
Steady-state temperature humidity bias life test
IEC 60749-6, Semiconductor devices – Mechanical and climatic test methods – Part 6:
Storage at high temperature
IEC 60749-10, Semiconductor devices – Mechanical and climatic test methods – Part 10:
Mechanical shock
IEC 60749-12, Semiconductor devices – Mechanical and climatic test methods – Part 12:
Vibration, variable frequency
60747-15 Ó IEC:2010 – 7 –
IEC 60749-15, Semiconductor devices – Mechanical and climatic test methods – Part 15:
Resistance to soldering temperature for through-hole mounted devices
IEC 60749-21, Semiconductor devices – Mechanical and climatic test methods – Part 21:
Solderability
IEC 60749-25, Semiconductor devices – Mechanical and climatic test methods – Part 25:
Temperature cycling
IEC 60749-34, Semiconductor devices – Mechanical and climatic test methods – Part 34:
Power cycling
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
isolated power semiconductor device
semiconductor power device that contains an integral electrical insulator between the cooling
surface or base plate and any isolated circuit elements
3.2 Constituent parts of the isolated power semiconductor device
3.2.1
switch
any single component that performs a switching function in a electrical circuit, e.g. diode,
thyristor, MOSFET, etc.
NOTE A switch might be a parallel or series connection of several chips with a single functionality.
3.2.2
base plate
part of the package having a cooling surface that transfers the heat from inside to outside
3.2.3
main terminal
terminal having a high potential of the power circuit and carrying the main current. The main
terminal can comprise more than one physical connector.
3.2.4
control terminal
terminal having a low current capability for the purpose of control function, to which the
external control signals are applied or from which sensing parameters are taken
3.2.4.1
high voltage control terminal
terminal electrically connected to an isolated circuit element, but carrying only low current for
control function
NOTE Examples include current shunts and collector sense terminals having the high potential of the main
terminals.
3.2.4.2
low voltage control terminal
terminal having a control function and isolated from the high voltage control terminals
NOTE Examples include the terminals of isolated temperature sensors and isolated gate driver inputs etc.

– 8 – 60747-15 Ó IEC:2010
3.2.5
insulation layer
integrated part of the device case that insulates any part having high potential from the
cooling surface or external heat sink and any isolated circuit element
3.3
peak case non-rupture current
peak current, which will not lead to a rupture of the package, ejecting plasma and massive
particles under specified conditions
3.4
thermal interface material
heat conducting material between base plate and external heat sink
4 Letter symbols
4.1 General
General letter symbols are defined in Clause 4 of IEC 60747-1:2006.
4.2 Additional subscripts/symbols
p = parasitic
t = terminal
isol = isolation
m = mount
4.3 List letter symbols
4.3.1 Voltages and currents
I
Terminal current
tRMS
V
Isolation voltage
isol
Partial discharge inception voltage V
i
Partial discharge extinction voltage V
e
Isolation leakage current I
isol
Peak case non-rupture current (for diode and thyristor devices) I

RSMC
Peak case non-rupture current (for IGBT and MOSFET devices) I
CNR
4.3.2 Mechanical symbols
M
s
Mounting torque for screws to heat sink
M
t
Mounting torque for terminal screws
F
Mounting force
a
Maximum acceleration in all 3 axis (x, y, z)
m
Mass
e
c
Flatness of the case (base-plate)
e
s
Flatness of the cooling surface (heat sink)
R
Zc
Roughness of the case (base plate)
R
Zs
Roughness of the cooling surface (heat sink)
d
(c-s)
Thickness of thermal interface material (case - sink)

60747-15 Ó IEC:2010 – 9 –
4.3.3 Other symbols
P
tot
Total maximum power dissipation per switch at T = 25 °C
c
L
p
Parasitic inductance, effective between terminals and chips (to be specified)
C
p
Parasitic capacitance between terminals and cooling surface (case, base plate,
ground)
r
xx
Lead resistance between terminal x and related switch x’ ’
T
t
Terminal temperature
N
f;p
Number of power load cycles until failure of a percentage p of a population of
devices
5 Essential ratings (limiting values) and characteristics
5.1 General
Isolated power semiconductor devices should be specified as case rated or heat-sink rated
devices. The ratings and characteristics should be quoted at a temperature of 25 °C or
another specified elevated temperature. Requirements for multiple devices having a common
encapsulation see 5.12 of IEC 60747-1:2006.
5.2 Ratings (limiting values)
5.2.1 Isolation voltage (V )
isol
Maximum r. m. s. or d. c. value between main terminals and high voltage control terminals at
one side and low voltage control terminals (where appropriate) and base plate at the other
side for a specified time
5.2.2 Peak case non-rupture current (I or I ) (where appropriate)
RSMC CNR
Maximum value for each main terminal that does not cause the bursting of the case or
emission of plasma and particles
5.2.3 Terminal current (I ) (where appropriate),
tRMS
Maximum r. m. s. value of the current through the main terminal under specified conditions at
minimum mounting torque M and maximum allowed terminal temperature (T = T or

t tmax stg
T £ T )
tmax vjmax
5.2.4 Total power dissipation (P )
tot
Maximum value per switch at T = 25 °C (or T = 25 °C), when T = T , at d.c. load.
c s vj vjmax
5.2.5 Temperatures
5.2.5.1 Solder temperature (T )
sold
Maximum solder temperature T during solder process over a specified solder processing
sold
time t
sold
5.2.5.2 Storage temperature (T )
stg
Minimum and maximum storage temperature

– 10 – 60747-15 Ó IEC:2010
5.2.6 Mechanical ratings
5.2.6.1 Mounting torque of screws to heat sink (M )
s
Minimum mounting torque that shall be applied to the fixing screws to the heat sink
5.2.6.2 Mounting torque of screws to terminals (M )
t
Minimum mounting torque that shall be applied to screwed terminals
5.2.6.3 Mounting force (F)
Minimum mounting force for pressure mounted devices, fixed by clips, that shall be applied to
the isolated pressure contact device
5.2.6.4 Terminal pull-out force (F )
t
Maximum force
5.2.6.5 Acceleration (a)
Maximum value along each axis (x, y, z)
5.2.6.6 Flatness of the heatsink surface (e ) (where appropriate)
S
Maximum deviation from flatness for the heatsink surface over the whole mounting area
5.2.6.7 Roughness of the heatsink surface (R ) (where appropriate)
ZS
Maximum roughness of the heatsink surface over the whole mounting area
5.2.7 Climatic ratings (where appropriate)
Limiting values of environmental parameters for the final application as follows
– ambient temperature
– humidity
– speed and pressure of air
– irradiation by sun and other heat sources
– mechanical active substances
– chemically active substances
– biological issues
shall be described in classes as specified in IEC 60721-3-3:1994, Table 1.
5.3 Characteristics
5.3.1 Mechanical characteristics
5.3.1.1 Creepage distance along surface (d )
s
Minimum value of distance along surface of the insulating material of the device between
terminals of different potential and to base plate
NOTE 1 IEC 60112 (details to comparative tracking index “CTI”) and IEC 60664-1:2007 Subclause 5.2 apply.
NOTE 2 Air gaps between plastic surface and grounded metal or between terminals of opposite polarity smaller
than 1,0 mm (for pollution degree 2), or 1,5 mm (pollution degree 3) shorten the countable creepage distance
considerably (details see 60664-1:2007, examples). This is essential, if dust, moisture or dirt starts to cover the

60747-15 Ó IEC:2010 – 11 –
surface and increases the leakage current over surface, which might start burning the plastic encapsulation
material.
5.3.1.2 Clearance distance in air (d )
a
Minimum value of distance through air between terminals of different potential of the isolated
device and to base plate
NOTE For details, see IEC 60664-1:2007, (Subclause 4.6 and Subclause 5.1) which shows typical examples of
various shapes of clearance distances.
5.3.1.3 Mass (m) of the device
Maximum value excluding accessories (mounting hardware).
5.3.1.4 Flatness of the base plate (e ) (where appropriate)
C
Maximum and minimum allowed deviation from flatness for the base plate and its direction
(convex or concave).
5.3.2 Parasitic inductance (L )
p
Maximum or typical value between the main terminals of each main current path.
5.3.3 Parasitic capacitances (C )
p
Maximum value of parasitic capacitance between the specified main terminal(s) and the
cooling surface.
5.3.4 Partial discharge inception voltage (V or V ) (where appropriate)
iM i(RMS)
Minimum peak value V or r.m.s. value V between the isolated terminals and the base
i(RMS)
iM
plate (details, see IEC 60270).
5.3.5 Partial discharge extinction voltage (V or V ) (where appropriate)

eM e(RMS)
Minimum peak value V or r.m.s. value V between the isolated terminals and the base
eM e(RMS)
plate (for details, see IEC 60270).
5.3.6 Thermal resistances
5.3.6.1 Thermal resistance junction to case for case rated devices (R )
th(j-c)X
Maximum value of thermal resistance junction to a specified reference point at the case (base
plate) per switch “X” (for example of the diode (D), thyristor (T), IGBT (I) or MOSFET (M)).
5.3.6.2 Thermal resistance case to heat sink (R ) (where appropriate)
th(c-s)
Maximum or typical value of thermal resistance between two specified points at the case and
at the heat sink of the case rated device (“module”), when the case is mounted according to
manufacturer’s mounting instructions.
5.3.6.3 Thermal resistance case to heat sink per switch (R ) (where appropriate)
th(c-s)X
Maximum or typical value of thermal resistance between the two specified points of the case
and the heat sink of the switch “X” (for example of the diode (D), thyristor (T), IGBT (I) or
MOSFET (M) ) of the isolated case rated devices (“module”), when the case is mounted
according to the manufacturer’s mounting instructions.

– 12 – 60747-15 Ó IEC:2010
5.3.6.4 Thermal resistance junction to heat sink for heat sink rated devices (R )
th(j-s)X
Maximum or typical value of thermal resistance junction to a specified point at the heat sink
per switch “X” (for example of the diode (D), thyristor (T), IGBT (I) or MOSFET (M)), when the
device is mounted according to the manufacturer’s mounting instructions.
5.3.6.5 Thermal resistance junction to sensor (R ) (where appropriate)
th(j-r)
Value of thermal resistance junction to an integrated temperature sensor, when the device is
mounted according to the manufacturer’s mounting instructions.
NOTE The position of this thermal resistance should be shown in the thermal resistance equivalent circuit.
5.3.7 Transient thermal impedance (Z )
th
Thermal impedance as a function of the time elapsed after a step change of power dissipation
for each thermal resistance specified in Subclause 5.3.6 and shall be specified in one of the
following ways.
6 Measurement methods
6.1 Verification of isolation voltage rating between terminals and base plate (V )
isol
– Purpose
Proof of the ability of the isolated power device to withstand the rated isolation voltage
– Circuit diagram
See Figure 1 below.
S
H
H
n
G
V
DUT
Base plate
A
E
IEC  2976/10
Figure 1 – Basic circuit diagram for isolation breakdown withstand
voltage test (“high pot test”) with V

isol
– Circuit description and requirements
DUT = Device under test
G = voltage source with high impedance, capable to supply V
isol
S = main switch
V = voltmeter for V
isol
60747-15 Ó IEC:2010 – 13 –
A = ammeter or current probe for I
isol
H …H = high potential terminal
1 n
The voltage source G is capable to supply the isolation voltage V as the a. c. or d. c.
isol
voltage with a high internal impedance to limit the possible breakthrough current in case of
breakdown of the DUT.
All main terminals and high voltage control terminals are connected together and connected
to the high potential output terminal H of the voltage source G. The base plate of the DUT,
respectively its metallized cooling surface and all low voltage terminals are connected to
ground potential E. An amperemeter or current probe A is applied to measure the isolation
leakage current.
– Test procedure
Switch S is closed and the voltage is slowly raised to the specified value and maintained at
that value for the specified time. The current measured on ammeter A shall not exceed the
specified value. The voltage is then reduced to zero.
– Specified conditions
Specified in IEC 60664-1:2007.
· Ambient or case temperature
· V
isol
· I as maximum test limit
isol
· Test time t, if less than 60 s
6.2 Methods of measurement
6.2.1 Partial discharge inception and extinction voltages (V ) (V )
i e
Between high potential terminals and base plate (where appropriate). See IEC 60270 and
IEC 60664-1:2007.
6.2.2 Parasitic inductance (L )
p
– Purpose
To measure the parasitic inductance between two main terminals
– Circuit diagram
See Figure 2 below.
– 14 – 60747-15 Ó IEC:2010
+
T D
3 3
C
DUT
L
p1
T D
1 1
G
G
v
CE
E
x1
C
E /C
1 2
L
L
T D
2 2
G
E
x2
L
pn
E
i
- DUT
IEC  2977/10
Figure 2 – Circuit diagram for measurement of parasitic inductances (L )
p
Key
DUT = device under test T1+T2, for example IGBT (Single or Dual – shown – or branch of a three phase
arrangement), fast diode or MOSFET device
C  = main capacitor bank as reservoir
L = load inductance, at least 100 times the parasitic inductance
L
L …L = portions of parasitic inductance L
p1 pn p
I = current probe
DUT
G = voltage source to charge the capacitor
T = DUT, top switch (shown as IGBT in Figure 2)
T = DUT, bottom switch (shown as IGBT in Figure 2), optional

T = auxiliary IGBT switch
60747-15 Ó IEC:2010 – 15 –
V
CC
V, I
v
CE
V
step
t
t t
di /dt
DUT
i
DUT
IEC  2978/10
Figure 3 – Wave forms
– Circuit description and requirements
The circuit of Figure 2 consists of a DC supply G for the charge reservoir C; T is an auxiliary
switch, a gate drive unit for T , the DUT inserted into the test set-up with the gate control
terminals shorted, a dual channel oscilloscope, which senses the voltage V between main
CE
terminals “C ” and “E “, a current probe, which senses the current I through the diode
1 2 DUT
path of the DUT, connected to the dual channel oscilloscope. This measuring method uses
reduced voltage V and the di/dt of diodes incorporated in the device at switch-off, sensing
CC
the voltage at outside main terminals. This is usable for single switch devices as well as for
half bridge circuit devices (DUAL modules).
– Measurement procedure
A pulsed current method is used. Auxiliary transistor T switches the load current to the
inductor L on and off. When T is off, the current freewheels via the diodes of the DUT.
L 3
When T switches on again, it causes the current through the diodes to fall at an almost linear
rate di /dt. During this time (t –t ), the voltage across the DUT forms at step of V
DUT 1 2 step
caused by the internal parasitic inductance at current decline (di /dt). The value of the
DUT
parasitic inductance of the main current path can be calculated from
L = V / |(di /dt)| (1)
p step DUT
NOTE Use low inductance (sheeted) bus baring and low inductance current probe.
6.2.3 Parasitic capacitance terminal to case (C )
p
– Purpose
To measure the parasitic capacitance C between specified main terminal(s) and the case
p
(base plate)
– Circuit diagram
See Figure 4 below.
– 16 – 60747-15 Ó IEC:2010
H
DUT
…
I
V
C
p
Base plate
CM V
I
IEC  2979/10
Figure 4 – Circuit diagram for measurement of parasitic capacitance (C )
p
– Circuit description and requirements
C = parasitic capacitance
p
H = high potential terminal
CM = capacitance meter
– Measurement procedure
Mount the device to a grounded heat sink according to the manufacturer’s mounting
instructions. Connect the current source connector “I ” of the capacitance meter CM to the
specified terminal and connector “I ” to ground (base plate) of the DUT. Connect the voltage
sensing connector of the capacitance meter to test points “V ” and “V ” to ground. CM is set
1 2
to the specified frequency. The capacitance C can be read on CM. For the measurement of
p
the total coupling capacitance C connect all main terminals to each other and proceed with
p
the measurement like described above.
– Specified conditions
·  Measurement frequency f of the CM
6.2.4 Thermal characteristics
6.2.4.1 General description of measuring methods
– Purpose
To measure thermal characteristics between the switch and the cooling system
– Reference points for temperature measurement and description
Same methods should be used as for the corresponding non-isolated device. Thermal
resistance and impedance are measured in the same way as described in the documents for
diodes IEC 60747-2, thyristors IEC 60747-6, bipolar transistors IEC 60747-7, FETs
IEC 60747-8 and IGBTs IEC 60747-9.

60747-15 Ó IEC:2010 – 17 –
Chip 1 Chip n
DUT
T T T T
sX
j1 j2 jn
Isolation layer
Base plate
Thermal interface material
Specified distance
External heat sink
T T T
c1 c2 sn
IEC  2980/10
Key
T = junction temperature of chip 1 to n
j1…n
T = case temperature under chip 1 to n
c1…n
T = heatsink temperature under chip 1 to n
s1.n
T = heatsink temperature at a specified surface point
sX
Figure 5 – Cross-section of an isolated power device
with reference points for temperature measurement of T and T
c s
– Measurement procedure
T is measured by a temperature measuring instrument from underneath through a small hole
c
through the heat sink and any thermal interface material underneath the switch (chip). T is
s
taken from above at hottest accessible point, nearest to the switch (chip) or from underneath
through a specified sack hole ending at 2 (+/-1) mm below the heat sink surface (to be
specified, type test feature). T is determined using indirect methods like described in the
j
individual documents.
NOTE The thermal resistance R and R depends on several mechanical parameters such as type and
th(j-s) th(c-s)
thickness of the used thermal interface material (should be specified in manufacturer’s mounting instructions, for
example 30 to 50mm), the max. deviation of flatness of the cooling surface of the device’s base plate and of the
heat sink and the mounting torque of the fixing screws, as per specified mounting instructions.
6.2.4.2 Thermal resistance junction to case per switch R
th(j-c)
R = (T - T )/P (2)
th(j-c) j c
where
T is the virtual junction temperature of the switch;
j
T is the temperature of the case (base plate) under the switch (chip);
c
P is the power dissipation of a switch (see Figure 5).
6.2.4.3 Thermal resistance case to heat sink per switch (X) R or per device

th(c-s)X
R
th(c-s)
R = (T - T )/P (3)
th(c-s)(X) c s X
where
– 18 – 60747-15 Ó IEC:2010
X is the D (Diode), I (IGBT); M (MOSFET)
T is the temperature taken at the specified point of the case (as above) under the chip
c
T is the temperature of the heat sink, taken at the reference point for testing T specified
s s
P is the complete power dissipation of the switch
X
P is the power dissipation of the complete device
– Specified conditions
· Mounting according manufacturer’s instructions
· Thermal conductivity of the thermal interface material
· Reference points for thermal measurement
NOTE See Annex B for Measuring method of the thickness of thermal interface material.
6.2.4.4 Thermal resistance junction to heat sink per switch R (for heat sink

th(j-s)
rated devices)
R = (T - T )/P (4)
th(j-s) j sn
where
T is the virtual junction temperature of the switch;
j
T is taken at the specified reference point n at the heatsink (see Figure 5);
sn
P is the power dissipation of the switch.
– Specified conditions
· Mounting according manufacturer’s instructions
· Thermal conductivity of the thermal interface material
· Reference points for thermal measurement
6.2.4.5 Transient thermal impedance Z
th
– Measurement circuit and procedure
These are based on former Subclause 6.2.4.2 to 6.2.4.4. Individual documents of the non-
insulated devices apply.
Z = (|T (0) - T (0)| - |T (t) - T (t)|)/P (5)

th(j-c) j c j c
Z = (|T (0) - T (0)| - |T (t) - T (t)|)/P (6)

th(c-s) c s c s
Z = (|T (0) - T (0)| - |T (t) - T (t)|)/P (7)

th(j-s) j s j s
– Specified conditions
· Mounting according manufacturer’s instructions
· Thermal conductivity of the thermal interface material
· Reference points for thermal measurement
7 Acceptance and reliability
7.1 General requirements
In addition to the following subclauses, the requirements applicable to the non-isolated
devices as given in the other relevant parts of IEC 60747 apply.

60747-15 Ó IEC:2010 – 19 –
7.2 List of endurance tests
See Table 1.
Table 1 – Endurance tests
Subclause Environmental Testing – designation Short form Normative references

7.2.1 High temperature reverse bias or high temperature IEC 60749-5
HTRB
blocking
7.2.2 High humidity and high temperature reverse bias or IEC 60749-5
H TRB
high humidity and high temperature blocking
7.2.3 Power cycling (load) capability IEC 60749-34

7.2.4 High temperature storage IEC 60749-6
HTS
7.2.5 Low temperature storage 1
LTS
IEC 60068-2-48
7.2.6 Thermal cycling TC IEC 60749-25;
7.2.7 Resistance to solder heat IEC 60749-15
7.2.8 Solderability IEC 60749-21
7.2.9 Mechanical shock IEC 60749-10
7.2.10 Vibration (variable frequency) IEC 60749-12

7.3 Acceptance defining criteria
Table 2 – Acceptance defining characteristics for endurance and reliability tests
Acceptance
Acceptance
Measurement conditions
criteria
defining
characteristic
I < USL Specified V
isol isol
R Mounting instructions
< USL
th
USL: upper specification limit

7.4 Type tests and routine tests
7.4.1 Type tests
The experience which has been obtained with other isolated power semiconductor devices,
using the same or similar components such as switches or packages, should be considered
when deciding which tests are mandatory.
Type tests are carried out on new products on a sample basis, in order to determine the
electrical and thermal and mechanical and climatic ratings (limiting values) characteristics to
be given in the data sheet and to establish the test limits for future routine tests. Some or all
of the tests should be repeated from time to time on samples drawn from current production
or deliveries so as to confirm that the quality of the product continuously meets the
requirements.
The minimum type tests to be carried out are as follows:
___________
Withdrawn in 2008.
– 20 – 60747-15 Ó IEC:2010
New isolated power semiconductor devices should undergo the type tests listed in Table 3,
marked with “X” (X = mandatory). Some of the type tests are destructive.
Table 3 – Minimum type and routine tests for isolated power semiconductor devices
Subclause Type test Routine test Destructive

Isolation voltage test V
5.2.1 X X
isol
X
a
5.2.2   Peak case non-rupture current I ; I X
RSMC CNR
5.3.1  outline dimensions, creepage, clearance X
b
5.3.1.4  flatness of base-plate or of cooling surface X X
5.3.6  thermal resistances R X
th
5.3.7  transient thermal impedance Z X
th
a
5.3.2  parasitic inductance L X
p
a
5.3.3  parasitic capacitance C X
p
a
5.3.4/5  partial discharge voltages X
b
5.2.6.4  terminal pull out force X X
c
7.2.6  thermal cycling   X
c
7.2.3  power cycling (load) X
c
7.2.9/10  mechanical tests X
a
5.2.7  climatic characteristics classification X
NOTE Tests for isolation voltage, partial discharge voltage, creepage and clearance distance should be based on
each standard which should be applied to any final equipment using the isolated power semiconductor device. For
example see IEC 60950 (Safety information technology, IEC 61287 (rolling stock) etc.
a
Type test only for devices with specified maximum values.
b
Routine test only for devices with specified maximum or minimum values.
c See Table 1 for normative references of test.

7.4.2 Routine tests
The routine tests should be carried out on the current
...