IEC 62215-3:2013

Integrated circuits - Measurement of impulse immunity - Part 3: Non-synchronous transient injection method

IEC 62215-3:2013 specifies a method for measuring the immunity of an integrated circuit (IC) to standardized conducted electrical transient disturbances. The disturbances, not necessarily synchronized to the operation of the device under test (DUT), are applied to the IC pins via coupling networks. This method enables understanding and classification of interaction between conducted transient disturbances and performance degradation induced in ICs regardless of transients within or beyond the specified operating voltage range.

Circuits intégrés - Mesure de l'immunité aux impulsions - Partie 3: Méthode d'injection de transitoires non synchrones

La CEI 62215-3:2013 spécifie une méthode pour mesurer l'immunité d'un circuit intégré (CI) aux perturbations transitoires électriques conduites normalisées. Les perturbations, non nécessairement synchronisées sur le fonctionnement du dispositif en essai (DUT, device under test), sont appliquées aux broches du circuit intégré via des réseaux de couplage. Cette méthode permet de comprendre et de classer les interactions entre des perturbations transitoires conduites et la dégradation de fonctionnement induite dans les circuits intégrés indépendamment des transitoires à l'intérieur ou au-delà de la gamme de tensions de fonctionnement spécifiées.

General Information

• Status: Published
• Publication Date: 16-Jul-2013
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 9 - TC 47/SC 47A/WG 9
• Current Stage: PPUB - Publication issued
• Start Date: 17-Jul-2013
• Completion Date: 31-Aug-2013

Standards Content (Sample)

IEC 62215-3 ®
Edition 1.0 2013-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Integrated circuits – Measurement of impulse immunity –
Part 3: Non-synchronous transient injection method

Circuits intégrés – Mesure de l'immunité aux impulsions –
Partie 3: Méthode d'injection de transitoires non synchrones

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IEC 62215-3 ®
Edition 1.0 2013-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Integrated circuits – Measurement of impulse immunity –

Part 3: Non-synchronous transient injection method

Circuits intégrés – Mesure de l'immunité aux impulsions –

Partie 3: Méthode d'injection de transitoires non synchrones

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX V
ICS 31.200 ISBN 978-2-8322-0994-3

– 2 – 62215-3 © IEC:2013
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 General . 8
5 Coupling networks . 9
5.1 General on coupling networks . 9
5.2 Supply injection network . 9
5.2.1 Direct injection . 9
5.2.2 Capacitive coupling . 10
5.3 Input injection . 10
5.4 Output injection . 11
5.5 Simultaneous multiple pin injection . 12
6 IC configuration and evaluation . 12
6.1 IC configuration and operating modes . 12
6.2 IC monitoring . 13
6.3 IC performance classes . 13
7 Test conditions . 14
7.1 General . 14
7.2 Ambient electromagnetic environment . 14
7.3 Ambient temperature . 14
7.4 IC supply voltage . 14
8 Test equipment . 14
8.1 General requirements for test equipment . 14
8.2 Cables . 14
8.3 Shielding . 14
8.4 Transient generator . 14
8.5 Power supply . 14
8.6 Monitoring and stimulation equipment . 14
8.7 Control unit . 15
9 Test set up . 15
9.1 General . 15
9.2 EMC test board . 15
10 Test procedure . 17
10.1 Test plan . 17
10.2 Test preparation . 17
10.3 Characterization of coupled impulses . 17
10.4 Impulse immunity measurement . 17
10.5 Interpretation and comparison of results . 18
10.6 Transient immunity acceptance level . 18
11 Test report . 18
Annex A (informative) Test board recommendations . 19
Annex B (informative) Selection hints for coupling and decoupling network values . 24
Annex C (informative) Industrial and consumer applications . 26
Annex D (informative) Vehicle applications . 29

62215-3 © IEC:2013 – 3 –
Figure 1 – Typical pin injection test implementation . 9
Figure 2 – Supply pin direct injection test implementation . 10
Figure 3 – Supply pin capacitive injection test implementation . 10
Figure 4 – Input pin injection test implementation . 11
Figure 5 – Output pin injection test implementation . 12
Figure 6 – Multiple pin injection test implementation . 12
Figure 7 – Test set-up diagram . 15
Figure 8 – Example of the routing from the injection port to a pin of the DUT . 16
Figure A.1 – Typical EMC test board topology. 22
Figure A.2 – Example of implementation of multiple injection structures . 23

Table A.1 – Position of vias over the board . 19
Table C.1 – Definition of pin types . 26
Table C.2 – Test circuit values . 27
Table C.3 – Example of IC impulse test level (IEC 61000-4-4) . 28
Table D.1 – IC pin type definition . 29
Table D.2 – Transient test level 12 V (ISO 7637-2) . 30
Table D.3 – Transient test level 24 V (ISO 7637-2) . 31
Table D.4 – Example of transient test specification . 32

– 4 – 62215-3 © IEC:2013
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
MEASUREMENT OF IMPULSE IMMUNITY –

Part 3: Non-synchronous transient injection method

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62215-3 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this standard is based on the following documents:
CDV Report on voting
47A/881/CDV 47A/890/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62215 series, published under the general title Integrated circuits
– Measurement of impulse immunity can be found on the IEC website.

62215-3 © IEC:2013 – 5 –
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
– 6 – 62215-3 © IEC:2013
INTEGRATED CIRCUITS –
MEASUREMENT OF IMPULSE IMMUNITY –

Part 3: Non-synchronous transient injection method

1 Scope
This part of IEC 62215 specifies a method for measuring the immunity of an integrated circuit
(IC) to standardized conducted electrical transient disturbances. The disturbances, not
necessarily synchronized to the operation of the device under test (DUT), are applied to the
IC pins via coupling networks. This method enables understanding and classification of
interaction between conducted transient disturbances and performance degradation induced
in ICs regardless of transients within or beyond the specified operating voltage range.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60050 (all parts), International Electrotechnical Vocabulary (IEV) (available at
)
IEC 61000-4-4:2012, Electromagnetic compatibility (EMC) – Part 4-4: Testing and
measurement techniques – Electrical fast transient/burst immunity test
IEC 61000-4-5:2005, Electromagnetic compatibility (EMC) – Part 4-5: Testing and
measurement techniques – Surge immunity test
IEC 62132-4:2006, Integrated circuits – Measurement of electromagnetic immunity 150 kHz to
1 GHz – Part 4: Direct RF power injection method
ISO 7637-2:2011, Road vehicles – Electrical disturbances from conduction and coupling –
Part 2: Electrical transient conduction along supply lines only
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60050-131 and
IEC 60050-161, some of which have been added for convenience, as well as the following
apply.
3.1
auxiliary equipment
equipment not under test but is indispensable for setting up all the functions and assessing
the correct performance (operation) of the equipment under test (EUT) during its exposure to
the disturbance
3.2
burst
sequence of a limited number of distinct impulses or an oscillation of limited duration

62215-3 © IEC:2013 – 7 –
3.3
coupling network
electrical circuit for transferring energy from one circuit to another with well-defined
impedance and known transfer characteristics
3.4
performance degradation
undesired departure in the operational performance of any device, equipment or system from
its intended performance
Note 1 to entry: The term “degradation” can apply to temporary or permanent failure.
3.5
DUT
device under test
device, equipment or system being evaluated
Note 1 to entry: In this part of IEC 62215, it refers to a semiconductor device being tested.
Note 2 to entry: This note applies to the French language only.
3.6
EMC
electromagnetic compatibility
ability of an equipment or system to function satisfactorily in its electromagnetic environment
without introducing intolerable electromagnetic disturbance to anything in that environment
3.7
global pin
pin that carries a signal or power which enters or leaves the application board without any
active device in between
3.8
immunity
ability of a device, equipment or system to perform without degradation in the presence of an
electromagnetic disturbance
3.9
jitter
short-term variations of the significant instants of a digital signal from their ideal positions in
time
3.10
local pin
pin that carries a signal or power which does not leave the application board
Note 1 to entry: The signal or power remains on the application board as a signal between two components with
or without additional EMC circuitry.
3.11
response signal
signal generated by the DUT for the purpose of monitoring for detecting performance
degradation
3.12
electromagnetic ambient
totality of electromagnetic phenomena existing at a given location

– 8 – 62215-3 © IEC:2013
3.13
transient
pertaining to or designating a phenomenon or a quantity which varies between two
consecutive steady states during a time interval which is short compared with the time-scale
of interest
3.14
surge voltage
transient voltage wave propagating along a line or a circuit and characterized by rapid
increase followed by a slower decrease of the voltage
3.15
VS
power supply input
3.16
Z
L
line impedance of a trace on the test board
4 General
Electrical transients are a common part of the EMC environment of electrical and electronic
devices. These transients are generated often on power nets and are directly applied or
coupled to the terminals of integrated circuits which may affect the functionality of the device.
The knowledge about the impulse immunity level enables the optimization of the IC as well as
the definition of application requirements.
The transient waveforms are dependent on the application area of the DUT. Typical transient
waveforms are burst and surge voltages as specified in IEC 61000-4-4 and IEC 61000-4-5 for
industrial and consumer applications and in ISO 7637-2 for automotive application to get
reproducible and comparable results for different DUTs.
The impulse immunity measurement method as described in this standard uses impulses with
different amplitude and rise times, duration, energy and polarity in a conductive mode to the
IC. In this test method the test time or the number of the applied impulses has to be chosen in
a way that statistical effects are covered.
This method is similar to immunity test method of integrated circuits in the presence of
conducted RF disturbances defined in IEC 62132-4. As in IEC 62132-4, the disturbance signal
can be injected into I/O pins, supply pins and into the PCB reference via defined coupling
networks. The EMC test board for this method can be the same as the one specified in
IEC 62132-4.
The pin injection test method evaluates the performance of individual IC pins or groups of
them when subjected to a transient waveform. Both positive and negative polarity transients,
referenced to ground are applied. The basic test implementation is shown in Figure 1 .

62215-3 © IEC:2013 – 9 –
Z = 50 Ω
L
Transient
IC
generator
R
Coupling network
GND
EMC test board
IEC  1742/13
Figure 1 – Typical pin injection test implementation
5 Coupling networks
5.1 General on coupling networks
The transient disturbances are applied to the IC pin under test via defined coupling networks
implemented on the PCB and connected to a device pin with respect to the pin functionality
and the disturbance signal. Coupling networks are defined for:
• supply injection;
• input injection;
• output injection;
• multiple pin injection.
The coupling network shown in Figure 1 is identical to that used for RF immunity testing in
IEC 62132-4. The series resistance (R) can be used to control the injected current, if required.
The capacitance (C) is a DC block with a value selected to represent coupling effects in
practice and to provide sufficient signal bandwidth while not excessively loading the
connected pin (see Annex B). Default values of the series resistor and DC block capacitor are
0 Ω and 1 nF (representing capacity of 10 m parallel lines), respectively. A different capacity
value may be used if required for correct functionality. The actual value of resistor and
capacitor, including the rationale for their selection, shall be documented in the test report.
5.2 Supply injection network
5.2.1 Direct injection
For supply pins directly connected to the power net a direct injection as shown in Figure 2
shall be used. For these tests the coupling and decoupling networks of the transient
generators standardized in IEC 61000-4-4 and IEC 61000-4-5 for industrial or ISO 7637-2 for
automotive applications are used.
Mandatory blocking capacitors (C ), filter or protection components at the supply pin have to
BL
be used as recommended by the manufacturer.

– 10 – 62215-3 © IEC:2013
Supply
Z = 50 Ω
L
IC
Transient
generator
VS
C
BL
GND
EMC test board
IEC  1743/13
Figure 2 – Supply pin direct injection test implementation
5.2.2 Capacitive coupling
For supply pins which are not directly connected to the power net, such as global distributed
sub-supply nets isolated by power converters, the test circuitry shall be implemented as
shown in Figure 3. The default values of the coupling network are 0 Ω for the resistor and
1 nF for the coupling capacitor. The external DC power supply should be decoupled from the
supply pin(s) of the DUT with impedance (Z) greater than 400 Ω (default) over the frequency
range of the test impulse spectrum. Other values for coupling and decoupling networks are
possible but must be stated in the test report (see also Clause 11).
Mandatory blocking capacitors, filter- or protection components at the supply pin have to be
used as recommended by the manufacturer.

Supply
Z > 400 Ω
Z = 50 Ω
L
IC
Transient
generator VS
R
C
Coupling network
C
BL
GND
EMC test board
IEC  1744/13
Figure 3 – Supply pin capacitive injection test implementation
5.3 Input injection
For general purpose I/O pins configured as inputs or input-only pins and globally connected,
the test circuitry shall be implemented as shown in Figure 4. The default values of the

62215-3 © IEC:2013 – 11 –
coupling network are 0 Ω for the resistor and 1 nF for the coupling capacitor. External signal
sources (e.g. signal generator) which are connected to the input signal connector should be
decoupled from the input pin(s) of the DUT with impedance (Z) greater than 400 Ω (default)
over the frequency range of the test impulse spectrum. Other values for coupling and
decoupling networks are possible but shall be stated in the test report. The input shall be
configured as recommended by the manufacturer, only mandatory components have to be
applied (e.g. with an appropriate external pull up resistor (R ), a pull down resistor (R ) or a
U D
series resistor (R )). The DUT function shall not be affected by the coupling network.
S
Input signal connector
Z > 400 Ω
VS
Z = 50 Ω
L
IC
R
U
Transient
generator Input
R
S
R
C
RD
Coupling network
GND
EMC test board
IEC  1745/13
Figure 4 – Input pin injection test implementation
5.4 Output injection
For general purpose I/O pins configured as outputs or output-only pins and globally connected,
the test circuitry shall be implemented as shown in Figure 5. The default values of the
coupling network are 0 Ω for the resistor and 1 nF for the coupling capacitor. External signal
processing units or loads which are connected to the output signal connector should be
decoupled from the output pin(s) of the DUT with impedance (Z) greater than 400 Ω (default)
over the frequency range of the test impulse spectrum. Other values can be assigned to the
coupling and decoupling networks but they shall be stated in the test report. The output shall
be configured and loaded (e.g. with an appropriate external capacitive load (C )) as specified
L
by the manufacturer. Only mandatory external components according to the specification
should be connected during test.
For output pins, the DC block capacitance shall not exceed the rated capacitive load of this
output to prevent an unacceptable deviation of the output signal.

– 12 – 62215-3 © IEC:2013
Output signal connector
Z > 400 Ω
Z = 50 Ω
L
IC
Transient
generator
Output
C
R
Coupling network
C
L GND
EMC test board
IEC  1746/13
Figure 5 – Output pin injection test implementation
5.5 Simultaneous multiple pin injection
For parallel coupling to multiple pins or pin groups a coupling network consisting of one
injection point and a capacitive impulse signal splitter can be used as shown in Figure 6. The
default values of those coupling networks are the same as for respective single pins.

Z = 50 Ω
L
IC
Pin 1
Transient
C R
generator
Pin 2
GND
R
C
Coupling network
EMC test board
IEC  1747/13
Figure 6 – Multiple pin injection test implementation
6 IC configuration and evaluation
6.1 IC configuration and operating modes
For the impulse immunity test the IC shall be set in normal operating conditions according to
the typical data sheet values. This means the supply voltage shall be set to the nominal value
and not to the minimum and maximum values given in the data sheet. Depending on the IC
functionality relevant IC operation modes should be selected. Attempts should be made to
fully exercise all functions and modes of operation that significantly influence the immunity of
the DUT. If possible, the IC stimulation should be done as expected in a typical application or
by auxiliary equipment not affecting the immunity performance of the DUT. When a watchdog
function is available, it may be disabled during the test to collect additional information.

62215-3 © IEC:2013 – 13 –
Mandatory components listed in the data sheet, which are necessary for the IC functionality or
stimulation, shall be applied. The position of mandatory components and test board layout
shall be designed not to affect adversely the test results of the IC.
NOTE To fulfil a certain test level, additional components can be necessary. Such components are regarded as
mandatory for such applications.
6.2 IC monitoring
The DUT should be monitored such that immunity performance can be determined as
completely as possible. The monitoring shall be implemented such that the immunity
performance of the DUT is not affected.
In mixed signal ICs various response signals can be generated depending on implemented
functions or installed software programs. The response signal can be monitored for
indications of susceptibility that include, but are not limited to, the following parametric and
functional characteristics:
• cycle-to-cycle jitter, frequency, or duty cycle of a periodic waveform;
• signal transition time (rise or fall) of the output waveform;
• signal source voltage, current or resistance;
• spikes, glitches or other transient phenomena on the output waveform;
• DUT reset;
• DUT hang;
• DUT latch-up;
• digital data loss or deviation;
• memory content corruption.
Monitoring can be done by I/O signal detection, oscilloscopes, voltmeter, logic analyser, data
analyser etc. considering certain failure criteria.
For monitored response signals, failure criteria have to be defined individually for the
dedicated IC impulse immunity test. A failure criterion is defined by a nominal signal value
and an allowed tolerance.
6.3 IC performance classes
The IC immunity is categorised in IC performance classes as follows:
Class A : all monitored functions of the IC perform within the defined tolerances during
IC
and after exposure to disturbance;
Class B : short time degradation of one or more monitored signals during exposure to
IC
disturbance is not evaluable for IC only. Therefore this classification may not
be applicable for ICs (see Note);
Class C : at least one of the monitored functions of the IC is out of the defined tolerances
IC
during the disturbance but returns automatically to the defined tolerances after
the exposure to disturbance;
Class D : at least one monitored function of the IC does not perform within the defined
IC
tolerances during exposure and does not return to normal operation by itself.
The IC returns to normal operation by manual intervention;
Class D1 : the IC returns to normal operation by manual intervention:
IC
(e.g. reset);
Class D2 : the IC returns to normal operation by power cycling the device;
IC
Class E : at least one monitored function of the IC does not perform within the defined
IC
tolerances after exposure and cannot be returned to proper operation.

– 14 – 62215-3 © IEC:2013
NOTE Short time degradation of one or more monitored signals can be tolerable in the application by its error
handling. This error handling is unknown in most cases for IC test.
7 Test conditions
7.1 General
Unless otherwise specified in the manufacturer’s specifications, the following ambient
conditions shall apply.
7.2 Ambient electromagnetic environment
The electromagnetic ambient shall not affect responses of the DUT.
7.3 Ambient temperature
The ambient temperature during the test shall be (23 ± 5) °C.
7.4 IC supply voltage
The supply voltage(s) shall be set to the nominal supply voltage(s) as specified by the
IC manufacturer with a tolerance of ± 5 %.
8 Test equipment
8.1 General requirements for test equipment
All equipment used in this test shall be immune to the applied transient such that the test
results will not be influenced. The test equipment shall meet the following test equipment
requirements.
8.2 Cables
Coaxial cables are recommended to carry the disturbance signal to protect the test
environment and prevent cross coupling of disturbance signals to stimulation and monitoring
signals. For proper test signal delivery under high voltage test conditions, a cable rated for
the maximum test voltage to be applied shall be specified and used.
8.3 Shielding
To ensure proper ambient environments on DUT functionality or to suppress coupling to the
environment, testing in a shielded room may be required.
8.4 Transient generator
A transient generator according to IEC 61000-4-4, IEC 61000-4-5 or ISO 7637-2 shall be used.
8.5 Power supply
The DUT shall be powered by a source that is not affected by the injected disturbance signal.
If a battery is used, it shall meet the IC requirements and the supply voltage level shall be
checked to maintain a consistent operating environment.
8.6 Monitoring and stimulation equipment
The monitoring and stimulation equipment should not be affected by the injected disturbance
signal. Care should be taken that the monitoring and stimulation equipment do not adversely
affect the DUT or the test result.

62215-3 © IEC:2013 – 15 –
8.7 Control unit
A control unit is recommended to automate control of the transient generator, stimulate the IC
and acquire data from the performance monitoring.
9 Test set up
9.1 General
A block diagram of the test set-up for the non-synchronous transient immunity test is shown in
Figure 7. The transient generator injects the disturbance into the IC pin under test via the
coupling network on the EMC test board. The output of the transient generator is directly
connected to the coaxial connector of the coupling network. The transient generator ground
shall be connected to the reference ground provided by the EMC test board. A response
signal driven from the IC is monitored for any indication of susceptibility while the IC is
powered and a required functional stimulation is applied. The system can be controlled by a
control unit.
Power
supply
EMC test board
Transient
Stimulation
generator
Monitoring
Control bus
Control unit
IEC  1748/13
Figure 7 – Test set-up diagram
9.2 EMC test board
An EMC test board carrying the DUT, mandatory components and the necessary coupling and
decoupling networks is required to perform this test method. The test board is also described
in IEC 62132-4.
The use of a printed circuit board with a common ground plane for impulse testing of ICs is
recommended. The DUT should be placed on the test board without sockets. If a socket is
used care should be taken that the inductance of the socket does not significantly affect the
test results especially for fast transients.
It is the main purpose of this standard to test the impulse immunity of the DUT only. Therefore,
external protection components of the DUT shall be removed except when they are mandatory

– 16 – 62215-3 © IEC:2013
for proper function of the IC (e.g. blocking capacitors, timer capacitors, etc.). Such mandatory
components shall be placed directly at the IC and grounded on the same ground plane.
Return paths from mandatory blocking components to the DUT or the shield of a transmission
line should not have slits.
Pulse 50 Ω traces
injection port
As short as
possible
IC
Coupling
Optional
capacitor resistor
SMA or SMB
connector
Decoupling
as close as possible
to IC pin
Layer:
top:
bottom:
Signal from/ to
peripherals
IEC  1749/13
Figure 8 – Example of the routing from
the injection port to a pin of the DUT
The trace from impulse injection port connector to the coupling network should be a 50 Ω
transmission line (see example in Figure 8). The end of the transmission line to the pin of the
DUT should be as short as possible. A trace length equal to 1/20 of the shortest wavelength
applied is a reasonable target. For transients defined in the time domain, the trace length can
be calculated by:
t ⋅ v
r p
l ≤ (1)
t
c
v = (2)
p
ε
r
where
l is trace length (cm)
t
t is rise time (ns)
r
c is speed of light (m/s)
v is propagation speed (cm/ns)
p
(e.g. air: v = 30 cm/ns, PCB material FR4: v = 14,8 cm/ns)
p p
ε is relative permittivity
r
Shorter trace lengths are advantageous.
The ground plane shall not have slits in the return paths of traces carrying coupled signals. If
not possible, slits in the return paths of coupled signal carrying traces shall not exceed 1/20 of
the shortest wave length.
To have a reliable ground reference, the impedance between the DUT ground pin(s) and the
shield of any transmission line providing the coupled signal shall be as low as possible.

62215-3 © IEC:2013 – 17 –
Therefore using a ground plane on PCB to minimise the impedance of the ground connections
is strongly recommended. The impulse decoupling network should be placed as close as
possible to the pin where the impulse is injected.
If it is not possible to follow these rules, the deviations shall be described in the test report.
The impulse immunity test board can be based on the RF immunity test board of IEC 62132-4
with some modifications. Additional test board recommendations are provided in Annex A.
10 Test procedure
10.1 Test plan
The test plan shall include all conditions regarding the DUT and transients to be applied:
• selection of relevant impulses, test levels and polarity according to the target application
and related basic standards;
• generator settings (repetition rate, number of impulses, output impedance);
• operation mode(s);
• monitored function and failure criteria;
• pin to be coupled.
NOTE In case of a device having a large number of pins, only a representative selection of pins depending on
their type and location can be tested. The rationale for their selection are documented in the test report.
10.2 Test preparation
Energise the DUT and complete an operational check to verify proper function of the device
(i.e. run DUT test code) in the ambient test condition. During the operational check, the
transient generator and any stimulation and monitoring equipment shall be powered and
connected to the PCB; however, the output of the transient generator shall be disabled. The
performance of the DUT shall not be degraded by ambient conditions.
10.3 Characterization of coupled impulses
For consistent and repeatable testing it is necessary to characterize the generator output
voltage signal under open load conditions as specified in IEC 61000-4-4, IEC 61000-4-5 or
ISO 7637-2 respectively. Additionally, it is important that the coupled impulses are
characterized at the DUT landing pad under open load condition. This characterization
includes the impulse generator, connection lines, coupling network, mandatory components
and used decoupling networks. The transfer characteristic can be estimated by the signal
difference between the signal at the impulse generator output under open load conditions and
the measured signal at the DUT landing pad. Both measurements should be done using an
oscilloscope as defined in the respective impulse definition standard.
10.4 Impulse immunity measurement
With the EMC test board energized and the DUT being operated in the intended test mode,
measure the immunity to the injected transient disturbance signal.
The applied test level shall be increased according to the test plan in steps until a malfunction
is observed or the maximum test level is reached. The test shall be performed with voltage
step sizes not greater than those specified in the test plan. The voltage levels listed in the test
plan are the characterized transient generator output impulses under open load conditions.
At each test level, the transient signal shall be applied for a minimum of 10 s (or at least the
time necessary for the DUT to respond and the monitoring system to detect any performance
degradation).
– 18 – 62215-3 © IEC:2013
For definition of the minimum dwell time statistical coverage of process timing and disturbing
impulse events, thermal stress and life time test have to be considered. Typical values have
to be established for standard applications. The default value is 10 min.
Test schedule in detail:
1) Connect all the equipment as shown in Figure 7.
2) Verify the proper operation of the DUT.
3) Set the transient generator for the desired voltage level.
4) Set the transient generator for the desired polarity.
5) Inject the transient for the required dwell time. Monitor the DUT performance during
transient injection for performance degradation.
6) If testing at additional voltage levels is desired, go to step 3.
10.5 Interpretation and comparison of results
Results may be directly compared as long as measurements have been carried out under the
same conditions. If comparison is intended, the devices should be running the same code and
the test environment shall be as consistent as possible. The same kind of test boards shall be
used.
For determination of IC performance classes it has to be considered if the deviation of a
monitored signal is caused by an IC function or by a superposition of the disturban
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