IEC 60747-16-10:2004

Semiconductor devices - Part 16-10: Technology Approval Schedule (TAS) for monolithic microwave integrated circuits

IEC 60747-16-10:2004 specifies the terms, definitions, symbols, quality system, test, assessment and verification methods and other requirements relevant to the design, manufacture and supply of monolithic microwave integrated circuits in compliance with the general requirements of the IECQ-CECC System for electronic components of assessed quality.

Dispositifs à semiconducteurs - Partie 16-10: Format-cadre pour agrément de technologie (TAS) pour circuits intégrés monolithiques hyperfréquences

La CEI 60747-16-10:2004 spécifie les termes, les définitions, les symboles, le système de qualité, les méthodes d'essai, d'évaluation et de vérification et d'autres exigences relatives à la conception, la fabrication et la livraison de circuits intégrés monolithiques hyperfréquences conformément aux exigences générales du système IECQ-CECC pour les composants électroniques sous assurance de la qualité.

General Information

• Status: Published
• Publication Date: 14-Jul-2004
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47E - Discrete semiconductor devices
• Drafting Committee: WG 2 - TC 47/SC 47E/WG 2
• Current Stage: PPUB - Publication issued
• Start Date: 15-Jul-2004
• Completion Date: 30-Nov-2004

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD 60747-16-10
QC 210021
First edition
2004-07
Semiconductor devices –
Part 16-10:
Technology Approval Schedule (TAS)
for monolithic microwave integrated circuits
Reference number
Publication numbering
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60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
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edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the
base publication incorporating amendment 1 and the base publication incorporating
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INTERNATIONAL IEC
STANDARD 60747-16-10
QC 210021
First edition
2004-07
Semiconductor devices –
Part 16-10:
Technology Approval Schedule (TAS)
for monolithic microwave integrated circuits
© IEC 2004 ⎯ Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: [phone] Telefax: [phone] E-mail: [e-mail] Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale XA
International Electrotechnical Commission
ɆɟɠɞɭɧɚɪɨɞɧɚɹɗɥɟɤɬɪɨɬɟɯɧɢɱɟɫɤɚɹɄɨɦɢɫɫɢɹ
For price, see current catalogue

– 2 – 60747-16-10 © IEC:2004(E)
CONTENTS
FOREWORD.4
Foreword to this particular Technology Approval Schedule (TAS) .7
Organizations responsible for preparing the present TAS.7
Preface.7
INTRODUCTION.8
1 General .9
1.1 Scope.9
1.2 Normative documents.9
1.3 Units, symbols and terminology .10
1.4 Standard and preferred values .10
1.5 Definitions .10
2 Definition of the component technology .12
2.1 Scope.12
2.2 Description of activities and flow charts.13
2.3 Technical abstract .13
2.4 Requirements for control of subcontractors .16
3 Component design of MMICs.18
3.1 Scope.18
3.2 Description of activities and flow charts.18
3.3 Interfaces .19
3.4 Validations and control of the processes .21
4 Mask manufacture .23
4.1 Scope.23
4.2 Description of activities and flow charts.23
4.3 Validation and control of the processes .23
4.4 Subcontractors, vendors and internal suppliers .23
5 Wafer fabrication of MMICs .23
5.1 Scope.23
5.2 Description of activities and flow charts.24
5.3 Equipment.26
5.4 Materials .26
5.5 Re-work .26
5.6 Validation methods and control of the processes .27
5.7 Interrelationship .28
6 Wafer probing of MMICs .30
6.1 Scope.30
6.2 Description of activities and flow charts.30
6.3 Equipment.30
6.4 Test procedures .30
6.5 Interrelationship .30
7 Back-side process for bare chip delivery .32
7.1 Scope.32
7.2 Description of activity and flow charts.32
7.3 Equipment.33
7.4 Materials .33

60747-16-10 © IEC:2004(E) – 3 –
7.5 Validation methods and control of the processes .33
7.6 Interrelationship .33
7.7 Validity of release.34
8 Assembly of MMICs.36
8.1 Scope.36
8.2 Description of activities and flow charts.36
8.3 Materials, inspection and handling.37
8.4 Equipment.37
8.5 Re-work .37
8.6 Validation and control of the processes .37
8.7 Interrelationships.38
9 Testing of MMICs .40
9.1 Scope.40
9.2 Description of activities and flow charts.40
9.3 Equipment.40
9.4 Test procedures .41
9.5 Interfaces .42
9.6 Validation and control of the processes .43
9.7 Process boundary verification.46
9.8 Product verification.50
10 Process characterization .50
10.1 Identification of process characteristics .50
10.2 Description of activities .51
10.3 Characterization procedures.52
11 Packaging and shipping.53
11.1 Description of activities and flow charts.53
11.2 Interfaces .54
11.3 Validity of release.54
12 Withdrawal of Technology Approval.56
Figure 1 – Example flow chart of design/manufacture/test.16
Figure 2 – Example flow chart of a design.21
Figure 3 – Technology flow chart of the process .29
Figure 4 – Example flow chart for a wafer probing. .30
Figure 5 – Example flow chart for a back-side process for bare chip delivery .34
Figure 6 – Example flow chart for an assembly .38
Figure 7 – Example flow char for a testing .44
Figure 8 – Typical flow chart for packaging and shipping .54

– 4 – 60747-16-10 © IEC:2004(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
Part 16-10: Technology Approval Schedule (TAS)
for monolithic microwave integrated circuits
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60747-16-10 has been prepared by subcommittee 47E: Discrete
semiconductor devices, of IEC technical committee 47: Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47E/257/FDIS 47E/262/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The QC number that appears on the front cover of this publication is the specification number
in the IEC Quality Assessment System for Electronic Components (IECQ-CECC).

60747-16-10 © IEC:2004(E) – 5 –
This publication has been partially drafted in accordance with the ISO/IEC Directives, Part 2
(2001). It also follows the requirements given in IEC QC 210000:1995, Technology Approval
Schedules – Requirements under the IEC Quality Assessment System for Electronic
Components (IECQ-CECC).
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
– 6 – 60747-16-10 © IEC:2004(E)
International Electrotechnical Commission QC 210021
Quality Assessment System for Electronic Components (IECQ-CECC)
Responsible NAI: Name Specification available as shown in
Address QC 001004 Specifications List or from any
Tel:  National Authorized Institution (NAI)
Fax:
TECHNOLOGY APPROVAL SCHEDULE
(Monolithic microwave integrated circuits)
Issue
QC 210021
2004-07
60747-16-10 © IEC:2004(E) – 7 –
Foreword to this particular Technology Approval Schedule (TAS)
The IEC Quality Assessment System for Electronic Components (lECQ) is composed of those
member countries of the International Electrotechnical Commission (lEC) that wish to take
part in a harmonized system for electronic components of assessed quality.
The object of the System is to facilitate international trade by the harmonization of
specifications and quality assessment procedures for electronic components and by the
granting of an internationally recognized mark or certificate of conformity. The components
produced under the System are acceptable in all member countries without further testing.
This TAS has been prepared for use by those countries taking part in the System who wish to
issue national harmonized specifications for Technology Approval of manufacturers of
monolithic microwave integrated circuits. It should be read in conjunction with the current
regulations of the IECQ-CECC System.
At the date of printing of this schedule the member countries of IECQ-CECC are China,
Denmark, France, Germany, India, Italy, Japan, Republic of Korea, Netherlands, Norway,
Russian Federation, Switzerland, Thailand, Ukraine, United Kingdom, USA and Yugoslavia.
Copies of this schedule can be obtained from their National Authorized Institutions, National
Standards Organizations or, in case of difficulty, from the Central Office of IEC in Geneva,
Switzerland (fax [phone]) as described in the Specifications List QC 001004 on
www.iecq-cecc.org.
Organizations responsible for preparing the present TAS
IEC subcommittee 47E: Discrete semiconductor devices
Preface
This schedule was prepared by SC47E/WG2.
It is based, wherever possible, on the publications of the International Electrotechnical
Commission (lEC) and the International Organization for Standardization (ISO) and in
particular on:
IEC 60747-16-1: Semiconductor devices – Part 16-1: Microwave integrated circuits –
Amplifiers,
IEC 60747-16-2: Semiconductor devices – Part 16-2: Microwave integrated circuits –
Frequency prescalers,
IEC 60747-16-3: Semiconductor devices – Part 16-3: Microwave integrated circuits –
Frequency converters,
IEC 60747-16-4: Semiconductor devices – Part 16-4: Microwave integrated circuits –
Switches.
– 8 – 60747-16-10 © IEC:2004(E)
INTRODUCTION
The requirements for Technology Approval for manufacturers of electronic and electro-
mechanical components are given in QC 001002-3, Clause 6. The procedures for approval
defined in that clause require the manufacturer to have available an appropriate Technology
Approval Schedule (TAS).
This schedule defines how the principles and requirements of QC 001002-3, Clause 6 are
applied to monolithic microwave integrated circuits.

60747-16-10 © IEC:2004(E) – 9 –
SEMICONDUCTOR DEVICES –
Part 16-10: Technology Approval Schedule (TAS)
for monolithic microwave integrated circuits
1 General
1.1 Scope
This TAS specifies the terms, definitions, symbols, quality system, test, assessment and
verification methods and other requirements relevant to the design, manufacture and supply
of monolithic microwave integrated circuits in compliance with the general requirements of the
IECQ-CECC System for electronic components of assessed quality.
1.2 Normative documents
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60027 (all parts): Letter symbols to be used in electrical technology
IEC 60050: International Electrotechnical Vocabulary
IEC 60068 (all parts): Environmental testing
IEC 60191-2: Mechanical standardisation of semiconductor devices – Part 2: Dimensions
IEC 60617-DB (all parts): Graphical symbols for diagrams
IEC 60747-1: Semiconductor devices – Discrete devices and integrated circuits – Part 1:
General
IEC 60747-16-1: Semiconductor devices – Part 16-1: Microwave integrated circuits –
Amplifiers
IEC 60747-16-2: Semiconductor devices – Part 16-2: Microwave integrated circuits –
Frequency prescalers
IEC 60747-16-3: Semiconductor devices – Part 16-3: Microwave integrated circuits –
Frequency converters
IEC 60747-16-4: Semiconductor devices – Part 16-4: Microwave integrated circuits –
Switches
IEC 60748-1: Semiconductor devices – Integrated circuits – Part 1: General
ISO 1000: SI units and recommendations for the use of their multiples and certain other units
———————
“DB” refers to the IEC on-line database.
2 To be published.
– 10 – 60747-16-10 © IEC:2004(E)
1.3 Units, symbols and terminology
Units, graphical symbols, letter symbols and terminology shall, whenever possible, be taken
from the following documents:
IEC 60027: Letter symbols to be used in electrical technology
IEC 60050: International electrotechnical vocabulary
IEC 60617-DB: Graphical symbols for diagrams
ISO 1000: SI units and recommendations for the use of their multiples and certain other units
Any other units, symbols and terminology specific to the scope of this TAS shall be taken from
the relevant IEC or ISO documents listed under Normative documents.
1.4 Standard and preferred values
Technology Approval allows the customization of the component or process to suit each
customer. The conventional concept of preferred values may thus have limited application.
However, when internationally recognized preferred values apply these should be used, e.g.
voltage, temperature and dimensions. Reference shall be made to the appropriate IEC or ISO
publications, i.e.:
– voltage IEC 60747-1
– temperature IEC 60747-1
– dimensions IEC 60191-2.
1.5 Definitions
For the purposes of this document, the following definitions apply.
1.5.1 General terms for monolithic microwave integrated circuits
1.5.1.1
microelectronics
(IEC 60748-1, definition 4.1.5)
1.5.1.2
microcircuit
(IEC 60748-1, definition 4.2.2)
1.5.1.3
integrated circuit
(IEC 60748-1, definition 4.2.3)
1.5.1.4
integrated microcircuit
microcircuit in which a number of circuit elements are inseparably associated and electrically
interconnected such that for the purpose of specification and testing and commerce and
maintenance, it is considered indivisible
NOTE 1 For this definition, a circuit element does not have an envelope or external connection and is not
specified or sold as a separate item.
NOTE 2 Where no misunderstanding is possible, the term "integrated microcircuit" may be abbreviated to
"integrated circuit".
NOTE 3 Further qualifying terms may be used to describe the technique used in the manufacture of a specific
integrated microcircuit. Examples to the use of qualifying terms: semiconductor monolithic integrated circuit;
semiconductor multi-chip integrated circuit; thin film integrated circuit; thick film integrated circuit; hybrid integrated
circuit.
60747-16-10 © IEC:2004(E) – 11 –
1.5.1.5
micro-assembly
microcircuit consisting of various components and/or integrated microcircuits which are
constructed separately and which can be tested before being assembled and packaged
NOTE 1 For this definition, a component has external connections and possibly an envelope as well and it also
can be specified and sold as a separate item.
NOTE 2 Further qualifying terms may be used to describe the form of the components and/or the assembly
techniques used in the construction of a specific micro-assembly. Examples of use of qualifying terms:
semiconductor multi-chip micro-assembly; discrete component micro-assembly.
1.5.2 List of abbreviations
– ASIC: Application Specific Integrated Circuit
– BDS: Blank Detail Specification
– BICMOS: Bipolar and Complementary Metal Oxide Silicon
– CAD: Computer Aided Design
– CAE: Computer Aided Engineering
– CECC: CENELEC Electronic Components Committee
– CMB: Contract Management Branch
– Cpk: Index of critical process capability
– Die Shear: Test on die attach
– DIL: Dual In Line Package
– DRC: Design Rules Check
– Dye Penetrant (ZYGLO): Seal test
– EDP: Electronic Data Processing
– EFR: Electrical Failure Rate
– ERC: Electrical Rules Check
– ESD: Electro Static Discharge
– GaAs: Gallium Arsenide
– HBT: Hetero-junction Bipolar Transistor
– HEMT: High Electron Mobility Transistor
– ISO 9000: ISO International Quality Rules
– JFET: Junction Field Effect Transistor
– LRM: Line Reflect Match
– LSSD: Level Sensitive Scan Design
– LVS: Layout Versus Schematics
– MESFET: Metal Semiconductor Field Effect Transistor
– MMIC: Monolithic Microwave Integrated Circuits
– MODFET: Modulation Doped Field Effect Transistor
– MTF: Mean Time to Failure
– MTBF: Mean Time Between Failures
– MTTR: Mean Time To Repair
– NMOS: Metal Oxide Silicon N channel

– 12 – 60747-16-10 © IEC:2004(E)
– OS: Operating System
– PAS: Publicly Available Specification
– PCM: Process Control Monitor
– PDA: Percentage Defectives Allowed
– PM: Parametric Monitor
– PMOS: Metal Oxide Silicon P channel
– POST CAP: Inspection after Encapsulation
– PRE CAP: Inspection before Encapsulation
– QA: Quality Assurance
– QCI: Quality Conformance Inspection
– QML: Qualified Manufacturer List
– RIE: Reactive Ion Etching
– SEC: Standard Evaluation Circuit
– SEM: Scanning Electron Microscope
– SI: Supervising Inspectorate
– SOI: Silicon on Insulator
– SOLT: Short Open Load Thru
– SOS: Silicon on Sapphire
– SPC: Statistical Process Control
– Si: Silicon
– TADD: Technology Approval Declaration Document
– TCI: Technology Conformance Inspection
– TCV: Technology Characterization Vehicle
– TDDB: Time Dependent Dielectric Breakdown
– TQM: Total Quality Management
– TRB: Technology Review Board
– TRL: Thru Reflect Line
– VT: Threshold Voltage for FET
– ZYGLO: see Dye Penetrant.
NOTE PCM and PM have the same meaning; however, PCM is the term used in the following subclauses.
1.5.3 Definitions relevant to the scope of the TAS
See QC 001002-3, Clause 6 for definitions specific to Technology Approval.
2 Definition of the component technology
2.1 Scope
The Technology Approval for the declared range or family of components shall include their
design and manufacturing processes and their interfaces. The overall management of these
interfaces by the Control Site shall be included. These processes and interfaces shall be
declared within the Technology Approval Declaration Document (TADD).

60747-16-10 © IEC:2004(E) – 13 –
More detailed requirements for the listed processes and interfaces to be included within the
Technology Approval are given in the relevant clauses of this TAS. The processes are listed
below with the identification of the MAIN TECHNICAL PROCESS:
• Process characterization
• Integrated circuit design – This is a MAIN TECHNICAL PROCESS
• Mask manufacture
• Wafer fabrication – This is a MAIN TECHNICAL PROCESS
• Back-side process
• Wafer probe
• Assembly – This is a MAIN TECHNICAL PROCESS
• Test and release – This is a MAIN TECHNICAL PROCESS
• Packaging and shipping
Shipping includes the temporary storage of finished products before shipment to the
customer.
2.2 Description of activities and flow charts
2.2.1 Description of activities
All the activities (processes) shall be identified with the relevant flow charts included. This
information may include different processes for different types of components but covered by
the same technology. Where applicable, these should address all the processes listed in 2.1.
The design and manufacturing cycle of integrated circuits may involve one or more qualified
company or facility handing different tasks within the “life cycle” of an MMIC.
Design, development or specification of an MMIC is performed to the specific requirements of
a customer, which may be an external customer (such as for an application-specific MMIC), or
an internal department.
The prime contractor is that organization which undertakes the responsibility for the
management of all tasks prior to the supply of an MMIC to the specified requirements.
2.2.2 Flow charts
The flow chart in Figure 1 is an example showing such operations, where the specific stages
are expected to be defined, referencing the relevant internal documentation.
2.3 Technical abstract
2.3.1 TADD abstract (not for publication)
The Technology Approval technical abstract shall be declared by the technology approval
declaration document (TADD).
For each technology declared the following shall be identified:
• Description of design tools used e.g. CAD systems, software;
• Description of wafer fabrication processes including feature size, technology, types and
number of interconnects
– e.g. 0,5 µm gate, GaAs MESFET, double layer metal;

– 14 – 60747-16-10 © IEC:2004(E)
• Description/list of products and/or family of products
– e.g. low noise amplifiers; power amplifiers; switches;
• Description of packaging types/materials and range of pincounts
– e.g. chip form: ceramic, DIL 8, 16 pin;
• Description of test equipment, i.e. type of test equipment and scope.
An example of a Technology Approval technical abstract is given in 2.3.3.
2.3.2 QC 001005 abstract
The information to be published within QC 001005:2000, Register of Firms, Products and
Services approved under the IECQ-CECC System, including ISO 9000, may be based on the
information given to satisfy the Technology Approval technical abstract of 2.3.1. Information
marked with an asterisk (“*”) may be omitted in the published “Abstract of Technology
Approval” if requested by Control Site.

60747-16-10 © IEC:2004(E) – 15 –
2.3.3 Example of a Technology Approval technical abstract
TECHNOLOGY DESCRIPTION: MONOLITHIC MICROWAVE INTEGRATED CICUIT
Manufacture [Control Site]: Name and location
IEC Reference: QC 210021 – TAS for Monolithic Microwave Integrated Circuits
Certificate Number: Reference of the local SI
TADD Generic: Control Site’s Document Reference
(Cross references to other TADD shall exist in the Generic Specification
where applicable).
LIBRARY/DESIGN
Manufacturer’s name of the library:
Information on the library (where applicable):
Purpose: [ ] Microwave Design [ ] Digital Design [ ] Others
Types: [ ] Standard Cells [ ] Element Cells
Contents: Types of cells
WAFER FABRICATION:
Wafer Fabrication Process Name: (e.g. “AMES0.5” etc.)
Wafer Fabrication Process Type: (e.g. FET/Bipolar etc.)
Function: (e.g. Standard Cell/Custom etc.)
Production Families: (e.g. Low Noise/High Power/Control etc.)
Details:
Wafer Size: (e.g. 100 mm)
Gate Length: (e.g. 0,5 µm)
Maximum Interconnect Levels:* (Triple/Double/Single Level/Metal etc.)*
Transmission line structure: (e.g. microstrip/coplanar waveguide etc.)
Metal Compositions:* (Al/Si/Al/Cu etc.)*
Gate Material:* (Metal/Polysilicon etc.)*
Passivation Material:* (1,2 µm Compressive Nitride etc.)*
Substrate Material:* (e.g. GaAs)*
Number of masks:* (e.g. 8)*
ASSEMBLY:
Package types: (e.g. Thin Plastic Quad Flat Pack, 7,6 mm Small Outline (SO) etc.)
Details:
Maximum Die Size: (e.g. TPQFP – 9 x 9 mm: SO300 – 2,3 mm x 2,3 mm)
Package materials: (e.g. Ceramic/Epoxy/Plastic etc.)
Header/Leadframe:* (e.g. Copper/Alloy 42 etc.)*
Pin/Lead Finish: (e.g. Gold/Solder Dipped etc.)
Die Attachment:* (e.g. Silicon-Gold Eutectic etc.)*
Bond Wire Attachment:* (e.g. Aluminium, Ultrasonic etc.)*
Package assembly
ELECTRICAL CHARACTERISTICS OF PRODUCTS:
Supply Voltage Range:
Maximum Input Power:
Total Power Dissipation:
Maximum Operating Frequency:
Operating Temperature Range:
Storage Temperature Range:
ENVIRONMENTAL/RELIABILITY LIMITS:
Endurance Test Performance: (e.g. > x year at 55 °C or > 1 000 h at 125 °C)
Accelerated Damp Heat Severity: (e.g. > x year at 55 °C/60 % RH or 1 000 h at 85 °C/85 % RH)
Temperature Cycling Extremes: (e.g. –65 °C / +150 °C)
etc.
AND
Expected Failure Rate (under specified environments)
Quality Factor (π ).
Q
(The limits of approval shall be made available to the customer, and any tests should correlate to IEC
test methods and should be suitable for the intended application.)

– 16 – 60747-16-10 © IEC:2004(E)
2.4 Requirements for control of subcontractors
Where a technical process as defined in 2.1 is subcontracted, the procedures and criteria
employed to demonstrate control shall be specified. This may be achieved either by the
demonstration of conformance to the requirements of the appropriate PAS (Publicly Available
Specification) in the IECQ-CECC 200000 series, or by demonstrating that the processes have
been satisfactorily performed in accordance with criteria defined or referenced from the TADD.
Such criteria shall be capable of demonstrating compliance with the declaration of reliability
and environmental performance.
The following items shall be specified:
• Reason for subcontracting
• Name and address
• IECQ-CECC Process and Approval or Technology Approval certificate reference (where
appropriate)
• Name of CMB (Contract Management Branch) contract within the subcontractor
• Documentation
• Interrelationship documentation.
NOTE Design, mask manufacture, wafer fabrication, wafer probe, assembly, testing, packaging and shipping may
be subcontracted provided that the control site has the capability for at least one of the MAIN TECHNICAL
PROCESSES as defined in 6.2.1.3 of QC 001002-3.

60747-16-10 © IEC:2004(E) – 17 –
CUSTOMER
Custom IC
INTEGRATED
CIRCUIT DESIGN
CENTRE
MASK
MANUFACTURE
WAFER
FABRICATION
PROBE
TEST
ASSEMBLY
TEST
PACKAGING
AND
SHIPPING
IEC  876/04
NOTE This is an example of a packaged device.
Figure 1 – Example flow chart of design/manufacture/test

– 18 – 60747-16-10 © IEC:2004(E)
3 Component design of MMICs
3.1 Scope
Design information relevant to the technology for which approval is sought shall be included in
the TADD.
This shall include design of the semiconductor process incorporating modification and
publication of the process parameters and related process design rules in the form of written
and computer files suitable for use in CAD tools at either internal customers or independent
design centres.
Process characterization and circuit design are, in general, separate though inter-related
tasks, and so their interfaces with the process design task shall be specified in detail, including
management responsibilities, transfer specifications, requirements and deliverables.
The IC design centre is responsible for the design of integrated circuits in accordance with
customer requests as defined by product or other specifications, generally by translation from
received data into IC specifications, then design and simulation phases followed by
production of data, specifications, and computer files (or equivalent) required for manu-
facturing. This shall generally employ data from the process design task.
Activities may include mask making and writing product test programmes or test data suitable
for development into test programmes by a test centre or task.
3.2 Description of activities and flow charts
3.2.1 Description of activities
The activities of design for integrated circuits shall be declared, including flow charts showing
all activities, critical steps, check points and quality indicators, referencing the relevant
internal documentation. These shall include any or all of items a) to e) below, as appropriate:
a) Feasibility
The availability of equipment and of the design/manufacturing capacity to cover the
required production lot quantities shall be verified.
b) Process design
i) Physical characteristics (required for circuit design)
ii) Electrical characteristics
iii) Layout rules.
c) Design services and support
i) Design Rule Checker (DRC)
ii) Layout Versus Schematic (LVS)
iii) Process rules (wafer fab and assembly)
iv) CAD Models.
d) Circuit design tools
i) Linear simulation (frequency domain)
ii) Harmonic balance
iii) SPICE
iv) Electromagnetic analysis
v) Other.
60747-16-10 © IEC:2004(E) – 19 –
e) Conversion or adaptation of existing designs
Any activities not so described shall be stated with reference to the relevant
documentation and interface controls. The information to be listed, where applicable,
concerns:
i) basic technologies (processes, layers, elements, geometries, described in design
book, etc.);
ii) design rules identification (including physical, electrical and layout for wafer fab and
assembly also described in design book);
iii) CAD data and tools for each type of component e.g. hardware, software and cell
libraries generally part of the design kit;
iv) verification and validation procedures;
v) package selection or design procedures;
vi) test programmes (e.g. test description language, test parameters, etc.).
3.2.2 Flow charts
For an example of a typical flow chart, see Figure 2.
3.3 Interfaces
3.3.1 Design/manufacture
The manufacturing interrelationship during the design stages shall be declared, including
those with
– manufacturing (mask manufacture and/or fabrication),
– management of software configuration and library updates,
– upward compatibility,
– documentation,
– traceability,
– usage limits (model, accuracy),
– usage of verification tools (DRC, ERC, LVS),
– assembly (including package suppliers),
– prototyping (if applicable),
– characterization and test (including equipment and specifications),
– any other requirements.
3.3.2 Customer/user
The design centre defines its policy related to the involvement of the customer during the
various design steps:
• Specifications
− writing the technical need specification.
• Design reviews
− functional simulation,
− test oriented simulation ,
− place and electromagnetic simulation.

– 20 – 60747-16-10 © IEC:2004(E)
• Prototyping (if applicable)
− characterization and evaluation of prototypes.
The design centre is responsible for the application of the design and fabrication rules related
to the identified technology. It is also responsible for the correct test methodology to fulfil the
requirements of the technical need specification.
3.3.3 Interface with test centre
An identification and description of the interface between the design centre (responsible for
the implementation of testability inside the circuit and test element group generation) and the
entity realising, controlling and running the tester and the test programme shall be made.
A description shall be given of the methodology concerning:
– evaluation and tests on characterization of prototypes (if applicable);
– evaluation and tests on wafers (probing);
– evaluation and control of finished products;
– evaluation and tests to investigate failures mechanisms.
3.3.4 Vendor software capability
a) Software transparency/portability
This subclause outlines the steps to be taken to ensure that a piece of software is
transparent and portable.
b) Definitions
Portability
The software is applicable to different processes, e.g. several MMIC processes. Portability
can be to different levels, e.g. a piece of software can be used
– for 0,5 µm processes only,
– or for all 0,25 µm and 0,5 µm processes,
– or for all MMIC processes from a specific manufacturer, etc.
Transparency
The degree to which the software handles the details of the chip design without detailed
knowledge from the user, e.g.:
– Software with little transparency is that currently used for full custom design where the
software is merely a tool for layout/simulation etc., and the designer makes all the
decisions.
This leads to several issues to be addressed primarily by the software vendor. To identify
the degree of transparency/portability, attention is paid to the following points:
i) If vendors claim their software to be portable some sort of benchmarking must be
carried out.
ii) The qualification level of personnel used as MMIC designers will vary according to
level of transparency/portability, e.g. they may be educated in, say, MMIC design
techniques, but need no knowledge of a particular process; or, with a higher level of
design software, they need know nothing about microwave elements at all.
iii) The configuration of the design on the computer also needs to be transparent to the
user, i.e. the software vendor should take responsibility for the configuration control.

60747-16-10 © IEC:2004(E) – 21 –
iv) Software vendor sets up and funds a system (e.g. a user group) to ensure that all user
problems are identified and corrected.
v) A version of design software may be changed part way through a design, requiring the
transfer of files or cells produced using one version to another version. In such a case,
the designer shall make a record of the file/cell name thus transferred, giving the
name of the file just prior to transfer, the name just after transfer and the date of
transfer. This will ensure traceability in the case of errors due to software bugs
appearing at a later date.
3.3.5 Subcontractors, vendors and internal suppliers
Design may be subcontracted in accordance with 2.4.
3.4 Validations and control of the processes
3.4.1 Global design methodology
The methodology used to define the overall design process shall be described, and shall
include:
– structure of design;
– testability of the design topology;
– documentation.
3.4.2 Validation of simulation results against technical needs specification
The methodology to cover the technical need specification shall be defined. The following
points
...

IEC 60747-16-10 ®
Edition 1.0 2004-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices –
Part 16-10: Technology Approval Schedule (TAS) for monolithic microwave
integrated circuits
Dispositifs à semiconducteurs –
Partie 16-10: Format-cadre pour agrément de technologie (TAS) pour circuits
intégrés monolithiques hyperfréquences

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IEC 60747-16-10 ®
Edition 1.0 2004-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices –
Part 16-10: Technology Approval Schedule (TAS) for monolithic microwave

integrated circuits
Dispositifs à semiconducteurs –

Partie 16-10: Format-cadre pour agrément de technologie (TAS) pour circuits

intégrés monolithiques hyperfréquences

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX XA
ICS 31.200 ISBN 978-2-83220-619-5

– 2 – 60747-16-10  IEC:2004
CONTENTS
FOREWORD . 4
Foreword to this particular Technology Approval Schedule (TAS) . 7
Organizations responsible for preparing the present TAS . 7
Preface . 7
INTRODUCTION . 8
1 General . 9
1.1 Scope . 9
1.2 Normative documents . 9
1.3 Units, symbols and terminology . 10
1.4 Standard and preferred values . 10
1.5 Definitions . 10
2 Definition of the component technology . 12
2.1 Scope . 12
2.2 Description of activities and flow charts . 13
2.3 Technical abstract . 13
2.4 Requirements for control of subcontractors . 16
3 Component design of MMICs . 18
3.1 Scope . 18
3.2 Description of activities and flow charts . 18
3.3 Interfaces . 19
3.4 Validations and control of the processes . 21
4 Mask manufacture . 23
4.1 Scope . 23
4.2 Description of activities and flow charts . 23
4.3 Validation and control of the processes . 23
4.4 Subcontractors, vendors and internal suppliers . 23
5 Wafer fabrication of MMICs . 23
5.1 Scope . 23
5.2 Description of activities and flow charts . 24
5.3 Equipment . 26
5.4 Materials . 26
5.5 Re-work . 26
5.6 Validation methods and control of the processes . 27
5.7 Interrelationship . 28
6 Wafer probing of MMICs . 30
6.1 Scope . 30
6.2 Description of activities and flow charts . 30
6.3 Equipment . 30
6.4 Test procedures . 30
6.5 Interrelationship . 30
7 Back-side process for bare chip delivery . 32
7.1 Scope . 32
7.2 Description of activity and flow charts . 32
7.3 Equipment . 33
7.4 Materials . 33

60747-16-10  IEC:2004 – 3 –
7.5 Validation methods and control of the processes . 33
7.6 Interrelationship . 33
7.7 Validity of release . 34
8 Assembly of MMICs . 36
8.1 Scope . 36
8.2 Description of activities and flow charts . 36
8.3 Materials, inspection and handling. 37
8.4 Equipment . 37
8.5 Re-work . 37
8.6 Validation and control of the processes . 37
8.7 Interrelationships . 38
9 Testing of MMICs . 40
9.1 Scope . 40
9.2 Description of activities and flow charts . 40
9.3 Equipment . 40
9.4 Test procedures . 41
9.5 Interfaces . 42
9.6 Validation and control of the processes . 43
9.7 Process boundary verification . 46
9.8 Product verification. 50
10 Process characterization . 50
10.1 Identification of process characteristics . 50
10.2 Description of activities . 51
10.3 Characterization procedures . 52
11 Packaging and shipping . 53
11.1 Description of activities and flow charts . 53
11.2 Interfaces . 54
11.3 Validity of release . 54
12 Withdrawal of Technology Approval . 56

Figure 1 – Example flow chart of design/manufacture/test. 16
Figure 2 – Example flow chart of a design . 21
Figure 3 – Technology flow chart of the process . 29
Figure 4 – Example flow chart for a wafer probing. . 30
Figure 5 – Example flow chart for a back-side process for bare chip delivery . 34
Figure 6 – Example flow chart for an assembly . 38
Figure 7 – Example flow char for a testing . 44
Figure 8 – Typical flow chart for packaging and shipping . 54

– 4 – 60747-16-10  IEC:2004
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
Part 16-10: Technology Approval Schedule (TAS)
for monolithic microwave integrated circuits

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60747-16-10 has been prepared by subcommittee 47E: Discrete
semiconductor devices, of IEC technical committee 47: Semiconductor devices.
This bilingual version (2013-01) corresponds to the monolingual English version, published in
2004-07.
The text of this standard is based on the following documents:
FDIS Report on voting
47E/257/FDIS 47E/262/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The French version of this standard has not been voted upon.

60747-16-10  IEC:2004 – 5 –
This publication has been partially drafted in accordance with the ISO/IEC Directives, Part 2
(2001). It also follows the requirements given in IEC QC 210000:1995, Technology Approval
Schedules – Requirements under the IEC Quality Assessment System for Electronic
Components (IECQ-CECC).
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
– 6 – 60747-16-10  IEC:2004
International Electrotechnical Commission QC 210021
Quality Assessment System for Electronic Components (IECQ-CECC)

Responsible NAI: Name Specification available as shown in
Address QC 001004 Specifications List or from any
Tel:  National Authorized Institution (NAI)
Fax:
TECHNOLOGY APPROVAL SCHEDULE
(Monolithic microwave integrated circuits)

Issue
QC 210021
2004-07
60747-16-10  IEC:2004 – 7 –
Foreword to this particular Technology Approval Schedule (TAS)
The IEC Quality Assessment System for Electronic Components (lECQ) is composed of those
member countries of the International Electrotechnical Commission (lEC) that wish to take
part in a harmonized system for electronic components of assessed quality.
The object of the System is to facilitate international trade by the harmonization of
specifications and quality assessment procedures for electronic components and by the
granting of an internationally recognized mark or certificate of conformity. The components
produced under the System are acceptable in all member countries without further testing.
This TAS has been prepared for use by those countries taking part in the System who wish to
issue national harmonized specifications for Technology Approval of manufacturers of
monolithic microwave integrated circuits. It should be read in conjunction with the current
regulations of the IECQ-CECC System.
At the date of printing of this schedule the member countries of IECQ-CECC are China,
Denmark, France, Germany, India, Italy, Japan, Republic of Korea, Netherlands, Norway,
Russian Federation, Switzerland, Thailand, Ukraine, United Kingdom, USA and Yugoslavia.
Copies of this schedule can be obtained from their National Authorized Institutions, National
Standards Organizations or, in case of difficulty, from the Central Office of IEC in Geneva,
Switzerland (fax [phone]) as described in the Specifications List QC 001004 on
www.iecq-cecc.org.
Organizations responsible for preparing the present TAS
IEC subcommittee 47E: Discrete semiconductor devices
Preface
This schedule was prepared by SC47E/WG2.
It is based, wherever possible, on the publications of the International Electrotechnical
Commission (lEC) and the International Organization for Standardization (ISO) and in
particular on:
IEC 60747-16-1: Semiconductor devices – Part 16-1: Microwave integrated circuits –
Amplifiers,
IEC 60747-16-2: Semiconductor devices – Part 16-2: Microwave integrated circuits –
Frequency prescalers,
IEC 60747-16-3: Semiconductor devices – Part 16-3: Microwave integrated circuits –
Frequency converters,
IEC 60747-16-4: Semiconductor devices – Part 16-4: Microwave integrated circuits –
Switches.
– 8 – 60747-16-10  IEC:2004
INTRODUCTION
The requirements for Technology Approval for manufacturers of electronic and electro-
mechanical components are given in QC 001002-3, Clause 6. The procedures for approval
defined in that clause require the manufacturer to have available an appropriate Technology
Approval Schedule (TAS).
This schedule defines how the principles and requirements of QC 001002-3, Clause 6, are
applied to monolithic microwave integrated circuits.

60747-16-10  IEC:2004 – 9 –
SEMICONDUCTOR DEVICES –
Part 16-10: Technology Approval Schedule (TAS)
for monolithic microwave integrated circuits

1 General
1.1 Scope
This TAS specifies the terms, definitions, symbols, quality system, test, assessment and
verification methods and other requirements relevant to the design, manufacture and supply
of monolithic microwave integrated circuits in compliance with the general requirements of the
IECQ-CECC System for electronic components of assessed quality.
1.2 Normative documents
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60027 (all parts): Letter symbols to be used in electrical technology
IEC 60050: International Electrotechnical Vocabulary
IEC 60068 (all parts): Environmental testing
IEC 60191-2: Mechanical standardisation of semiconductor devices – Part 2: Dimensions
IEC 60617-DB (all parts): Graphical symbols for diagrams
IEC 60747-1: Semiconductor devices – Discrete devices and integrated circuits – Part 1:
General
IEC 60747-16-1: Semiconductor devices – Part 16-1: Microwave integrated circuits –
Amplifiers
IEC 60747-16-2: Semiconductor devices – Part 16-2: Microwave integrated circuits –
Frequency prescalers
IEC 60747-16-3: Semiconductor devices – Part 16-3: Microwave integrated circuits –
Frequency converters
IEC 60747-16-4: Semiconductor devices – Part 16-4: Microwave integrated circuits –
Switches
IEC 60748-1: Semiconductor devices – Integrated circuits – Part 1: General
ISO 1000: SI units and recommendations for the use of their multiples and certain other units
———————
DB” refers to the IEC on-line database.
2 To be published.
– 10 – 60747-16-10  IEC:2004
1.3 Units, symbols and terminology
Units, graphical symbols, letter symbols and terminology shall, whenever possible, be taken
from the following documents:
IEC 60027: Letter symbols to be used in electrical technology
IEC 60050: International electrotechnical vocabulary
IEC 60617-DB: Graphical symbols for diagrams
ISO 1000: SI units and recommendations for the use of their multiples and certain other units
Any other units, symbols and terminology specific to the scope of this TAS shall be taken from
the relevant IEC or ISO documents listed under Normative documents.
1.4 Standard and preferred values
Technology Approval allows the customization of the component or process to suit each
customer. The conventional concept of preferred values may thus have limited application.
However, when internationally recognized preferred values apply these should be used, e.g.
voltage, temperature and dimensions. Reference shall be made to the appropriate IEC or ISO
publications, i.e.:
– voltage IEC 60747-1
– temperature IEC 60747-1
– dimensions IEC 60191-2.
1.5 Definitions
For the purposes of this document, the following definitions apply.
1.5.1 General terms for monolithic microwave integrated circuits
1.5.1.1
microelectronics
(IEC 60748-1, definition 4.1.5)
1.5.1.2
microcircuit
(IEC 60748-1, definition 4.2.2)
1.5.1.3
integrated circuit
(IEC 60748-1, definition 4.2.3)
1.5.1.4
integrated microcircuit
microcircuit in which a number of circuit elements are inseparably associated and electrically
interconnected such that for the purpose of specification and testing and commerce and
maintenance, it is considered indivisible
NOTE 1 For this definition, a circuit element does not have an envelope or external connection and is not
specified or sold as a separate item.
NOTE 2 Where no misunderstanding is possible, the term "integrated microcircuit" may be abbreviated to
"integrated circuit".
NOTE 3 Further qualifying terms may be used to describe the technique used in the manufacture of a specific
integrated microcircuit. Examples to the use of qualifying terms: semiconductor monolithic integrated circuit;
semiconductor multi-chip integrated circuit; thin film integrated circuit; thick film integrated circuit; hybrid integrated
circuit.
60747-16-10  IEC:2004 – 11 –
1.5.1.5
micro-assembly
microcircuit consisting of various components and/or integrated microcircuits which are
constructed separately and which can be tested before being assembled and packaged
NOTE 1 For this definition, a component has external connections and possibly an envelope as well and it also
can be specified and sold as a separate item.
NOTE 2 Further qualifying terms may be used to describe the form of the components and/or the assembly
techniques used in the construction of a specific micro-assembly. Examples of use of qualifying terms:
semiconductor multi-chip micro-assembly; discrete component micro-assembly.
1.5.2 List of abbreviations
– ASIC: Application Specific Integrated Circuit

– BDS: Blank Detail Specification
– BICMOS: Bipolar and Complementary Metal Oxide Silicon

– CAD: Computer Aided Design
– CAE: Computer Aided Engineering
– CECC: CENELEC Electronic Components Committee
– CMB: Contract Management Branch
– Cpk: Index of critical process capability

– Die Shear: Test on die attach
– DIL: Dual In Line Package
– DRC: Design Rules Check
– Dye Penetrant (ZYGLO): Seal test

– EDP: Electronic Data Processing
– EFR: Electrical Failure Rate
– ERC: Electrical Rules Check
– ESD: Electro Static Discharge

– GaAs: Gallium Arsenide
– HBT: Hetero-junction Bipolar Transistor
– HEMT: High Electron Mobility Transistor

– ISO 9000: ISO International Quality Rules

– JFET: Junction Field Effect Transistor

– LRM: Line Reflect Match
– LSSD: Level Sensitive Scan Design
– LVS: Layout Versus Schematics

– MESFET: Metal Semiconductor Field Effect Transistor
– MMIC: Monolithic Microwave Integrated Circuits
– MODFET: Modulation Doped Field Effect Transistor
– MTF: Mean Time to Failure
– MTBF: Mean Time Between Failures
– MTTR: Mean Time To Repair
– NMOS: Metal Oxide Silicon N channel

– 12 – 60747-16-10  IEC:2004
– OS: Operating System
– PAS: Publicly Available Specification
– PCM: Process Control Monitor
– PDA: Percentage Defectives Allowed
– PM: Parametric Monitor
– PMOS: Metal Oxide Silicon P channel
– POST CAP: Inspection after Encapsulation
– PRE CAP: Inspection before Encapsulation

– QA: Quality Assurance
– QCI: Quality Conformance Inspection
– QML: Qualified Manufacturer List

– RIE: Reactive Ion Etching
– SEC: Standard Evaluation Circuit
– SEM: Scanning Electron Microscope
– SI: Supervising Inspectorate
– SOI: Silicon on Insulator
– SOLT: Short Open Load Thru
– SOS: Silicon on Sapphire
– SPC: Statistical Process Control
– Si: Silicon
– TADD: Technology Approval Declaration Document
– TCI: Technology Conformance Inspection
– TCV: Technology Characterization Vehicle
– TDDB: Time Dependent Dielectric Breakdown
– TQM: Total Quality Management
– TRB: Technology Review Board
– TRL: Thru Reflect Line
– VT: Threshold Voltage for FET

– ZYGLO: see Dye Penetrant.
NOTE PCM and PM have the same meaning; however, PCM is the term used in the following subclauses.
1.5.3 Definitions relevant to the scope of the TAS
See QC 001002-3, Clause 6 for definitions specific to Technology Approval.
2 Definition of the component technology
2.1 Scope
The Technology Approval for the declared range or family of components shall include their
design and manufacturing processes and their interfaces. The overall management of these
interfaces by the Control Site shall be included. These processes and interfaces shall be
declared within the Technology Approval Declaration Document (TADD).

60747-16-10  IEC:2004 – 13 –
More detailed requirements for the listed processes and interfaces to be included within the
Technology Approval are given in the relevant clauses of this TAS. The processes are listed
below with the identification of the MAIN TECHNICAL PROCESS:
• Process characterization
• Integrated circuit design – This is a MAIN TECHNICAL PROCESS
• Mask manufacture
• Wafer fabrication – This is a MAIN TECHNICAL PROCESS
• Back-side process
• Wafer probe
• Assembly – This is a MAIN TECHNICAL PROCESS
• Test and release – This is a MAIN TECHNICAL PROCESS
• Packaging and shipping
Shipping includes the temporary storage of finished products before shipment to the
customer.
2.2 Description of activities and flow charts
2.2.1 Description of activities
All the activities (processes) shall be identified with the relevant flow charts included. This
information may include different processes for different types of components but covered by
the same technology. Where applicable, these should address all the processes listed in 2.1.
The design and manufacturing cycle of integrated circuits may involve one or more qualified
company or facility handing different tasks within the “life cycle” of an MMIC.
Design, development or specification of an MMIC is performed to the specific requirements of
a customer, which may be an external customer (such as for an application-specific MMIC), or
an internal department.
The prime contractor is that organization which undertakes the responsibility for the
management of all tasks prior to the supply of an MMIC to the specified requirements.
2.2.2 Flow charts
The flow chart in Figure 1 is an example showing such operations, where the specific stages
are expected to be defined, referencing the relevant internal documentation.
2.3 Technical abstract
2.3.1 TADD abstract (not for publication)
The Technology Approval technical abstract shall be declared by the technology approval
declaration document (TADD).
For each technology declared the following shall be identified:
• Description of design tools used e.g. CAD systems, software;
• Description of wafer fabrication processes including feature size, technology, types and
number of interconnects
– e.g. 0,5 µm gate, GaAs MESFET, double layer metal;

– 14 – 60747-16-10  IEC:2004
• Description/list of products and/or family of products
– e.g. low noise amplifiers; power amplifiers; switches;
• Description of packaging types/materials and range of pincounts
– e.g. chip form: ceramic, DIL 8, 16 pin;
• Description of test equipment, i.e. type of test equipment and scope.
An example of a Technology Approval technical abstract is given in 2.3.3.
2.3.2 QC 001005 abstract
The information to be published within QC 001005:2000, Register of Firms, Products and
Services approved under the IECQ-CECC System, including ISO 9000, may be based on the
information given to satisfy the Technology Approval technical abstract of 2.3.1. Information
marked with an asterisk (“*”) may be omitted in the published “Abstract of Technology
Approval” if requested by Control Site.

60747-16-10  IEC:2004 – 15 –
2.3.3 Example of a Technology Approval technical abstract
TECHNOLOGY DESCRIPTION: MONOLITHIC MICROWAVE INTEGRATED CICUIT
Manufacture [Control Site]: Name and location
IEC Reference: QC 210021 – TAS for Monolithic Microwave Integrated Circuits
Certificate Number: Reference of the local SI
TADD Generic: Control Site’s Document Reference
(Cross references to other TADD shall exist in the Generic Specification
where applicable).
LIBRARY/DESIGN
Manufacturer’s name of the library:
Information on the library (where applicable):
Purpose: [ ] Microwave Design [ ] Digital Design [ ] Others
Types: [ ] Standard Cells [ ] Element Cells
Contents: Types of cells
WAFER FABRICATION:
Wafer Fabrication Process Name: (e.g. “AMES0.5” etc.)
Wafer Fabrication Process Type: (e.g. FET/Bipolar etc.)
Function: (e.g. Standard Cell/Custom etc.)
Production Families: (e.g. Low Noise/High Power/Control etc.)
Details:
Wafer Size: (e.g. 100 mm)
Gate Length: (e.g. 0,5 µm)
Maximum Interconnect Levels:* (Triple/Double/Single Level/Metal etc.)*
Transmission line structure: (e.g. microstrip/coplanar waveguide etc.)
Metal Compositions:* (Al/Si/Al/Cu etc.)*
Gate Material:* (Metal/Polysilicon etc.)*
Passivation Material:* (1,2 µm Compressive Nitride etc.)*
Substrate Material:* (e.g. GaAs)*
Number of masks:* (e.g. 8)*
ASSEMBLY:
Package types: (e.g. Thin Plastic Quad Flat Pack, 7,6 mm Small Outline (SO) etc.)
Details:
Maximum Die Size: (e.g. TPQFP – 9 x 9 mm: SO300 – 2,3 mm x 2,3 mm)
Package materials: (e.g. Ceramic/Epoxy/Plastic etc.)
Header/Leadframe:* (e.g. Copper/Alloy 42 etc.)*
Pin/Lead Finish: (e.g. Gold/Solder Dipped etc.)
Die Attachment:* (e.g. Silicon-Gold Eutectic etc.)*
Bond Wire Attachment:* (e.g. Aluminium, Ultrasonic etc.)*
Package assembly
ELECTRICAL CHARACTERISTICS OF PRODUCTS:
Supply Voltage Range:
Maximum Input Power:
Total Power Dissipation:
Maximum Operating Frequency:
Operating Temperature Range:
Storage Temperature Range:
ENVIRONMENTAL/RELIABILITY LIMITS:
Endurance Test Performance: (e.g. > x year at 55 °C or > 1 000 h at 125 °C)
Accelerated Damp Heat Severity: (e.g. > x year at 55 °C/60 % RH or 1 000 h at 85 °C/85 % RH)
Temperature Cycling Extremes: (e.g. –65 °C / +150 °C)
etc.
AND
Expected Failure Rate (under specified environments)
Quality Factor (π ).
Q
(The limits of approval shall be made available to the customer, and any tests should correlate to IEC
test methods and should be suitable for the intended application.)

– 16 – 60747-16-10  IEC:2004
2.4 Requirements for control of subcontractors
Where a technical process as defined in 2.1 is subcontracted, the procedures and criteria
employed to demonstrate control shall be specified. This may be achieved either by the
demonstration of conformance to the requirements of the appropriate PAS (Publicly Available
Specification) in the IECQ-CECC 200000 series, or by demonstrating that the processes have
been satisfactorily performed in accordance with criteria defined or referenced from the TADD.
Such criteria shall be capable of demonstrating compliance with the declaration of reliability
and environmental performance.
The following items shall be specified:
• Reason for subcontracting
• Name and address
• IECQ-CECC Process and Approval or Technology Approval certificate reference (where
appropriate)
• Name of CMB (Contract Management Branch) contract within the subcontractor
• Documentation
• Interrelationship documentation.
NOTE Design, mask manufacture, wafer fabrication, wafer probe, assembly, testing, packaging and shipping may
be subcontracted provided that the control site has the capability for at least one of the MAIN TECHNICAL
PROCESSES as defined in 6.2.1.3 of QC 001002-3.

60747-16-10  IEC:2004 – 17 –
CUSTOMER
Custom IC
INTEGRATED
CIRCUIT DESIGN
CENTRE
MASK
MANUFACTURE
WAFER
FABRICATION
PROBE
TEST
ASSEMBLY
TEST
PACKAGING
AND
SHIPPING
IEC  876/04
NOTE This is an example of a packaged device.
Figure 1 – Example flow chart of design/manufacture/test

– 18 – 60747-16-10  IEC:2004
3 Component design of MMICs
3.1 Scope
Design information relevant to the technology for which approval is sought shall be included in
the TADD.
This shall include design of the semiconductor process incorporating modification and
publication of the process parameters and related process design rules in the form of written
and computer files suitable for use in CAD tools at either internal customers or independent
design centres.
Process characterization and circuit design are, in general, separate though inter-related
tasks, and so their interfaces with the process design task shall be specified in detail, including
management responsibilities, transfer specifications, requirements and deliverables.
The IC design centre is responsible for the design of integrated circuits in accordance with
customer requests as defined by product or other specifications, generally by translation from
received data into IC specifications, then design and simulation phases followed by
production of data, specifications, and computer files (or equivalent) required for manu-
facturing. This shall generally employ data from the process design task.
Activities may include mask making and writing product test programmes or test data suitable
for development into test programmes by a test centre or task.
3.2 Description of activities and flow charts
3.2.1 Description of activities
The activities of design for integrated circuits shall be declared, including flow charts showing
all activities, critical steps, check points and quality indicators, referencing the relevant
internal documentation. These shall include any or all of items a) to e) below, as appropriate:
a) Feasibility
The availability of equipment and of the design/manufacturing capacity to cover the
required production lot quantities shall be verified.
b) Process design
i) Physical characteristics (required for circuit design)
ii) Electrical characteristics
iii) Layout rules.
c) Design services and support
i) Design Rule Checker (DRC)
ii) Layout Versus Schematic (LVS)
iii) Process rules (wafer fab and assembly)
iv) CAD Models.
d) Circuit design tools
i) Linear simulation (frequency domain)
ii) Harmonic balance
iii) SPICE
iv) Electromagnetic analysis
v) Other.
60747-16-10  IEC:2004 – 19 –
e) Conversion or adaptation of existing designs
Any activities not so described shall be stated with reference to the relevant
documentation and interface controls. The information to be listed, where applicable,
concerns:
i) basic technologies (processes, layers, elements, geometries, described in design
book, etc.);
ii) design rules identification (including physical, electrical and layout for wafer fab and
assembly also described in design book);
iii) CAD data and tools for each type of component e.g. hardware, software and cell
libraries generally part of the design kit;
iv) verification and validation procedures;
v) package selection or design procedures;
vi) test programmes (e.g. test description language, test parameters, etc.).
3.2.2 Flow charts
For an example of a typical flow chart, see Figure 2.
3.3 Interfaces
3.3.1 Design/manufacture
The manufacturing interrelationship during the design stages shall be declared, including
those with
– manufacturing (mask manufacture and/or fabrication),
– management of software configuration and library updates,
– upward compatibility,
– documentation,
– traceability,
– usage limits (model, accuracy),
– usage of verification tools (DRC, ERC, LVS),
– assembly (including package suppliers),
– prototyping (if applicable),
– characterization and test (including equipment and specifications),
– any other requirements.
3.3.2 Customer/user
The design centre defines its policy related to the involvement of the customer during the
various design steps:
• Specifications
− writing the technical need specification.
• Design reviews
− functional simulation,
− test oriented simulation ,
− place and electromagnetic simulation.

– 20 – 60747-16-10  IEC:2004
• Prototyping (if applicable)
− characterization and evaluation of prototypes.
The design centre is responsible for the application of the design and fabrication rules related
to the identified technology. It is also responsible for the correct test methodology to fulfil the
requirements of the technical need specification.
3.3.3 Interface with test centre
An identification and description of the interface between the design centre (responsible for
...