IEC 62271-101:2012/AMD1:2017
(Amendment)Amendment 1 - High-voltage switchgear and controlgear - Part 101: Synthetic testing
Amendment 1 - High-voltage switchgear and controlgear - Part 101: Synthetic testing
The contents of the corrigendum of January 2018 have been included in this copy.
Amendement 1 - Appareillage à haute tension - Partie 101: Essais synthétiques
Le contenu du corrigendum de janvier 2018 a été pris en considération dans cet exemplaire.
General Information
Relations
Standards Content (Sample)
IEC 62271-101 ®
Edition 2.0 2017-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
A MENDMENT 1
AM ENDEMENT 1
High-voltage switchgear and controlgear –
Part 101: Synthetic testing
Appareillage à haute tension –
Partie 101: Essais synthétiques
IEC 62271-101:2012-10/AMD1:2017-11(en-fr)
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC
copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or
your local IEC member National Committee for further information.
Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduite
ni utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopie
et les microfilms, sans l'accord écrit de l'IEC ou du Comité national de l'IEC du pays du demandeur. Si vous avez des
questions sur le copyright de l'IEC ou si vous désirez obtenir des droits supplémentaires sur cette publication, utilisez
les coordonnées ci-après ou contactez le Comité national de l'IEC de votre pays de résidence.
IEC Central Office Tel.: +41 22 919 02 11
3, rue de Varembé Fax: +41 22 919 03 00
CH-1211 Geneva 20 info@iec.ch
Switzerland www.iec.ch
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.
About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.
IEC Catalogue - webstore.iec.ch/catalogue Electropedia - www.electropedia.org
The stand-alone application for consulting the entire The world's leading online dictionary of electronic and
bibliographical information on IEC International Standards, electrical terms containing 20 000 terms and definitions in
Technical Specifications, Technical Reports and other English and French, with equivalent terms in 16 additional
documents. Available for PC, Mac OS, Android Tablets and languages. Also known as the International Electrotechnical
iPad. Vocabulary (IEV) online.
IEC publications search - www.iec.ch/searchpub IEC Glossary - std.iec.ch/glossary
The advanced search enables to find IEC publications by a 65 000 electrotechnical terminology entries in English and
variety of criteria (reference number, text, technical French extracted from the Terms and Definitions clause of
committee,…). It also gives information on projects, replaced IEC publications issued since 2002. Some entries have been
and withdrawn publications. collected from earlier publications of IEC TC 37, 77, 86 and
CISPR.
IEC Just Published - webstore.iec.ch/justpublished
Stay up to date on all new IEC publications. Just Published IEC Customer Service Centre - webstore.iec.ch/csc
details all new publications released. Available online and If you wish to give us your feedback on this publication or
also once a month by email. need further assistance, please contact the Customer Service
Centre: csc@iec.ch.
A propos de l'IEC
La Commission Electrotechnique Internationale (IEC) est la première organisation mondiale qui élabore et publie des
Normes internationales pour tout ce qui a trait à l'électricité, à l'électronique et aux technologies apparentées.
A propos des publications IEC
Le contenu technique des publications IEC est constamment revu. Veuillez vous assurer que vous possédez l’édition la
plus récente, un corrigendum ou amendement peut avoir été publié.
Catalogue IEC - webstore.iec.ch/catalogue Electropedia - www.electropedia.org
Application autonome pour consulter tous les renseignements Le premier dictionnaire en ligne de termes électroniques et
bibliographiques sur les Normes internationales, électriques. Il contient 20 000 termes et définitions en anglais
Spécifications techniques, Rapports techniques et autres et en français, ainsi que les termes équivalents dans 16
documents de l'IEC. Disponible pour PC, Mac OS, tablettes langues additionnelles. Egalement appelé Vocabulaire
Android et iPad. Electrotechnique International (IEV) en ligne.
Recherche de publications IEC - www.iec.ch/searchpub Glossaire IEC - std.iec.ch/glossary
La recherche avancée permet de trouver des publications IEC 65 000 entrées terminologiques électrotechniques, en anglais
en utilisant différents critères (numéro de référence, texte, et en français, extraites des articles Termes et Définitions des
comité d’études,…). Elle donne aussi des informations sur les publications IEC parues depuis 2002. Plus certaines entrées
projets et les publications remplacées ou retirées. antérieures extraites des publications des CE 37, 77, 86 et
CISPR de l'IEC.
IEC Just Published - webstore.iec.ch/justpublished
Restez informé sur les nouvelles publications IEC. Just Service Clients - webstore.iec.ch/csc
Published détaille les nouvelles publications parues. Si vous désirez nous donner des commentaires sur cette
Disponible en ligne et aussi une fois par mois par email. publication ou si vous avez des questions contactez-nous:
csc@iec.ch.
IEC 62271-101 ®
Edition 2.0 2017-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
A MENDMENT 1
AM ENDEMENT 1
High-voltage switchgear and controlgear –
Part 101: Synthetic testing
Appareillage à haute tension –
Partie 101: Essais synthétiques
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 29.130.10 ISBN 978-2-8322-4811-9
– 2 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
FOREWORD
This amendment has been prepared by subcommittee 17A: Switching devices, of IEC
technical committee 17: High-voltage switchgear and controlgear.
The text of this amendment is based on the following documents:
FDIS Report on voting
17A/1149/FDIS 17A/1154/RVD
Full information on the voting for the approval of this amendment can be found in the report
on voting indicated in the above table.
The committee has decided that the contents of this amendment and the base publication will
remain unchanged until the stability date indicated on the IEC website under
"http://webstore.iec.ch" in the data related to the specific publication. At this date, the
publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
The contents of the corrigendum of January 2018 have been included in this copy.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
_____________
INTRODUCTION to the Amendment
This amendment includes the following significant technical changes:
– the test procedure for test-duty T100a has been aligned with IEC 62271-100;
– Annexes A through D have been transferred to IEC 62271-306;
– Annex I has been revised and now includes Annex P of IEC 62271-100;
– Annexes K, L and N have been revised.
_____________
2 Normative references
Replace the existing reference to IEC 62271-100:2008 by the following new reference:
IEC 62271-100:2008, High-voltage switchgear and controlgear – Part 100: Alternating current
circuit-breakers
© IEC 2017
IEC 62271-100:2008/AMD 1:2012
IEC 62271-100:2008/AMD 2:2017
3.17
minimum clearing time
Replace the entire term, definition, note and source as follows:
3.17
(void)
Add, after the definition 3.18, a new term and definition as follows:
3.19
intermediate asymmetry
level of asymmetry in the other two phases having a reduced (intermediate) level of
asymmetry when in a three-phase system the short-circuit current is initiated simultaneously
in all phases and maximum asymmetry is obtained in one of the phases
4.1.2 High-current interval
Replace the entire subclause by the following:
The tolerance on the amplitude and the power frequency of the prospective breaking current
is given in 6.103.2 and 6.104.3 of IEC 62271-100:2008. Therefore, the following conditions
concerning the actual current through the test circuit-breaker shall be met:
– for symmetrical testing the current amplitude and final loop duration shall not be less than
90 % of the required values based on the current of the test-duty considered;
– for SLF test-duties and T100s and T100a when tested with ITRV, the product of the
current amplitude and the duration of the final loop shall not be less than 95 % of the
required values based on the current of the test-duty considered;
– for asymmetrical testing, both the current amplitude and final loop duration shall be
between 90 % and 110 % of the required values, based on the current of the test-duty
considered and time constant (see Tables L.12 to L.17).
In rare cases, where the applied voltage from the high current source is of the same
magnitude as the required test voltage in a direct test circuit, a higher deviation of the last
current loop is accepted provided that the prospective current loop with the auxiliary circuit-
breaker arcing is within the specified tolerances.
4.1.4 High-voltage interval
Replace the first sentence of the first hyphen by the following:
The initial value of the power-frequency recovery voltage, excluding the transient oscillations,
shall not be less than the equivalent initial value of the power-frequency recovery voltage
specified in 6.104.7 of IEC 62271-100:2008 which, for a test with symmetrical current, starts
with a minimum peak value of 0,95×k ×U √(2/3).
pp r
4.2.1 Current injection methods
Replace, in the first sentence, "(see Annex B)" by "(see IEC 62271-306)".
Add, after the second indent, the following new sentences:
Current injection method is mandatory for:
– short-line fault test duties;
– 4 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
– T100s and T100a when tested with ITRV.
The time during which the arc is fed only by the injected current shall be treated as part of the
length of the final current loop.
Replace the paragraph below the second hyphen by the following:
If any device with breaking capability interrupts the current through the test circuit-breaker at
the same time as the test circuit-breaker, the method is not a valid current injection method.
Replace, in item c), "(see Annex B)" by "(see IEC 62271-306)".
4.2.2 Voltage injection method
Replace, in the first sentence, "(see also Annex C)" by "(see IEC 62271-306)".
Delete the sentence below the third hyphen of the first list.
4.2.3 Duplicate circuit method (transformer or Skeats circuit)
Replace, in the first sentence, "(see also Annex D)" by "(see IEC 62271-306)".
Delete the penultimate paragraph.
Replace, in the last paragraph, "See Annex D" by "See IEC 62271-306".
4.2.4 Other synthetic test methods
Remove the last two paragraphs.
Table 3 – Test parameters during three-phase interruption for test-duties T10, T30, T60
and T100s, k = 1,3
pp
Replace "98" by "97" (3 instances).
5.2.2 Test circuit
Replace the second sentence of the first paragraph by the following:
Examples of circuits showing voltage and current wave shapes are given in Figures 5 and 6
for single-phase and Figure 7 for three-phase.
6 Specific requirements for synthetic tests for making and breaking
performance related to the requirements of 6.102 through 6.111 of
IEC 62271-100:2008
Replace the existing title by the following new title:
6 Type tests
Add, before the existing text of this clause, the following new title:
6.1 General
Replace the second paragraph by the following new paragraphs and new table:
© IEC 2017
Requirements concerning testing of metal enclosed and dead tank circuit-breakers are given
in Annex N.
General requirements for circuit-breakers with opening resistors are given in Annex R of
IEC 62271-100:2008/AMD1:2012. A method available for testing circuit-breakers having
opening resistors is reported in Annex F.
The abbreviations given in Table 6 are used to specify the operations to be performed.
Table 6 – Abbreviations used for operation during synthetic tests
Cd Closing operation in a direct circuit at the voltage of the current source which can be less than the
voltage specified in 6.104.1 of IEC 62271-100:2008
(Cd) Closing operation as Cd, which may be carried out under no-load conditions
Cd Closing operation against the rated short-circuit making current according to 6.104.2 of
asy
IEC 62271-100:2008/AMD2:2017 in a direct circuit at conditions described under Cd
Cs Closing operation against a symmetrical current equal to the rated short-circuit breaking current,
sym
carried out at the required applied voltage in a synthetic circuit
Od Breaking operation at the voltage of the current source only and with the specified breaking current
Os Breaking operation with specified parameters in a synthetic circuit
t Time interval between operations (0,3 s or 3 min depending on the rated operating sequence)
t' Time interval between operations (3 min)
t" Time interval between operations (15 s)
SP Single-phase test as defined in 6.108 of IEC 62271-100:2008/AMD2:2017
DEF Double-earth fault test as defined in 6.108 of IEC 62271-100:2008/AMD2:2017
NOTE Due to the characteristics of synthetic testing it may be difficult to comply with the specified time intervals
of the rated operating sequence. See 6.105.1 of IEC 62271-100:2008/AMD1:2008.
In order to comply with all test requirements, it may be necessary to make more operations
than specified in the normal test-duty. In such cases the circuit-breaker may be reconditioned
and the test duty repeated.
6.102.10 Demonstration of arcing times
Replace the subclause by the following:
6.102.10 Demonstration of arcing times
6.102.10.1 General
The basic requirements to be met are given in 6.102.10 of IEC 62271-100:2008/AMD2:2017.
In order to be able to perform synthetic tests on the same basis as direct tests, normally it will
be necessary to apply special re-ignition methods to prolong the arcing of the test circuit-
breaker through the necessary number of zeros of the power-frequency current. See Annex H
for re-ignition methods to prolong arcing.
The "step-by-step" method described in Annex H is the method used on most synthetic tests.
The method is considered to be a sufficiently close approximation of the direct testing
procedure.
The arcing is prolonged by means of thermal re-ignitions. As this method makes it possible to
force the test circuit-breaker to re-ignite in all conditions, special care shall be taken not to re-
ignite the circuit-breaker at the instant of a current zero when the circuit-breaker can clear.
For this purpose it is necessary to determine, for each terminal fault, short-line fault and out-
– 6 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
of-phase test duty, the minimum arcing time of the circuit-breaker. At least two breaking tests,
one clearance and one re-ignition, are necessary for this determination.
The clearance at the minimum arcing time is the first valid breaking operation. The other test
is performed to demonstrate that a re-ignition at an early current zero would take place
between the arcing contacts. This re-ignition test shall not be the last in a test duty.
For Od operations, a tolerance of ±2 ms on the arcing time applies.
The extra tests necessary to demonstrate correct behaviour at early current zeros will usually
contribute insignificantly to contact wear, etc., due to the short arcing times. Therefore, no re-
conditioning should be necessary because of these tests.
The re-ignition(s) obtained when determining the minimum arcing time do(es) not indicate a
failure of the circuit-breaker. However, it is important to establish that this re-ignition has
taken place between the arcing contacts only. When using a current injection method, the
interruption of the injected current a few loops after the re-ignition is often a useful means for
the judgement. Thorough inspection of screens, arcing and main contacts, etc., should also
be made to verify correct behaviour.
NOTE When performing Od-COs, or COd-COs operations the first opening operation is performed in a direct test
circuit. This first opening operation should represent the minimum arcing time found for single opening operations.
In case the arcing time of this first opening operation is longer than required, the test is considered as more severe.
The minimum clearing time for test-duty T100a is validated by the minimum arcing time of an
interruption after a major loop with intermediate asymmetry.
6.102.10.2 Three-phase tests
Depending on the test circuit used, the test procedures given here may not cover the
rd
conditions of the 3 pole-to-clear for solidly earthed systems (k = 1,3). For this case the
pp
same procedures may be applied, with the manufacturer’s consent, by combining the TRV and
nd rd
di/dt parameters for the 2 pole-to-clear and the arcing time corresponding to the 3 pole-to-
clear. Alternatively, an additional test may be performed with the TRV, di/dt and the maximum
rd
arcing time corresponding to the 3 pole-to-clear.
For alternative testing procedures of multi-enclosure type circuit-breakers with operating
mechanism characteristics that require three-phase current, see Annex K.
6.102.10.2.1 Test duties T10, T30, T60, T100s, T100s(b)
The test procedure is as follows:
For convenience of testing, the pole in phase A is kept as the first-pole-to-clear.
First the minimum arcing time and correct re-ignition behaviour are established. This is done
by changing the setting of the tripping impulse in steps of 18° (possibly this has to be
repeated several times). After having done so, the setting of the control of the tripping impulse
has to be advanced by approximately 40°, starting from the shortest arcing time at which the
circuit-breaker cleared. For the last test, the setting of the control of the tripping impulse has
to be advanced by approximately 20°, starting from the shortest arcing time at which the
circuit-breaker cleared:
– first valid breaking operation: t , minimum arcing time in phase A;
arc min
– re-ignition test: t = t − 18°, re-ignition in phase A;
arc reig arc min
– second valid breaking operation: t = t + 40°, longest arcing time in phase A;
arc max arc min
– third valid breaking operation: t = t + 20°, medium arcing time in phase A.
arc med arc min
© IEC 2017
The first valid breaking operation and re-ignition test consist of single opening operations. The
second and third valid breaking operations are carried out as part of the rated operating
sequence. If the rated operating sequence is CO-15s-CO, the third valid breaking operation is
not required (see 6.102.10 of IEC 62271-100:2008/AMD2:2017).
For comparison with the arcing time settings used in three-phase direct tests, see Figure 8.
6.102.10.2.2 Test duty T100a
The intention is to demonstrate in a series of breaking tests the requirement a) and b) as
defined in clause 6.102.10.2.2 of IEC 62271-100:2008/AMD2:2017:
– condition a) where arc extinction occurs in the first-pole-to-clear at the end of a major loop
in the first phase with the required asymmetry criteria and with the longest possible arcing
time t ;
arc1
– condition b) where arc extinction occurs at the end of an extended major loop in the last-
pole-to-clear or in the second-pole-to-clear with the required asymmetry criteria and with
the longest possible arcing time, t and t as follows:
arc2 arc3
• the longest possible arcing time t applies for the last-pole-to-clear for circuit-
arc2
breakers rated for k = 1,5;
pp
• the longest possible arcing time t applies for the second-pole-to-clear for circuit-
arc3
breakers rated for k = 1,3 or 1,2.
pp
The test procedure, for three-phase testing, is as follows:
In order to simplify the test procedure, the pole in phase A is kept as the first-pole-to-clear. As
a consequence the pole in phase C will be subjected to increased electrical wear. In order to
obtain similar electrical wear on the poles of phase B and C, the test can be performed by
exchanging the poles of phases B and C for the second breaking operation.
First the minimum arcing time t (Figures 9 and 10, first test) and re-ignition behaviour
arc min
(Figures 9 and 10, second test) shall be demonstrated having intermediate asymmetry in
phase A (Tables L.12 to L.17, columns 7, 8 and 9) and with the major extended loop occurring
in phase C. This is done by changing the setting of the tripping impulse in steps of dα = 18°
(possibly this has to be repeated several times).
Before the next operation, initiation of short-circuit current shall be advanced by 60° where
the required asymmetry changes to phase A (Figures 9 and 10 third test). Arc extinction shall
occur in phase A, the first-pole-to-clear at the end of a major loop with the required
asymmetry criteria and with the maximum arcing time demonstrating condition a) mentioned
above.
The maximum arcing time t for the first pole-to-clear is achieved when the following
arc1
condition is met:
t = t + ∆t – T × dα/360°
arc1 arc min a1
In the next operation, the initiation of short-circuit current shall be delayed by 60°. As a result
the required asymmetry changes to phase C. Arc extinction shall occur in phase C at the end
of a major extended loop with the required asymmetry criteria and with the maximum arcing
time demonstrating condition b) mentioned above:
– the maximum arcing time t for the last-pole-to-clear for circuit-breakers intended to be
arc2
used in non-effectively earthed neutral systems (Figure 9 fourth test) is achieved when the
following condition is met:
t = t + ∆t – T × dα/360°
arc2 arc min a2
– 8 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
– the maximum arcing time t for the second-pole-to-clear for circuit-breakers intended to
arc3
be used in effectively earthed neutral systems (Figure 10 fourth test) is achieved when the
following condition is met:
t = t + ∆t – T × dα/360°
arc3 arc min a3
where ∆t , ∆t , ∆t are the relevant time parameters to be selected from Tables L.12 to
a1 a2 a3
L.17.
The order of the last two breaking operations can be interchanged.
Some circuit-breakers will not clear at the end of a major loop after the required arcing time.
However, this test is valid if the circuit-breaker clears the subsequent minor loop, that
becomes the last-pole-to-clear. The corresponding parameters for the last-pole-to-clear shall
be applied.
For comparison with the arcing settings used in three-phase direct tests, see Figures 9 and 10.
6.102.10.3 Single-phase tests in substitution for three-phase conditions, out-of-phase
and short-line fault tests
6.102.10.3.1 General
The procedures as described in 6.102.10.3 of IEC 62271-100:2008/AMD2:2017 are applicable
with the following changes. These procedures are meant to demonstrate the first-pole-to-clear,
the second-pole-to-clear and the third-pole-to-clear conditions, with current and voltage
parameters applicable for the first-pole-to-clear.
6.102.10.3.3 Test-duty T100a
The test procedure is as follows.
The minimum arcing time t and re-ignition behaviour shall be demonstrated with the
arc min
major loop at intermediate asymmetry (Tables L.12 to L.17, columns 8 and 9). This is done by
changing the setting of the tripping impulse in steps of 18° (possibly this has to be repeated
several times).
After that, two breaking operations at required asymmetry shall be performed as described
below. Tables L.12 to L.17, columns 3 and 4, give the required values of the peak short-circuit
current and loop duration that shall be attained in the last loop prior to the interruption.
One breaking operation, corresponding to condition a) of 6.102.10.2.2 of
IEC 62271-100:2008/AMD2:2017, shall demonstrate interruption at the end of the major loop
with an arcing time equivalent to the maximum arcing time under three-phase conditions t
arc1
of the first-pole-to-clear.
The maximum arcing time t for the first pole-to-clear is achieved when the following
arc1
condition is met:
t = t + ∆t – T × dα/360°
arc1 arc min a1
Another breaking operation, corresponding to condition b) of 6.102.10.2.2 of
IEC 62271-100:2008/AMD2:2017, shall demonstrate interruption at the end of the major loop
with an arcing time equivalent to the maximum arcing time under three-phase conditions:
– the maximum arcing time t for the last-pole-to-clear for circuit-breakers intended to be
arc2
used in non-effectively earthed neutral systems (k = 1,5) is achieved when the following
pp
condition is met:
© IEC 2017
= t + ∆t – T × dα/360°
t
arc2 arc min a2
– the maximum arcing time t for the second-pole-to-clear for circuit-breakers intended to
arc3
= 1,3 or k = 1,2) is achieved when the
be used in effectively earthed neutral systems (k
pp pp
following condition is met:
t = t + ∆t – T × dα/360°
arc3 arc min a3
where ∆t , ∆t , ∆t are the relevant time parameters to be selected from Tables L.12 to
a1 a2 a3
L.17.
The order of the last two breaking operations may be interchanged.
Since some circuit-breakers will not clear after a major loop, a test is still valid if the circuit-
breaker interrupts at the subsequent minor loop.
6.102.10.3.5 Splitting of test-duties in test series, taking into account the associated
TRV for each pole-to-clear
The procedures as described in 6.102.10.3.5 of IEC 62271-100:2008/AMD2:2017 are
applicable and the test procedure for synthetic testing is given in Annex L.
6.102.10.3.101 Modified procedure in cases where the circuit-breaker did not interrupt
during a test with a medium arcing time, during breaking tests with
symmetrical current
If the circuit-breaker did not interrupt at the expected current zero during a breaking operation
with symmetrical current with a medium arcing time then it is necessary to perform an
additional breaking operation.
The breaking operation shall demonstrate interruption with the "ultimate maximum arcing time”
t which is:
arc ult max
t = t + T × (150 / 360), if k = 1,5
arc ult max arc med pp
t = t + T × (180 / 360), if k = 1,3, 1,2 or 1,0
arc ult max arc med pp
where
t is the medium arcing time at which the circuit-breaker did not interrupt;
arc med
is the ultimate maximum arcing time.
t
arc ult max
If the circuit-breaker does not interrupt during this additional breaking operation, it is
permissible to carry out maintenance work on the circuit-breaker according to 6.102.9.5 of
IEC 62271-100:2008/AMD2:2017 and repeat the test-duty where the breaking operation with
the medium arcing time is replaced by the breaking operation with the ultimate maximum
arcing time.
For test duties T10, T30, T60, L , L and L , the t is demonstrated with (Cd)Os.
90 75 60 arc ult max
For test duty T100s, the t is demonstrated with CdOs.
arc ult max
For OP1 and OP2 test duties, the t is demonstrated with Os.
arc ult max
6.106 Basic short-circuit test-duties
Delete the second paragraph and the list of abbreviations.
– 10 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
6.106.5 Test-duty T100a
Replace the second paragraph of item a) by the following:
Required values of the peak short-circuit current and loop duration shall be in accordance
with the values in Tables L.12 to L.17.
Delete the fourth paragraph from item a) starting with "The required asymmetry level".
Replace the third paragraph of item b) by the following:
The corresponding corrected values can be found in Tables L.12 to L.17.
Replace the last sentence of 1) of item c) by the following:
See Annex I for more guidance.
Replace the last paragraph of 2) of item c) by the following:
Different test circuits for different asymmetry conditions may be needed in order to obtain the
required values. A test with one single test circuit may over-stress the circuit-breaker and
requires the consent of the manufacturer.
Add the following paragraph to item c):
3) u and RRRV for second-pole-to-clear and last-pole-to-clear are obtained from the
c
respective values for symmetrical conditions reduced by the same factor as the
corresponding di/dt.
Add, at the end of the list, the following new item e):
e) Intermediate asymmetry
The phase with the intermediate asymmetry as required for testing T100a according to
6.102.10.2.2 and 6.102.10.3.3 refers to the phase, in a three-phase system, having its
current zero just prior to current zero of the phase with required asymmetry. This phase
also starts with a major loop of current, at current initiation. As an example the red
coloured phase in tests 1 and 2 of Figures 9 and 10 (synthetic test, right hand part of the
figures) fulfils this intermediate asymmetry condition.
In this particular phase, the major loops are called intermediate major loops.
The parameters of the intermediate major loop can be obtained from Tables L.12 to L.17.
6.109 Short-line fault (SLF) tests
Replace the third paragraph by the following:
The final current loop before clearing shall have an amplitude equal to the test current times
+10
√2 with a tolerance of % including the provisions of 4.1.2.
−5
6.111.2 General
Delete the existing title and text.
6.111.3 Characteristics of supply circuits
Replace the second paragraph by the following:
© IEC 2017
The effects of current chopping, as described in G.7, may modify the recovery voltage during
the capacitive current switching tests.
Add, after the second paragraph, the following new paragraph:
A test circuit with a 50 Hz current circuit may be used to prove the capacitive current
switching capability for a rating of 60 Hz, provided that the recovery voltage fulfils the 60 Hz
requirements (see 6.111.3 of IEC 62271-100:2008/AMD2:2017). The setting of the contact
separation should be based on the frequency of the current source.
6.111.7 Test voltage
Replace the existing text by the following:
The prospective recovery voltage during synthetic capacitive current switching tests shall be
calculated based on the test voltage of the corresponding single-phase direct test, as defined
in 6.111.7 of IEC 62271-100:2008/AMD2:2017, and comply with the requirements of 6.111.10
of IEC 62271-100:2008/AMD2:2017.
Due to limitations of some synthetic test circuits the following additional requirements apply to
the recovery voltage:
– The peak value of the a.c. component of the recovery voltage should be kept as close as
possible to k ×U 2 / 3 ;
c r
– The d.c. component of the recovery voltage shall not decay more than 10 % within an
interval of 0,3 s after final arc extinction, except for test duty LC1 and/or CC1;
– The recovery voltage shall not fall below 1,5 × k ×U 2 / 3 within an interval of 0,1 s after
c r
final arc extinction.
Graphical representation is shown in Figure 8.
Examples of synthetic capacitive current switching circuits are given in Annex G.
Figure 2 – Examples of evaluation of recovery voltage
Replace Figure 2 by the following:
– 12 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
IEC
a) Example of a power-frequency recovery voltage
IEC
b) Example of a d.c. steady-state recovery voltage
P1 Point of initial value of (power frequency or d.c. steady-state) recovery voltage,
≥ 0,95 × k ×U ×
pp r
Blue line Tested recovery voltage
Green dotted line Tested power frequency or d.c. steady-state recovery voltage
Figure 2 – Examples of evaluation of initial recovery voltage
© IEC 2017
Figure 5 – Typical synthetic making circuit for single-phase tests
Replace Figure 5 by the following:
IEC
Key
u voltage of current circuit u voltage of voltage circuit
cs vs
CH making device (triggered spark gap) i initial transient making current (ITMC)
h
i i
power-frequency current supplied by current circuit current in the test circuit-breaker
t
S test circuit-breaker t time delay of making device
t m
Figure 5 – Example of synthetic making circuit for single-phase tests
– 14 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
Figure 6 – Typical synthetic making circuit for out-of-phase
Replace Figure 6 by the following:
IEC
Key
u voltage of current circuit u voltage of voltage circuit
cs vs
CH making device (triggered spark gap) i initial transient making current (ITMC)
h
i i
power-frequency current supplied by current circuit current in the test circuit-breaker
t
S test circuit-breaker u test voltage across test circuit-breaker
t t
t time delay of making device
m
Figure 6 – Example of synthetic making circuit for out-of-phase
© IEC 2017
Figure 7 – Typical synthetic make circuit for three-phase tests (k = 1,5)
pp
Replace Figure 7 by the following:
i
h1
CH1
i
i
t1 Voltage circuit 1
u
h1
(AC source)
S
t
i
h2
CH2
Voltage circuit 2
i
i
u
t2
h2
(AC source)
u
cs
Three-phase Voltage circuit 3
u
h3
(AC source)
i
h3
CH3
i
3 i
t3
Current circuit
Voltage circuit
IEC
Key
u , u , u voltage of current circuit u , u , u applied voltage
cs1 cs2 cs3 h1 h2 h3
i , i , i current supplied by the current circuit CH , CH , CH making device (triggered spark
1 2 3 1 2 3
gap)
i , i , i current through the test object S test circuit-breaker
t1 t2 t3 t
, i , i t
i initial transient making current (ITMC) time delay of making device
h1 h2 h3 m
Figure 7 – Example of synthetic making circuit for three-phase tests (k = 1,5)
pp
– 16 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
Figure 8 – Comparison of arcing time settings during three-phase direct tests (left) and
three-phase synthetic (right) for T100s with k = 1,5
pp
Replace Figure 8 by the following:
– 17 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
u
P
P 3 t
P
recovery voltage (a.c. and d.c.)
u
t = 0,1 s
decay of d.c. component within
prospective recovery
0,3 s less than 10 %
voltage peak at T = τ/2
1,98 or 1,95 × k × U 2 / 3
c r
≥ 1,5 × k × U 2 / 3
c r
t
IEC
Key
1 recovery voltage with exponential decrement in the a.c. and d.c. components P point on which the peak of recovery voltage (1) occurs
across the circuit-breaker during a synthetic capacitive current switching test
2 a.c. component of the recovery voltage P
point where the recovery voltage (1) shall not be below 1,5 × k ×U 2 / 3
c r
3 d.c. component of the recovery voltage
P point where the d.c. recovery voltage (3) shall not be below 0,9 × k ×U 2 / 3
c r
cycle of power frequency
τ
Figure 8 – Evaluation of recovery voltage during synthetic capacitive current switching testing
© IEC 2017
Figure 9 – Comparison of arcing time settings during three-phase direct tests (left) and
three-phase synthetic (right) for T100a with k = 1,5
pp
Replace Figure 9 by the following:
t
arc min
t
a100s
t - da
arc min
t
arc 1 t
arc 1
∆t
a1 ∆t
a1
t - da
t - da arc min
a100s
t - da
a100s
t - da
arc min
∆t ∆t
a2 a2
t t
arc 2 arc 2
IEC
Key
1 First test, t
arc min
Second test, t − da, resulting in re-ignition
arc min
3 Condition a) first-pole-to-clear after major loop
4 Condition b) last-pole-to-clear after major extended loop
Figure 9 – Comparison of arcing time settings during three-phase direct tests (left) and
three-phase synthetic tests (right) for T100a with k = 1,5
pp
– 19 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
Add, after the new Figure 9 added by this amendment, the following new Figure 10:
t
arc min
t
a100s
t - da
arc min
t t
arc 1 arc 1
∆t
a1
∆t
a1
t - da
arc min
t - da
a100s
t - da t - da
a100s arc min
∆t ∆t
a3 a3
t
t arc 3
arc 3
IEC
Key
First test, t
arc min
2 Second test, t − da, resulting in re-ignition
arc min
3 Condition a) first-pole-to-clear after major loop
4 Condition b) second-pole-to-clear after major extended loop
Figure 10 – Comparison of arcing time settings during three-phase direct tests (left) and
three-phase synthetic tests (right) for T100a with k = 1,3
pp
© IEC 2017
E.1 General
Replace "Annex C of IEC 62271-100:2008" by "IEC 62271-306".
E.3 Test conditions
Replace item a) by the following:
a) Circuit parameters of the circuits.
E.4.2 Voltages
Add, after item b), the following item:
c) Voltage to enclosure for the test circuit-breaker when applicable.
E.4.3 Currents
Delete the paragraph below item b).
Annex G (informative) Synthetic methods for capacitive-current switching
Replace the entire text of this annex, including figures, by the following:
G.1 General
Synthetic capacitive current switching tests are generally performed using single-phase test
circuits. There are principally two types of circuits:
a) Combined current and voltage circuits
The test circuit consists of a current circuit and a voltage circuit. Both circuits have a
capacitive nature, although an inductive or resistive current circuit can be used as an
alternative, provided that the phase angle between the two sources is changed
accordingly.
The two sources can be power frequency fed transformers or charged capacitors, or a
combination of both. The application of this type of circuit implies the use of an auxiliary
circuit-breaker to isolate the test circuit-breaker from the current circuit.
The time between separation of voltage circuit and current circuit by the auxiliary circuit-
breaker (current zero in the current circuit) and the current zero in the voltage circuit
should not be longer than 500 µs.
b) LC oscillating circuits
The test circuit consists of an LC oscillating circuit that provides both the current and
voltage from a single source. The application of this type of circuit does not require the
use of an auxiliary circuit-breaker.
For applicability of the mentioned methods in case of metal-enclosed or dead tank circuit-
breakers, see Annex N of this document and Annex O of IEC 62271-100:2008/AMD2:2017.
NOTE Phenomena occurring after a restrike or a re-ignition event are not representative of service conditions as
the test circuit does not adequately reproduce the post-event voltage conditions.
Many test circuits are possible with different features. Some examples are given in
Figures G.1 to G.7.
– 21 – IEC 62271-101:2012/AMD1:2017
© IEC 2017
An impedance may be added for protection of the test circuit and/or control of the inrush
current, provided that the prospective recovery voltage is in accordance with 6.111.10 of
IEC 62271-100:2008/AMD2:2017.
G.2 Recovery voltage
In principle, the recovery voltage consists of an a.c. voltage applied to one terminal of the test
circuit-breaker, while a slowly decaying d.c. voltage stresses the other terminal. In some test
circuits both voltages are superimposed at one terminal of the test circuit-breaker, the other
terminal being earthed. This condition is more severe with respect to both the insulation to
earth and across contacts. The combined current and voltage circuits of Figures G.4 and G.5
can be used to apply the correct voltage stresses to each terminal of the circuit-breaker. For
synthetic method the decay of the AC voltage should be kept within limits given in 6.111.7 and
Figure 8.
G.3 Combined current and voltage circuits
When tests are performed using the circuits described in item a) of G.1, the connection of the
current and voltage circuits to the auxiliary and test circuit-breakers can be in parallel mode,
subtracting the voltages on the auxiliary circuit-breaker, or in series mode, and adding the
voltages on the test circuit-breaker.
Depending on whether the voltage circuit is connected permanently or switched in before or
after power-frequency current zero, a distinction can be made between power-frequency
current superposition, current injection and voltage injection circuits.
G.4 Making tests
An example of a test circuit is given in Figure G.7.
The voltage circuit supplies the test voltage during closing of the contacts until dielectric
breakdown occurs causing the initial transient making current to flow.
G.5 Current chopping
Current chopping phenomena, caused by interaction between a circuit-breaker and its circuit
(in service or during laboratory tests), generally leads to a reduction of the load side voltage
and thus also of the dielectric stress applied to the circuit-breaker.
In service or during laboratory tests in direct test circuits, chopping of small capacitive
currents may take place. In synthetic test circuits the probability of these events occurring is
increased for the following reasons:
– generally speaking the characteristic parameters of the main and stray components of
some synthetic test circuits are different and may influence the chopping behaviour of the
circuit-breaker;
– the effect of additional (auxiliary) circuit-breakers in series with the test circuit-breaker in
combined current and voltage circuits;
– the increased ratio of arc voltage to power-frequency voltage.
Therefore, when performing synthetic tests using test circuits described in item a) of G.1, it
may be difficult to determine whether or not current chopping is a significant feature of the
test circuit-breaker. To reduce current chopping, the following measures can be taken:
– modify the capacitances seen from the circuit-breaker terminals;
© IEC 2017
– use an auxiliary circuit-breaker with a short minimum arc duration and low arc voltage in
combined current and voltage circuits.
Some synthetic test circuits are less-sensitive to current chopping, and therefore, may provide
a recovery voltage for long arcing times where it would be reduced in a direct circuit.
G.6 Examples test circuits
Figures G.1 to G.7 show some examples of synthetic test circuits for capacitive current
switching. The following list of symbol explanations relates to these figures, as appropriate,
and are listed here for the sake of brevity and to avoid repetition.
The equations presented for the given circuits are meant for guidance only. They do not take
into account losses or other phenomena in the test circuits.
C = capacitance of the current circuit
c
C , C = capacitances of the voltage circuit B
hB B
C = capacitance of the voltage circuit
v
C , L = power frequency oscillation circuit
h pf
f = frequency of the inrush current
inrush
f = frequency of the
...
Questions, Comments and Discussion
Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.
Loading comments...