IEC 62026-6:2001

Low-voltage switchgear and controlgear - Controller-device interfaces (CDIs) - Part 6: Seriplex (Serial Multiplexed Control Bus)

Specifies an interface system between single or multiple controllers, and control circuit devices or switching elements. The interface system uses two twisted conductor pairs within one cable - one of these pairs provides a communication medium and the other pair provides power to the devices. It also establishes requirements for the interchangeability of components with such interfaces. This standard specifies the physical and operating characteristics of the Seriplex controller-device interface.

General Information

• Status: Withdrawn
• Publication Date: 27-Nov-2001
• Withdrawal Date: 26-Apr-2006
• ICS: 29.130.20 - Low voltage switchgear and controlgear
• Technical Committee: SC 121A - Low-voltage switchgear and controlgear
• Drafting Committee: WG 3 - TC 121/SC 121A/WG 3
• Current Stage: WPUB - Publication withdrawn
• Completion Date: 20-Jan-2006

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD
62026-6
First edition
2001-11
Low-voltage switchgear and controlgear –
Controller-device interfaces (CDIs) –
Part 6:
Seriplex (Serial Multiplexed Control Bus)
Appareillage à basse tension –
Interfaces appareil de commande-appareil (CDI) –
Partie 6:
Seriplex (Serial Multiplexed Control Bus)

Reference number
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edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the
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INTERNATIONAL IEC
STANDARD
62026-6
First edition
2001-11
Low-voltage switchgear and controlgear –
Controller-device interfaces (CDIs) –
Part 6:
Seriplex (Serial Multiplexed Control Bus)
Appareillage à basse tension –
Interfaces appareil de commande-appareil (CDI) –
Partie 6:
Seriplex (Serial Multiplexed Control Bus)

 IEC 2001  Copyright - all rights reserved
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– 2 – 62026-6  IEC:2001(E)
CONTENTS
FOREWORD.4

INTRODUCTION.5

1 Scope.7

2 Normative references .7

3 Definitions, symbols and abbreviations .8

3.1 Definitions .8
3.2 Symbols and abbreviations.13
4 Classification.14
4.1 General .14
4.2 Frame period, t .15
f
4.3 Signal update time, t
............................................................................................15
u
4.4 Input response time, t .16
ir
4.5 Output response time, t .17
or
4.6 System response time, t .18
sr
5 Characteristics .19
5.1 System overview .19
5.2 Frequency, cable length and node count .23
5.3 Data transmission.24
5.4 General data transmission features .26
5.5 Signal timing .31
5.6 Data definitions .33
5.7 Signal addressing conventions .38
5.8 Operational characteristics .39
5.9 Fault responses.43
5.10 Device programming .48
6 Product information .48
7 Normal service, mounting and transport conditions.48
7.1 General .48
7.2 Ambient air temperature .48

7.3 Humidity.49
7.4 Conditions during transport and storage .49
7.5 Mounting .49
7.6 Shock.49
7.7 Vibration.49
8 Constructional and performance requirements.49
8.1 Seriplex power supply .49
8.2 Power distribution.50
8.3 Isolation .50
8.4 Data line characteristics .51
8.5 Clock line characteristics.52
8.6 Seriplex cable topology .54
8.7 Cable specifications .55
8.8 Electromagnetic compatibility .57

62026-6  IEC:2001(E) – 3 –
9 Tests .59

9.1 Supply polarity .59

9.2 Power supply.59

9.3 Clock source .60

9.4 I/O device.70

9.5 Seriplex cable .81

Figure 1 − Seriplex controller-device interface system diagram .20

Figure 2 − Peer-to-peer timing diagram.21
Figure 3 − Master/slave timing diagram.22
Figure 4 − Example of address multiplexing .22
Figure 5 − Peer-to-peer transmission format .24
Figure 6 − Master/slave mode data transmission format.26
Figure 7 − Sync period diagram .28
Figure 8 − Data signal timing diagram.32
Figure 9 − Check byte formation .37
Figure 10 − Bus Fault Detection pulse .40
Figure 11 − Digital debounce .42
Figure 12 − Data line diagram .51
Figure 13 − Hysteresis .52
Figure 14 − Clock line diagram .53
Figure 15 − Preferred Seriplex topologies .54
Figure 16 − Other controller-device interface topologies .54
Figure 17 − Four-conductor Seriplex cable.56
Figure 18 − Six-conductor Seriplex cable .57
Figure 19 − Circuit for verification of clock source power consumption.60
Figure 20 − Connections for clock signal tests .61
Figure 21 − Clock signal waveform .61
Figure 22 − Test circuit for clock signal.63
Figure 23 − Waveform of clock pulse .64

Figure 24 − Transient current.64
Figure 25 − Test circuit for CDI data signal .65
Figure 26 − Waveform for CDI data signal.65
Figure 27 − Data line waveforms.67
Figure 28 − Connections for verification of data line requirements .68
Figure 29 − Waveforms for verification of data line requirements .68
Figure 30 − Connections for verification of I/O device requirements .71
Figure 31 − Connections for verification of I/O device data line capacitance (a) .71
Figure 32 − Connections for measurement of I/O device data line capacitance (b) .71
Figure 33 − Measurement of I/O device data line capacitance.72
Figure 34 − Connections for measurement of I/O device voltage drop .73

– 4 – 62026-6  IEC:2001(E)
Figure 35 − Connections for measurement of output device lower voltage threshold .73

Figure 36 − Connections for measurement of output device upper voltage threshold.74

Figure 37 − Connections for measurement of input device lower voltage threshold .76

Figure 38 − Connections for measurement of input device upper voltage threshold.76

Table 1 − Maximum available clock frequency for valid networks (single power supply) .23

Table 2 − Maximum available clock frequency for valid networks (multiple power supplies).24

Table 3 − Sync period parameters .28

Table 4 − Symbols and parameters.32
Table 5 − CDR signal address assignments .35
Table 6 − Address codes .36
Table 7 − Channel codes .37
Table 8 − I/O direction codes .
...