IEC 62433-2:2008

EMC IC modelling - Part 2: Models of integrated circuits for EMI behavioural simulation - Conducted emissions modelling (ICEM-CE)

IEC 62433-2:2008 specifies macro-models for ICs to simulate conducted electromagnetic emissions on a printed circuit board. The model is commonly called Integrated Circuit Emission Model - Conducted Emission (ICEM-CE). The ICEM-CE model can also be used for modelling an IC-die, a functional block and an Intellectual Property block (IP). The ICEM-CE model can be used to model both digital and analogue ICs. Basically, conducted emissions have two origins:
- conducted emissions through power supply terminals and ground reference structures;
- conducted emissions through input/output (I/O) terminals. The ICEM-CE model addresses those two types of origins in a single approach. This standard defines structures and components of the macro-model for EMI simulation taking into account the IC's internal activities. This standard gives general data, which can be implemented in different formats or languages such as IBIS, IMIC, SPICE, VHDL-AMS and Verilog. SPICE is however chosen as default simulation environment to cover all the conducted emissions. This standard also specifies requirements for information that shall be incorporated in each ICEM-CE model or component part of the model for model circulation, but description syntax is not within the scope of this standard.

Modèles de circuits intégrés pour la CEM - Partie 2: Modèles de circuits intégrés pour la simulation du comportement lors de perturbations électromagnétiques - Modélisation des émissions conduites (ICEM-CE)

La CEI 62433-2:2008 définit des macromodèles pour circuits intégrés, destinés à simuler les émissions électromagnétiques conduites sur une carte de circuit imprimé. On appelle habituellement ce modèle: Modèle des émissions de circuits intégrés - Émission conduite (ICEM-CE). Le modèle ICEM-CE peut également être utilisé pour modéliser une puce de circuit intégré, un bloc fonctionnel et un bloc à propriété intellectuelle (IP). Le modèle ICEM-CE peut être utilisé pour modéliser à la fois des circuits intégrés numériques et analogiques. Les émissions conduites ont fondamentalement deux origines:
- les émissions conduites par l'intermédiaire des bornes d'alimentation et des structures de référence de masse;
- les émissions conduites par l'intermédiaire des bornes d'entrée/sortie (E/S). Le modèle ICEM-CE traite ces deux types d'origine en une approche unique. La présente norme définit les structures et les composants du macromodèle pour la simulation des perturbations électromagnétiques en tenant compte des activités internes du circuit intégré. La présente norme fournit des données générales, pouvant être mises en oeuvre dans des formats ou des langages différents tels que: IBIS, IMIC, SPICE, VHDL-AMS et Verilog. On choisit toutefois SPICE comme environnement de simulation par défaut pour couvrir la totalité des émissions conduites. La présente norme spécifie également les exigences relatives aux informations qui doivent être incorporées dans chaque modèle ICEM-CE ou élément constituant du modèle pour la circulation du modèle. La syntaxe de la description ne fait toutefois pas partie du domaine d'application de la présente norme.

General Information

• Status: Published
• Publication Date: 07-Oct-2008
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 2 - TC 47/SC 47A/WG 2
• Current Stage: DELPUB - Deleted Publication
• Completion Date: 27-Jan-2017

Relations

• Revised: IEC 62433-2:2017 - EMC IC modelling - Part 2: Models of integrated circuits for EMI behavioural simulation - Conducted emissions modelling (ICEM-CE)
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 62433-2
Edition 1.0 2008-10
INTERNATIONAL
STANDARD


EMC IC modelling –
Part 2: Models of integrated circuits for EMI behavioural simulation – Conducted
emissions modelling (ICEM-CE)



IEC 62433-2:2008(E)

---------------------- Page: 1 ----------------------
THIS PUBLICATION IS COPYRIGHT PROTECTED
Copyright © 2008 IEC, Geneva, Switzerland

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
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---------------------- Page: 2 ----------------------
IEC 62433-2
Edition 1.0 2008-10
INTERNATIONAL
STANDARD


EMC IC modelling –
Part 2: Models of integrated circuits for EMI behavioural simulation – Conducted
emissions modelling (ICEM-CE)


INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
X
ICS 31.200 ISBN 978-2-88910-702-5
® Registered trademark of the International Electrotechnical Commission

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– 2 – 62433-2 © IEC:2008(E)
CONTENTS
FOREWORD.5
1 Scope.7
2 Normative references .7
3 Terms and definitions .7
4 Philosophy .8
4.1 General .8
4.2 Conducted emission from core activity (digital culprit) .8
4.3 Conducted emission from I/O activity.9
5 Basic components .9
5.1 General .9
5.2 Internal Activity (IA).9
5.3 Passive Distribution Network (PDN) .10
6 IC macro-models .12
6.1 General .12
6.2 General IC macro-model .12
6.3 Block-based IC macro-model.13
6.3.1 Block component .13
6.3.2 Inter-Block Coupling component (IBC) .14
6.3.3 Block-based IC macro-model structure .15
6.4 Sub-model-based IC macro-model .17
6.4.1 Sub-model component.17
6.4.2 Sub-model-based IC macro-model structure .18
7 Requirements for parameter extraction.19
7.1 General .19
7.2 Environmental extraction constraints .19
7.3 IA parameter extraction .19
7.4 PDN parameter extraction .19
7.5 IBC parameter extraction.19
Annex A (informative) Model parameter generation.20
Annex B (informative) Decoupling capacitors optimization .38
Annex C (informative) Conducted emission prediction.40
Annex D (informative) Conducted emission prediction at PCB level .41
Bibliography.43

Figure 1 – Decomposition example of a digital IC for conducted emissions analysis .8
Figure 2 – IA component.9
Figure 3 − Example of IA characteristics in time domain .10
Figure 4 − Example of IA characteristics in frequency domain.10
Figure 5 − Example of a four-terminal PDN using lumped elements .11
Figure 6 − Example of a seven-terminal PDN using distributed elements .11
Figure 7 − Example of a twelve-terminal PDN using matrix representation .12
Figure 8 – General IC macro-model .13
Figure 9 – Example of block component.13
Figure 10 – Example of block components for I/Os .14

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62433-2 © IEC:2008(E) – 3 –
Figure 11 – Example of IBC with two internal terminals.15
Figure 12 – Relationship between blocks and IBC.15
Figure 13 – Block-based IC macro-model.16
Figure 14 – Example of block-based IC macro-model.17
Figure 15 – Example of simple sub-model.18
Figure 16 – Sub-model-based IC macro-model .18
Figure A.1 – Typical characterization current gate schematic.22
Figure A.2 – Current peak during switching transition .22
Figure A.3 – Example of IA extraction procedure from design .23
Figure A.4 – Technology Influence.23
Figure A.5 – Final current waveform for a program period.24
Figure A.6 – Comparison between measurement and simulation.24
Figure A.7 – Lumped element model of a package.25
Figure A.8 – Circuit structure of the netlist .26
Figure A.9 – Principle of the IA computation .27
Figure A.10 – Process involved to model i (t) .27
A
Figure A.11 – i (t) measured using IEC 61967-4.28
Ext
Figure A.12 – i (t)and i (t) profiles .28
A Ext
Figure A.13 – Example of a hardware set-up used to extract the PDN parameters .30
Figure A.14 – Miniature 50 Ω coaxial connectors .30
Figure A.15 – Impedance probe using two miniature coaxial connectors .31
Figure A.16 – Open and short terminations .31
Figure A.17 – Measurement probe model.31
Figure A.18 – De-embedding principle .32
Figure A.19 – Example of a predefined PDN structure .33
Figure A.20 – RL configuration .34
Figure A.21 – RLC configuration .34
Figure A.22 – RLC with magnetic coupling configuration.35
Figure A.23 – Impedance seen from Vcc and Gnd .35
Figure A.24 – Complete PDN component .36
Figure A.25 – Set-up for correlation (left), measurement and prediction (right).37
Figure A.26 – Set-up used to measure the internal decoupling capacitor .37
Figure B.1 – Equivalent schematic of the complete electronic system .38
Figure B.2 – Impedance prediction and measurements .39
Figure C.1 – IEC 61967-4 test set-up standard .40
Figure C.2 – Comparison between prediction and measurement .40
Figure D.1 – Prediction of the Vdcc noise level at PCB level.41
Figure D.2 – Good agreements on the noise envelope .42

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Table A.1 – Typical parameters for CMOS logic technologies .20
Table A.2 – Typical number of logic gates vs. CPU technology .21
Table A.3 – R, L and C parameters for various package types .21
Table A.4 – Measurement configurations and extracted RLC parameters.33

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62433-2 © IEC:2008(E) – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

EMC IC MODELLING –

Part 2: Models of integrated circuits for EMI behavioural simulation –
Conducted emissions modelling (ICEM-CE)


FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62433-2 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47A/794/FDIS 47A/799/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 62433 series, under the general title EMC IC modelling, can
be found on the IEC website.

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– 6 – 62433-2 © IEC:2008(E)
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.

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62433-2 © IEC:2008(E) – 7 –
EMC IC MODELLING –

Part 2: Models of integrated circuits for EMI behavioural simulation –
Conducted emissions modelling (ICEM-CE)



1 Scope
This part of IEC 62433 specifies macro-models for ICs to simulate conducted electromagnetic
emissions on a printed circuit board. The model is commonly called Integrated Circuit
Emission Model - Conducted Emission (ICEM-CE).
The ICEM-CE model can also be used for modelling an IC-die, a functional block and an
Intellectual Property block (IP).
The ICEM-CE model can be used to model both digital and analogue ICs.
Basically, conducted emissions have two origins:
• conducted emissions through power supply terminals and ground reference structures;
• conducted emissions through input/output (I/O) terminals.
The ICEM-CE model addresses those two types of origins in a single approach.
This standard defines structures and components of the macro-model for EMI simulation
taking into account the IC’s internal activities.
This standard gives general data, which can be implemented in different formats or languages
such as IBIS, IMIC, SPICE, VHDL-AMS and Verilog. SPICE is however chosen as default
simulation environment to cover all the conducted emissions.
This standard also specifies requirements for information that shall be incorporated in each
ICEM-CE model or component part of the model for model circulation, but description syntax
is not within the scope of this standard.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 61967 (all parts), Integrated Circuits – Measurement of electromagnetic emissions, 150
KHz to 1 GHz
IEC 61967-4, Integrated circuits – Measurement of electromagnetic emissions, 150 kHz to 1
GHz – Part 4: Measurement of conducted emissions – 1 Ω/150 Ω direct coupling method
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

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– 8 – 62433-2 © IEC:2008(E)
3.1
external terminal
terminal of an IC macro-model, which interfaces the model to the external environment of the
IC, such as power supply pins and I/O pins
NOTE In this document, the name of each external terminal starts with "ET".
3.2
internal terminal
terminal of an IC macro-model's component, which interfaces the component to other
components of the IC macro-model
NOTE In this document, the name of each internal terminal starts with "IT".
4 Philosophy
4.1 General
Integrated circuits will have more and more gates on silicon and technical progress will
develop faster. To predict the electromagnetic behaviour of equipment, it is required to model
the switching of the input and output interface and the internal activities of an integrated
circuit effectively.
Figure 1 depicts an example of decomposition of an IC to enable conducted emissions
analysis. The internal digital activity (culprit) is a source of electromagnetic noise that
originates in switching of active devices. The coupling path propagates the emissions to the
IC’s external terminals: pins/pads. The coupling path is the power distribution network or I/O
lines inside the IC.
Power Distribution
Network
Vdd Vss Vdd Vss
Digital Culprit
Digital Coupling I/Os' Coupling I/Os' Culprit
(Emission
path path (Emission Source)
Source)
IC
Inter Block Coupling Path
I/O
IEC  1644/08

Figure 1 – Decomposition example of a digital IC for conducted emissions analysis
4.2 Conducted emission from core activity (digital culprit)
The current transients are created in the core area on the IC-die. Due to the characteristics of
the digital coupling paths, the passive distribution network on printed circuit board (PCB) and
the availability of on-chip decoupling, a portion of these current transients will occur at the
power supply pins of the IC.

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62433-2 © IEC:2008(E) – 9 –
NOTE These off-chip power supply currents can be measured according to the IEC 61967 series.
4.3 Conducted emission from I/O activity
I/Os activities may create voltage fluctuations of power and ground levels, and conducted
emissions appear at power and ground pins through the I/Os' coupling path. And the output
signals at output pins themselves are sources of conducted emissions to the printed circuit
boards.
NOTE The measurement set-up is done according to the IEC 61967 series.
5 Basic components
5.1 General
The basic components are component parts of the IC macro-model or block component or
sub-model component. The following subclauses define the basic components.
NOTE The block component and the sub-model component are defined in Subclause 6.3.1 and 6.4.1 respectively.
5.2 Internal Activity (IA)
The Internal Activity (IA) component is the electromagnetic noise source that originates in
switching of active devices in the IC or in a portion of the IC. This component is applicable for
both analogue and digital circuitry.
The IA is described using an independent current source or an independent voltage source
with two internal terminals as shown in Figure 2.
ITITAA--[[00]]
ITITAA++[[00]]

IEC  1645/08
Figure 2 – IA component
The characteristics of IA component are typically described in the time domain, and the
characteristics can also be described in the frequency domain.
The description of an IA component shall contain the following information.
• Name of the IA component
• Names of its internal terminals
• Operational mode or test vector
• Domain (time or frequency)
• Definition of origin of time, and cycle-time for the operational mode (for time domain)
• Definition of origin of phase (for frequency domain)
• Operational conditions and applicable ranges
a) Power supply voltage ranges
b) Temperature range

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– 10 – 62433-2 © IEC:2008(E)
c) Frequency range
• Characteristics of the IA
a) Current or voltage waveform over the whole cycle-time (for time domain)
b) Current or voltage amplitude and phase, versus frequency over the whole frequency
range (for frequency domain)
EXAMPLE 1
Figure 3 shows an example of characteristics of IA in the time domain. The waveform
depends on the specific operational mode of function. A simple waveform such as a triangular
waveform can be used for the component description.
i (A)
time (s)
IEC  1646/08

Figure 3 − Example of IA characteristics in the time domain
EXAMPLE 2
Figure 4 shows an example of characteristics of IA in the frequency domain.
I (dBµA)
f (Hz)

IEC  1647/08
Figure 4 − Example of IA characteristics in the frequency domain
5.3 Passive Distribution Network (PDN)
The Passive Distribution Network component (PDN) presents the characteristics of
propagation path of electromagnetic noises such as power distribution network (part of the
PDN). The PDN can be linear or non-linear.

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62433-2 © IEC:2008(E) – 11 –
The PDN consists of passive elements, and is equipped with internal terminals. And the PDN
can have external terminals.
The PDN can be described using a netlist. In the case the PDN can be assumed to be linear,
some matrix formats such as the S-parameter can also present the PDN characteristics.
The description of a PDN component shall contain the following information.
• Name of the PDN component
• Names of its internal terminals and external terminals
• Applicable ranges
a) Power supply voltage range
b) Temperature range
c) Applicable load conditions if the PDN is for output
d) Applicable frequency range
• Characteristics of the PDN
EXAMPLE 1
Figure 5 shows an example of a four-terminal PDN using lumped elements. The ETVdd and
ETVss are two external terminals of the PDN. The IT[1] and the IT[0] are two internal
terminals.
ITIT[[11]] ITIT[[00]]
PDPDNN
ETETVVdddd ETETVVssss

IEC  1648/08
Figure 5 − Example of a four-terminal PDN using lumped elements
EXAMPLE 2
Figure 6 depicts the seven-terminal PDN structure using distributed elements such as
transmission lines. The ETVxx are the four external terminals, the ITVxx are two internal
terminals and the ETGnd is the common ground of the four transmission lines, connected to
the PCB ground.
PDPDNN
EETTVVdd[dd[00]] IITTVVdd[dd[0]0]
IITTVVss[ss[00]]
EETTVVss[ss[00]]
EETTVVdd[dd[11]]
EETTVVss[ss[11]]
ETETGGnndd

IEC  1649/08
Figure 6 − Example of a seven-terminal PDN using distributed elements

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– 12 – 62433-2 © IEC:2008(E)
EXAMPLE 3
Figure 7 shows an example of a twelve-terminal PDN using scattering parameters in a matrix
format (black box). The ET[x] are external terminals. The IT[1] to IT[6] are internal terminals.
A ground plane below the modelled IC is taken as an ideal reference ground for these
terminals.
ETET[[11]]
IT[IT[11]]
S1S111 -- -- -- -- SS1 121 12
ETET[[22]]
IT[IT[22]]
---- --------
---- --------
ETET[[33]]
IT[IT[33]]
ETET[[44]] ---- --------
IT[IT[44]]
---- --------
ETET[[55]]
IT[IT[55]]
SS12 112 1 -- -- -- -- SS12 1212 12
ETET[[66]]
IT[IT[66]]

IEC  1650/08
Figure 7 − Example of a twelve-terminal PDN using matrix representation
6 IC macro-models
6.1 General
An IC is modelled as an IC macro-model. Three types of IC macro-models, general model,
block-based model and sub-model-based model, are possible. These IC macro-models are
defined in this subclause.
The description of an IC macro-model shall contain the following information for model
circulation.
• Name of the IC macro-model
• Type of the model, general model or block-based model or sub-model-based model
• Names of components that are included in the IC macro-model
• Names of its external terminals
• Connections of the internal terminals of its components
6.2 General IC macro-model
The general model consists of a single PDN and one or more IAs as shown in Figure 8. The
PDN shall include both the whole PDN on the IC die(s) and the whole PDN of the package. An
on-chip decoupling capacitor shall also be included in the PDN if it exists.
NOTE This structure is suitable for the model circulation to IC users because of the least disclosure of proprietary
information of the IC vendor.

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62433-2 © IEC:2008(E) – 13 –
IICC m modelodel
IAIA
IAIA IAIA
IT[6IT[6]] IITT[[77]] IT[8IT[8]] IIT[T[99]] IITT[1[100]] IT[1IT[111]]
IT[0IT[0]] IITT[[11]] IT[2IT[2]] IIT[T[33]] ITIT[4[4]] IIT[5T[5]]
PDPDNN
ET[ET[00]] ETET[1][1]
ET[4]ET[4] EET[T[5]5] ETET[[88]] ETET[[99]]
ET[ET[22]] EETT[[3]3]
ETET[[66]] EETT[[77]]
ETET[[110]0] ETET[[11]11] ETET[14][14] ET[ET[115]5]
ET[ET[118]8] EETT[[119]9]
ETET[12][12] ETET[13][13]
ET[ET[116]6] ET[ET[117]7]
PPDN ofDN of P PCCB B ((outout of of t thhe e scope)scope)

IEC  1651/08

Figure 8 – General IC macro-model
6.3 Block-based IC macro-model
6.3.1 Block component
The block component represents EMC properties of a specific functional block of IC such as
embedded memory.
The block component consists of a single PDN and one or more IAs. The PDN includes PDN
of the specific functional block, a portion of global power/ground network and a portion of
package PDN, which are directly involved into the block's functionality. The on-chip
decoupling capacitor is a part of the PDN. The component is equipped with external terminals
and internal terminals.
The description of a block component shall include the following information.
• Name of the block component
• Names of the basic components that make up the block component
• Connections of the internal terminals of its basic components
EXAMPLE 1
Figure 9 shows an example of block component. The block consists of an IA and a PDN. The
internal terminals of the IA are connected to the internal terminals of the PDN.
PDPDPDPDNNNN E E E Exxxxamamamampppplllleeee
ITITITIT[[[[1111]]]] ITITITIT[[[[3333]]]]
IAIAIAIA E E E Exxxxaaaammmmpppplelelele
ETETETET[[[[1111]]]] ITITITIT[[[[1111]]]]
ITITITIT[3[3[3[3]]]]
RVRVRVRVdddddddd
LVLVLVLVdddddddd
PDPD
...

IEC 62433-2
®

Edition 1.0 2008-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside


EMC IC modelling –
Part 2: Models of integrated circuits for EMI behavioural simulation – Conducted
emissions modelling (ICEM-CE)

Modèles de circuits intégrés pour la CEM –
Partie 2: Modèles de circuits intégrés pour la simulation du comportement lors
de perturbations électromagnétiques – Modélisation des émissions conduites
(ICEM-CE)

IEC 62433-2:2008

---------------------- Page: 1 ----------------------
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Copyright © 2008 IEC, Geneva, Switzerland

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
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The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.

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---------------------- Page: 2 ----------------------
IEC 62433-2

®


Edition 1.0 2008-10




INTERNATIONAL



STANDARD




NORME



INTERNATIONALE
colour

inside










EMC IC modelling –

Part 2: Models of integrated circuits for EMI behavioural simulation – Conducted

emissions modelling (ICEM-CE)




Modèles de circuits intégrés pour la CEM –

Partie 2: Modèles de circuits intégrés pour la simulation du comportement lors


de perturbations électromagnétiques – Modélisation des émissions conduites

(ICEM-CE)












INTERNATIONAL

ELECTROTECHNICAL

COMMISSION


COMMISSION

ELECTROTECHNIQUE

PRICE CODE
INTERNATIONALE

CODE PRIX X


ICS 31.200 ISBN 978-2-83220-593-8



Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

---------------------- Page: 3 ----------------------
– 2 – 62433-2  IEC:2008
CONTENTS
FOREWORD. 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Philosophy . 8
4.1 General . 8
4.2 Conducted emission from core activity (digital culprit) . 8
4.3 Conducted emission from I/O activity . 9
5 Basic components . 9
5.1 General . 9
5.2 Internal Activity (IA) . 9
5.3 Passive Distribution Network (PDN) . 10
6 IC macro-models . 12
6.1 General . 12
6.2 General IC macro-model . 12
6.3 Block-based IC macro-model . 13
6.3.1 Block component . 13
6.3.2 Inter-Block Coupling component (IBC) . 14
6.3.3 Block-based IC macro-model structure . 15
6.4 Sub-model-based IC macro-model . 17
6.4.1 Sub-model component . 17
6.4.2 Sub-model-based IC macro-model structure . 18
7 Requirements for parameter extraction . 19
7.1 General . 19
7.2 Environmental extraction constraints . 19
7.3 IA parameter extraction . 19
7.4 PDN parameter extraction . 19
7.5 IBC parameter extraction . 19
Annex A (informative) Model parameter generation . 20
Annex B (informative) Decoupling capacitors optimization . 38
Annex C (informative) Conducted emission prediction . 40
Annex D (informative) Conducted emission prediction at PCB level . 41
Bibliography . . 43

Figure 1 – Decomposition example of a digital IC for conducted emissions analysis . 8
Figure 2 – IA component . 9
Figure 3  Example of IA characteristics in time domain . 10
Figure 4  Example of IA characteristics in frequency domain . 10
Figure 5  Example of a four-terminal PDN using lumped elements . 11
Figure 6  Example of a seven-terminal PDN using distributed elements . 11
Figure 7  Example of a twelve-terminal PDN using matrix representation . 12
Figure 8 – General IC macro-model . 13
Figure 9 – Example of block component . 13
Figure 10 – Example of block components for I/Os . 14

---------------------- Page: 4 ----------------------
62433-2  IEC:2008 – 3 –
Figure 11 – Example of IBC with two internal terminals . 15
Figure 12 – Relationship between blocks and IBC . 15
Figure 13 – Block-based IC macro-model . 16
Figure 14 – Example of block-based IC macro-model . 17
Figure 15 – Example of simple sub-model . 18
Figure 16 – Sub-model-based IC macro-model . 18
Figure A.1 – Typical characterization current gate schematic . 22
Figure A.2 – Current peak during switching transition . 22
Figure A.3 – Example of IA extraction procedure from design . 23
Figure A.4 – Technology Influence . 23
Figure A.5 – Final current waveform for a program period . 24
Figure A.6 – Comparison between measurement and simulation . 24
Figure A.7 – Lumped element model of a package . 25
Figure A.8 – Circuit structure of the netlist . 26
Figure A.9 – Principle of the IA computation . 27
Figure A.10 – Process involved to model i (t) . 27
A
Figure A.11 – i (t) measured using IEC 61967-4 . 28
Ext
Figure A.12 – i (t)and i (t) profiles . 28
A Ext
Figure A.13 – Example of a hardware set-up used to extract the PDN parameters . 30
Figure A.14 – Miniature 50 Ω coaxial connectors . 30
Figure A.15 – Impedance probe using two miniature coaxial connectors . 31
Figure A.16 – Open and short terminations . 31
Figure A.17 – Measurement probe model . 31
Figure A.18 – De-embedding principle . 32
Figure A.19 – Example of a predefined PDN structure . 33
Figure A.20 – RL configuration . 34
Figure A.21 – RLC configuration . 34
Figure A.22 – RLC with magnetic coupling configuration . 35
Figure A.23 – Impedance seen from Vcc and Gnd . 35
Figure A.24 – Complete PDN component . 36
Figure A.25 – Set-up for correlation (left), measurement and prediction (right) . 37
Figure A.26 – Set-up used to measure the internal decoupling capacitor . 37
Figure B.1 – Equivalent schematic of the complete electronic system . 38
Figure B.2 – Impedance prediction and measurements . 39
Figure C.1 – IEC 61967-4 test set-up standard . 40
Figure C.2 – Comparison between prediction and measurement . 40
Figure D.1 – Prediction of the Vdcc noise level at PCB level . 41
Figure D.2 – Good agreements on the noise envelope . 42

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– 4 – 62433-2  IEC:2008

Table A.1 – Typical parameters for CMOS logic technologies . 20
Table A.2 – Typical number of logic gates vs. CPU technology . 21
Table A.3 – R, L and C parameters for various package types . 21
Table A.4 – Measurement configurations and extracted RLC parameters . 33

---------------------- Page: 6 ----------------------
62433-2  IEC:2008 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

EMC IC MODELLING –

Part 2: Models of integrated circuits for EMI behavioural simulation –
Conducted emissions modelling (ICEM-CE)


FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
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with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
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4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62433-2 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
This bilingual version (2013-01) corresponds to the monolingual English version, published in
2008-10.
The text of this standard is based on the following documents:
FDIS Report on voting
47A/794/FDIS 47A/799/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The French version of this standard has not been voted upon.

---------------------- Page: 7 ----------------------
– 6 – 62433-2  IEC:2008
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 62433 series, under the general title EMC IC modelling, can
be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The “colour inside” logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this publication using a colour printer.

---------------------- Page: 8 ----------------------
62433-2  IEC:2008 – 7 –
EMC IC MODELLING –

Part 2: Models of integrated circuits for EMI behavioural simulation –
Conducted emissions modelling (ICEM-CE)



1 Scope
This part of IEC 62433 specifies macro-models for ICs to simulate conducted electromagnetic
emissions on a printed circuit board. The model is commonly called Integrated Circuit
Emission Model - Conducted Emission (ICEM-CE).
The ICEM-CE model can also be used for modelling an IC-die, a functional block and an
Intellectual Property block (IP).
The ICEM-CE model can be used to model both digital and analogue ICs.
Basically, conducted emissions have two origins:
 conducted emissions through power supply terminals and ground reference structures;
 conducted emissions through input/output (I/O) terminals.
The ICEM-CE model addresses those two types of origins in a single approach.
This standard defines structures and components of the macro-model for EMI simulation
taking into account the IC’s internal activities.
This standard gives general data, which can be implemented in different formats or languages
such as IBIS, IMIC, SPICE, VHDL-AMS and Verilog. SPICE is however chosen as default
simulation environment to cover all the conducted emissions.
This standard also specifies requirements for information that shall be incorporated in each
ICEM-CE model or component part of the model for model circulation, but description syntax
is not within the scope of this standard.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 61967 (all parts), Integrated Circuits – Measurement of electromagnetic emissions, 150
KHz to 1 GHz
IEC 61967-4, Integrated circuits – Measurement of electromagnetic emissions, 150 kHz to 1
GHz – Part 4: Measurement of conducted emissions – 1 Ω/150 Ω direct coupling method
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

---------------------- Page: 9 ----------------------
– 8 – 62433-2  IEC:2008
3.1
external terminal
terminal of an IC macro-model, which interfaces the model to the external environment of the
IC, such as power supply pins and I/O pins
NOTE In this document, the name of each external terminal starts with "ET".
3.2
internal terminal
terminal of an IC macro-model's component, which interfaces the component to other
components of the IC macro-model
NOTE In this document, the name of each internal terminal starts with "IT".
4 Philosophy
4.1 General
Integrated circuits will have more and more gates on silicon and technical progress will
develop faster. To predict the electromagnetic behaviour of equipment, it is required to model
the switching of the input and output interface and the internal activities of an integrated
circuit effectively.
Figure 1 depicts an example of decomposition of an IC to enable conducted emissions
analysis. The internal digital activity (culprit) is a source of electromagnetic noise that
originates in switching of active devices. The coupling path propagates the emissions to the
IC’s external terminals: pins/pads. The coupling path is the power distribution network or I/O
lines inside the IC.
Power Distribution
Network
Vss
Vdd Vss Vdd
Digital Culprit
Digital Coupling I/Os' Coupling I/Os' Culprit
(Emission
path path (Emission Source)
Source)
IC
Inter Block Coupling Path
I/O
IEC  1644/08

Figure 1 – Decomposition example of a digital IC for conducted emissions analysis
4.2 Conducted emission from core activity (digital culprit)
The current transients are created in the core area on the IC-die. Due to the characteristics of
the digital coupling paths, the passive distribution network on printed circuit board (PCB) and
the availability of on-chip decoupling, a portion of these current transients will occur at the
power supply pins of the IC.

---------------------- Page: 10 ----------------------
62433-2  IEC:2008 – 9 –
NOTE These off-chip power supply currents can be measured according to the IEC 61967 series.
4.3 Conducted emission from I/O activity
I/Os activities may create voltage fluctuations of power and ground levels, and conducted
emissions appear at power and ground pins through the I/Os' coupling path. And the output
signals at output pins themselves are sources of conducted emissions to the printed circuit
boards.
NOTE The measurement set-up is done according to the IEC 61967 series.
5 Basic components
5.1 General
The basic components are component parts of the IC macro-model or block component or
sub-model component. The following subclauses define the basic components.
NOTE The block component and the sub-model component are defined in 6.3.1 and 6.4.1 respectively.
5.2 Internal Activity (IA)
The Internal Activity (IA) component is the electromagnetic noise source that originates in
switching of active devices in the IC or in a portion of the IC. This component is applicable for
both analogue and digital circuitry.
The IA is described using an independent current source or an independent voltage source
with two internal terminals as shown in Figure 2.
ITITAA--[[00]]
ITITAA++[[00]]

IEC  1645/08
Figure 2 – IA component
The characteristics of IA component are typically described in the time domain, and the
characteristics can also be described in the frequency domain.
The description of an IA component shall contain the following information.
 Name of the IA component
 Names of its internal terminals
 Operational mode or test vector
 Domain (time or frequency)
 Definition of origin of time, and cycle-time for the operational mode (for time domain)
 Definition of origin of phase (for frequency domain)
 Operational conditions and applicable ranges
a) Power supply voltage ranges
b) Temperature range

---------------------- Page: 11 ----------------------
– 10 – 62433-2  IEC:2008
c) Frequency range
 Characteristics of the IA
a) Current or voltage waveform over the whole cycle-time (for time domain)
b) Current or voltage amplitude and phase, versus frequency over the whole frequency
range (for frequency domain)
EXAMPLE 1
Figure 3 shows an example of characteristics of IA in the time domain. The waveform
depends on the specific operational mode of function. A simple waveform such as a triangular
waveform can be used for the component description.
i (A)
time (s)
IEC  1646/08

Figure 3  Example of IA characteristics in the time domain
EXAMPLE 2
Figure 4 shows an example of characteristics of IA in the frequency domain.
I (dBµA)
f (Hz)

IEC  1647/08
Figure 4  Example of IA characteristics in the frequency domain
5.3 Passive Distribution Network (PDN)
The Passive Distribution Network component (PDN) presents the characteristics of
propagation path of electromagnetic noises such as power distribution network (part of the
PDN). The PDN can be linear or non-linear.

---------------------- Page: 12 ----------------------
62433-2  IEC:2008 – 11 –
The PDN consists of passive elements, and is equipped with internal terminals. And the PDN
can have external terminals.
The PDN can be described using a netlist. In the case the PDN can be assumed to be linear,
some matrix formats such as the S-parameter can also present the PDN characteristics.
The description of a PDN component shall contain the following information.
 Name of the PDN component
 Names of its internal terminals and external terminals
 Applicable ranges
a) Power supply voltage range
b) Temperature range
c) Applicable load conditions if the PDN is for output
d) Applicable frequency range
 Characteristics of the PDN
EXAMPLE 1
Figure 5 shows an example of a four-terminal PDN using lumped elements. The ETVdd and
ETVss are two external terminals of the PDN. The IT[1] and the IT[0] are two internal
terminals.
ITIT[[11]] ITIT[[00]]
PDPDNN
ETETVVdddd EETTVVssss

IEC  1648/08
Figure 5  Example of a four-terminal PDN using lumped elements
EXAMPLE 2
Figure 6 depicts the seven-terminal PDN structure using distributed elements such as
transmission lines. The ETVxx are the four external terminals, the ITVxx are two internal
terminals and the ETGnd is the common ground of the four transmission lines, connected to
the PCB ground.
PDPDNN
EETTVVdd[dd[0]0] IITTVVddd[d[0]0]
ITITVVssss[[00]]
EETTVVss[ss[00]]
EETTVVdd[dd[1]1]
EETTVVss[ss[11]]
ETETGGnndd

IEC  1649/08
Figure 6  Example of a seven-terminal PDN using distributed elements

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– 12 – 62433-2  IEC:2008
EXAMPLE 3
Figure 7 shows an example of a twelve-terminal PDN using scattering parameters in a matrix
format (black box). The ET[x] are external termin
...