IEC TR 62433-2-1:2010

EMC IC modelling - Part 2-1: Theory of black box modelling for conducted emission

IEC/TR 62433-2-1:2010 covers black box modelling which has the potential to make the modelling of conducted emission very simple, very fast, and can provide complete protection of proprietary information of IC vendors. This technical report is intended to provide the theoretical background on black box modelling for IC conducted emission.

Modèles de circuits intégrés CEM - Partie 2-1: Théorie du modèle de la boîte noire pour les émissions conduites

La CEI/TR 62433-2-1:2010 couvre le modèle de la boîte noire qui permet de créer un modèle d'émissions conduites très simple et très rapide et peut offrir une protection complète des informations propriétaires des fabricants de circuits intégrés. Ce rapport technique est destiné à fournir un support théorique sur le modèle de la boîte noire pour les émissions conduites des circuits intégrés.

General Information

• Status: Published
• Publication Date: 04-Oct-2010
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 2 - TC 47/SC 47A/WG 2
• Current Stage: PPUB - Publication issued
• Start Date: 05-Oct-2010
• Completion Date: 30-Sep-2010

Standards Content (Sample)

IEC/TR 62433-2-1 ®
Edition 1.0 2010-10
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
EMC IC modelling –
Part 2-1: Theory of black box modelling for conducted emission

Modèles de circuits intégrés CEM –
Partie 2-1: Théorie du modèle de la boîte noire pour les émissions conduites

IEC/TR 62433-2-1:2010
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IEC/TR 62433-2-1 ®
Edition 1.0 2010-10
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
EMC IC modelling –
Part 2-1: Theory of black box modelling for conducted emission

Modèles de circuits intégrés CEM –
Partie 2-1: Théorie du modèle de la boîte noire pour les émissions conduites

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
U
CODE PRIX
ICS 31.200 ISBN 978-2-88912-208-0
– 2 – TR 62433-2-1 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Integrated circuit and modelling board .5
3 Assumptions.7
3.1 ICEM-CE .7
3.2 Black box model .9
4 Modelling.9
4.1 Terminals and objectives.9
4.2 Admittance matrix .10
4.3 Matrix compaction .11
4.4 Black box model structure .12
5 Parameter extractions .13
5.1 General .13
5.2 Equivalent internal activities .13
5.3 Equivalent passive distribution network .15
5.4 Parameter extraction method using finite impedance termination.16
5.5 Black box model including the reference terminal .17
6 Implementation.17
6.1 General .17
6.2 Configuration of the application board .17
6.3 Implementation of black box models.20
6.4 Solutions to noise voltages and noise currents .20
Annex A (informative) Nodal equation.22
Annex B (informative) Example of black box modelling .24
Bibliography.28

Figure 1 − Integrated circuit and its modelling board .6
Figure 2 − Basic ICEM-CE model structure for an IC.7
Figure 3 − Representation of the integrated circuit and its modelling board by ICEM-CE.8
Figure 4 − Structure of the ICEM-CE for IC black box modelling .10
Figure 5 − IC Black box model structure.12
Figure 6 − IC black box model description with circuit elements .13
Figure 7 − Setup for extraction of equivalent IAs.14
Figure 8 − Definition of phase .15
Figure 9 − Setup for extraction of equivalent PDN.16
Figure 10 − Setup for extraction of equivalent IAs and PDN .16
Figure 11 − Configuration of the application board .18
Figure 12 − Setup for simulation of the application board.19
Figure B.1 − The ICEM-CE model .25
Figure B.2 − Spectrum of equivalent IA.26
Figure B.3 − Calculated admittances.26
Figure B.4 − Noise voltage and noise current.27

TR 62433-2-1 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
EMC IC MODELLING –
Part 2-1: Theory of black box modelling for conducted emission

FOREWORD
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patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
The main task of IEC technical committees is to prepare International Standards. However, a
technical committee may propose the publication of a technical report when it has collected
data of a different kind from that which is normally published as an International Standard, for
example "state of the art".
IEC 62433-2-1, which is a technical report, has been prepared by subcommittee 47A:
Integrated circuits, of IEC technical committee 47: Semiconductor devices.
The text of this technical report is based on the following documents:
Enquiry draft Report on voting
47A/826A/DTR 47A/834/RVC
Full information on the voting for the approval of this technical report can be found in the
report on voting indicated in the above table.

– 4 – TR 62433-2-1 © IEC:2010
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of IEC 62433 series, under the general title EMC IC modelling, can be found
on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
TR 62433-2-1 © IEC:2010 – 5 –
EMC IC MODELLING –
Part 2-1: Theory of black box modelling for conducted emission

1 Scope
This part of IEC 62433-2-1 covers black box modelling which has the potential to make the
modelling of conducted emission very simple, very fast, and can provide complete protection
of proprietary information of IC vendors.
This technical report is intended to provide the theoretical background on black box modelling
for IC conducted emission.
2 Integrated circuit and modelling board
Figure 1 shows an integrated circuit (IC) and a modelling board. The IC is equipped with
power/ ground pins, output pins and input pins. Usually an IC requires different power supply
connections, namely, to supply digital cores, I/Os, and analogue circuits. Each one of these
power supplies may have plural pins.
An IC cannot be activated by itself. To activate the IC properly, the IC has to be provided with
power supplies, a set of input signals or an input signal vector, and appropriate loads for
output pins.
To achieve these requirements, the modelling board is used. The modelling board provides
minimum requirements for the activation. It supplies power, and input signals to the IC, and it
gives typical loads for the output pins. In addition, power/ ground pins of the same category
are connected to each other in the modelling board resulting in one terminal for each category
of the power/ ground supply at the interface of the modelling board.
The board is also used for parameter extractions for modelling the IC. The IC modelling
includes the board. The relationship between the IC modelling and the modelling board is just
like the relationship between measured data and measurement board that affects
measurement data. Therefore the modelling board should be as simple and general as
possible.
– 6 – TR 62433-2-1 © IEC:2010
Input signal vector
Input pins
Z
load
Output
Z
Integrated load
pins
circuit
Z
load
Z
load
Power/ground pins
Z Z Z Z
PG PG PG PG
Modelling board
IEC  2272/10
Figure 1a) – Entire structure
Input pins
Output
Internal circuits
Input circuits Output circuits
pins
Power/ground terminals Power/ground terminals Power/ground terminals
• • •  • • •  • • •
Power/ground network
IEC  2273/10
Power/ground pins
Figure 1b) – Structure of the IC part
Figure 1 – Integrated circuit and its modelling board

TR 62433-2-1 © IEC:2010 – 7 –
3 Assumptions
3.1 ICEM-CE
ICEM-CE is a macro model that approximates conducted emission behaviour of an IC using
two types of components, internal activity (IA) and passive distribution network (PDN) as
shown in Figure 2. These two types of components are connected through internal terminals
(ITs).
The IAs represent noise sources that originate in switching of active devices within the IC.
The PDN represents noise propagation characteristics from the internal terminals to the
external terminals (ETs).
The black box modelling is based on this ICEM-CE model structure.

Internal activity (IA)
IA
IA
• • •
Internal terminals
Passive distribution network (PDN)
External terminals
IEC  2274/10
Figure 2 – Basic ICEM-CE model structure for an IC
Figure 3 shows how to make an ICEM-CE model for the example of an IC and its modelling
board shown in Figure 1. Figure 3a) shows the assignment of IA and PDN. The IA part
includes input vector generators and output loads on the modelling board. The PDN part
consists of the IC PDN part and Board PDN part. The IC PDN part consists of the power/
ground network of the die and the package of the IC. Figure 3b) shows the ICEM-CE structure
of the IC and its modeling board with IAs and PDNs.

– 8 – TR 62433-2-1 © IEC:2010
Input signal vector
IA part
Z
load
Z
load
Internal circuits Output circuits
Input circuits
Z
load
Z
load
Power/ground terminals Power/ground terminals Power/ground terminals
• • •  • • •  • • •
Power/ ground network
PDN part
IC PDN part
Z Z Z Z
PG PG PG PG
Board PDN part
IEC  2275/10
Figure 3a) – IA and PDN assignment

IA IA IA
IA IA IA
• • •  • • •  • • •
Internal terminals
PDN of IC
External terminals
External terminals PDN of Board

IEC  2276/10
Figure 3b) – ICEM-CE representation
Figure 3 – Representation of the integrated circuit and its modelling board by ICEM-CE

TR 62433-2-1 © IEC:2010 – 9 –
3.2 Black box model
In black box modelling, the PDN is described using a numerical matrix. To represent the PDN
using a matrix, the PDN is assumed to be a linear circuit. Although the PDN is usually non-
linear, this assumption is generally valid because noise voltages are small enough.
The elements of the matrix depend on noise frequency. Therefore, the PDN and the IAs
should be described in frequency domain, and the PDN and IAs should be given for each
frequency concerned.
The PDN can be represented either by an impedance matrix or an admittance matrix. This
technical report uses an admittance matrix because admittance is more convenient than
impedance to combine other models to the black box model.
4 Modelling
4.1 Terminals and objectives
As shown in Figure 1 and Figure 3, an input signal vector is applied to the IC through input
terminals. The signal vector activates the IC and it causes IAs inside the IC. Therefore, the
voltages and currents of the input terminals are conditions for the modelling. Noise voltages
and currents at the input terminals are not the objectives of the modelling.
For the output pins of the IC, the modelling board provides typical loads. These loads
generate IAs at the output circuits of the IC and consequently, from the IAs noise voltages
and noise currents appear at the power/ ground terminals. This effect is included into the
black box modelling. Output terminals themselves are also a source of conducted emissions,
but the black box modelling given in this technical report cannot handle these emissions,
because the characteristics of output circuits are non-linear. To simulate conducted emissions
through output terminals, other black box modelling such as IMIC or IBIS has to be combined
with this black box modelling.
Users cannot manipulate the internal terminals shown in Figure 2 that connect the IAs to the
PDN. Therefore, the noise voltages and noise currents of internal terminals are also not the
objectives of the black box modelling. But for the first step of this study, these terminals have
to be used for the modelling, because these terminals provide the noise sources to the PDN.
They are necessary particularly when a model is built from design data.
As the result, the objectives of the black box modelling are to provide models that can be
used for numerical calculation of conducted emissions through power and ground terminals of
an IC, which is applicable for an application board.
The ICEM-CE model structure for the black box modelling is shown in Figure 4. The IAs are
expressed by current sources, and the PDN is given as an admittance matrix.
The noise voltages of the power/ ground terminals are defined with reference to a reference
ground terminal (ET0) that is directly connected to the reference plane of the modelling board.
The other power/ ground terminals of the PDN are named as ETx. The value of n is the
number of power/ ground terminals minus one. The number of IAs is m. Therefore there are
2 ⋅m internal terminals, and these terminals are named as ITx as shown in Figure 4.

– 10 – TR 62433-2-1 © IEC:2010
IA IA
m
Internal activity (IA)
• • •
IT IT
IT IT
1 2 2m-1 2m
Internal terminal (IT)
Passive distribution network (PDN)
[Y ]
External terminal (ET)
ET ET ET ET
0 1 n-1 n
• • •
Power/ground terminals
IEC  2277/10
Figure 4 – Structure of the ICEM-CE for IC black box modelling
4.2 Admittance matrix
The PDN in Figure 4 is assumed to be a linear circuit. Therefore, the PDN can be expressed
using an admittance matrix based on the nodal analysis method. The equation that expresses
the IC, shown as Figure 4, is given below.
⎡ Y . Y Y . Y ⎤ ⎡V ⎤ ⎡ I ⎤
ET1 ET1 ET1 ETn ET1 IT1 ET1 IT2m ET1 ET1
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
. . . . . . . .
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
Y . Y Y . Y V I
ETn ET1 ETn ETn ETn IT1 ETn IT2m ETn ETn
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
Y . Y Y . Y V I
IT1 ET1 IT1 ETn IT1 IT1 IT1 IT2m IT1 IT1
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
× = (1)
⎢ . . . . . . ⎥ ⎢ . ⎥ ⎢ I ⎥
IT2
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
. . . . . . . .
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
. . . . . . . I
IT2m-1
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
Y . Y Y . Y V I
⎣ IT2m ET1 IT2m ETn IT2m IT1 IT2m IT2m⎦ ⎣ IT2m⎦ ⎣ IT2m⎦
Here, V and I are the noise voltage and the noise current of ETx, respectively. V and
ETx ETx ITx
I represent the noise voltage and the noise current of ITx, respectively.
ITx
NOTE Equation 1 describes the PDN without using variables of voltages and currents for internal nodes, which
connect passive elements making up the PDN. Annex A gives the proof of the equation.
The admittance matrix is regular and its dimension is (n+2m, n+2m). For simplicity, Equation
(1) is represented using sub-matrices and vectors as follows. In this equation, IAs substitute
the currents of the internal terminals.
[]Y [Y ] []V []I
⎡ ⎤ ⎡ ⎤ ⎡ ⎤
ET ET ET IT ET ET
× = (2)
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] []V []I
⎣ IT ET IT IT ⎦ ⎣ IT ⎦ ⎣ IT ⎦
where,
TR 62433-2-1 © IEC:2010 – 11 –
[]Y is the regular admittance sub-matrix that represents interactions between ETs;
ET ET
[]Y is the admittance sub-matrix that represents interactions between ETs and ITs;
ET IT
[]Y is the admittance sub-matrix that represents interactions between ITs and ETs;
IT ET
[]Y is the regular admittance sub-matrix that represents interactions between ITs;
IT IT
[]V is the voltage vector that represents noise voltages of ETs;
ET
[]V is the voltage vector that represents noise voltages of ITs;
IT
[]I is the current vector that represents noise currents of ETs; and
ET
[]I is the current vector that represents noise currents of ITs.
IT
[]I is given as follows.
IT
IA
⎡ ⎤
⎢ ⎥
- IA
⎢ ⎥
⎢ ⎥
.
[]I =[IA] ≡ (3)
⎢ ⎥
IT
.
⎢ ⎥
⎢ ⎥
IA
m
⎢ ⎥
− IA
⎢ ⎥
⎣ m⎦
4.3 Matrix compaction
[]V is eliminated out from Equation (2), as follows.
IT
Equation (2) can be expanded into following two equations, combining Equation (3).
[]Y ×[V] +[Y ]×[V] =[I] (4)
ET ET ET ET IT IT ET
[]Y ×[V] +[Y ]×[V] =[IA] (5)
IT ET ET IT IT IT
From Equation (5), []V is obtained as follows.
IT
−1
[]V =[Y ] ×()[IA] −[Y ]×[V ] (6)
IT IT IT IT ET ET
By substituting Equation (6) by Equation (4), []V can be eliminated out from Equation (4).
IT
−1 −1
([]Y −[Y ]×[Y ] ×[Y ])×[]V =[I ] −[Y ]×[Y ] ×[IA] (7)
ET ET ET IT IT IT IT ET ET ET ET IT IT IT
The coefficient of []V in the left-hand side is an admittance matrix whose dimension is (n, n).
ET
And the second term of the right-hand side is a current vector with n-dimension. The
dimension of []IA' is n, and the dimension of []Y' is (n, n). Therefore, []IA' and []Y'
ET ET ET ET
can be defined as follows.
−1
[]IA' ≡ −[Y ]×[Y ] ×[IA] (8)
ET IT IT IT
−1
[Y' ] ≡[Y ] −[]Y ×[Y ] ×[]Y (9)
ET ET ET ET ET IT IT IT IT ET
– 12 – TR 62433-2-1 © IEC:2010
Then, Equation (7) becomes very simple.
[]Y' ×[V] =[I] +[IA'] (10)
ET ET ET ET
4.4 Black box model structure
In Equations (8) and (9), []IA' and []Y' are constant. Therefore []IA' and []Y' are
ET ET ET ET
named as "equivalent internal activities (equivalent IAs)" and "equivalent passive distribution
network (equivalent PDN)", respectively.
Equation (10) means that the black box model structure consists of an equivalent PDN and
equivalent IAs as illustrated in the dotted area of Figure 5.
Compared with Figure 4, the IAs at the internal terminals are modified and transferred to the
parallel positions to the external terminals. And the PDN is modified and simplified.

IC Black box model
Equivalent PDN
[Y' ]
ET ET
IA'
n
IA'
2 Equivalent IAs
IA'
ET
0 ET ET ET
1 2 • • • n
IEC  2278/10
Figure 5 – IC Black box model structure
The IC black box model structure, as shown in Figure 5, is modelled using the expression
having the (n+1) external terminals including the reference, where the number of the
independent terminal voltage is n. Equation (10) is the Y matrix expression that determines
the n external terminal voltages except for the reference as independent variables, and it is
the n port circuit which has the reference terminal as the common negative terminal and the
other terminals as the positive terminals. A n port circuit of black box model is expressed with
circuit elements as shown in Figure 6. It consists of the parallel connection of passive
elements having the admittance of the diagonal elements of the Y matrix, voltage controlled
current sources having the current of the product of the non-diagonal element value and the
other port voltage, and the independent current source having the current calculated from
Equation (8).
The Y matrix expression of Equation (10) can be converted into an expression using Z or S
matrices easily using conversion formulas.

TR 62433-2-1 © IEC:2010 – 13 –
Y’
I
Y’ V
Y’ V
1,1 • • • Y’ V 1
1,2 2 1,n n IA’
• •
•
•
I
n
•
•
Y’ V
IA’
Y’ n,2 2 • • • n V
Y’ V
n,n n
n,n n
IEC  2279/10
Figure 6 – IC black box model description with circuit elements
5 Parameter extractions
5.1 General
The black box model for conducted emission consists of two components, the equivalent IAs
and the equivalent PDN. To build a black box model from measurements, elements of these
two components should be obtained. This clause describes the methods used to obtain these
components from measurements.
The equivalent IAs depend on the operational mode and power supply condition of the IC.
Therefore, the typical power supply condition and the repetitive specific input signal vector
that corresponds to the operational mode should be applied to the power/ ground terminals
and the input terminals of the modelling board during the measurements of equivalent IAs,
respectively.
The equivalent PDN is assumed as a linear function, but it actually depends on voltages.
Therefore, the typical power supply is given to the power/ground terminals of the modelling
board during the measurements. Relatively small signals should be used for the
measurements to assure the assumption is valid.
5.2 Equivalent internal activities
From Equation (10), the equivalent noise current sources can be,
[]IA' = −[I ], when []V =[0] (11)
ET ET
– 14 – TR 62433-2-1 © IEC:2010
This means that the equivalent IAs can be obtained by measuring the []I under the
ET
condition that all the external terminals are RF shorted to the reference terminal. The
configuration of the measurement setup is shown in Figure 7.

IC Black box model
Equivalent PDN
[Y' ]
ET ET
IA'
n
IA'
Equivalent IAs
IA'
ET
ET ET ET
0 1 2 n
• • •
A
A
A
IEC  2280/10
Figure 7 – Setup for extraction of equivalent IAs
Each value of []I is a complex number; therefore, the amplitude and phase for each current
ET
element should be measured.
One way is to measure the amplitude and phase in frequency domain directly for each
external terminal for each frequency concerned. In this method, the phases should be
determined with reference to the cycle of the input signal vector. The definition is given in
Figure 8.
TR 62433-2-1 © IEC:2010 – 15 –

Cycle time of repetitive input signal vector
Input signal vector (i) Input signal vector (i+1)
EqEqEqEquivuivuivuivaaaalentlentlentlent I I I IAAAA
PhasePhasePhasePhasePhasePhasePhasePhase
t = 0 Time
IEC  2281/10
Figure 8 – Definition of phase
The other way is to measure the waveforms of the external terminals in the time domain. The
time is also determined with reference to the start of the cycle of the input signal vector. After
that, the waveforms should be converted into frequency domain using the Fourier
transformation.
5.3 Equivalent passive distribution network
Now all elements of the equivalent IAs are already known. Therefore each element of the
admittance matrix of equivalent PDN can be derived from Equation (10) as shown in Equation
(12).
I + IA'
i i
Y' = , at all V = 0 (12)
i j i≠j
V
j
Here, I is the measured current while V is the given signal voltage for the measurement. The
i j
configuration of the measurement setup for Y’ is shown in Figure 9. In this measurement, the
i j
phase of V and I should be given with reference to the cycle of the input vector, because the
j i
input signal vector determines the phase of IA.

– 16 – TR 62433-2-1 © IEC:2010
IC Black box model
Equivalent PDN
[Y' ]
ET ET
IA'
n
IA'
Equivalent IAs
IA'
ET ET ET ET
0 1 j n
• • •
A
V A
j
A
IEC  2282/10
Figure 9 – Setup for extraction of equivalent PDN
5.4 Parameter extraction method using finite impedance termination
The parameter extraction method explained above is the one by using RF short termination
for each external port. In reality a complete RF short is difficult for some cases, in particular
for measurements of the real devices. Thus a parameter extraction method using finite
impedance termination is described herein.

IC Black box model
Equivalent PDN
[Y' ]
ET ET
IA'
n
IA'
j
Equivalent IAs
IA'
ET ET ET ET
0 1 j n
• • • • • •
Z V A
1 1
Z
V A
j j
Z
A
n V
n
IEC  2283/10
Figure 10 – Setup for extraction of equivalent IAs and PDN

TR 62433-2-1 © IEC:2010 – 17 –
Figure 10 shows the setup structure of limited impedance termination. Each terminal is
terminated with a series of a DC power supply, an AC voltage source, a current meter, and a
finite impedance element. The circuit of Figure 10 can be expressed using n independent
equations. The number of elements of Y’ is n and that of the IA’ is n. Then the number of
unknowns is n(n+1). Then n(n+1) equations are necessary to get all element values of Y’ and
IA’. As the circuit of Figure 10 has n independent equations for each excitation, it needs (n+1)
independent sets of external AC voltage sources to determine the all unknown values.
For Figure 10, its terminal condition is expressed as below.
[]V =[Z ]×[I ] +[V] (13)
ET PS PS ET
−1
[]I =[Z ] ×[][V ]−[V] =[Y ]×[][V] −[V] (14)
ET PS PS ET PS PS ET
The combination of Equations (10) and (13), or Equations (10) and (14), give the following
equations.
[]Y' ×[][Z ]×[I]+[V] =[I]+[IA'] (15)
ET ET PS PS ET ET
[Y' ]×[]V =[][Y ]×[][]V −[V] +[IA'] (16)
ET ET ET PS PS ET
By using Equation (15), the combination according to (n+1) of input []V and its response []I
ET
leads []Y' and []IA' . And by using Equation (16), the combination according to (n+1) of
ET ET
input []V and its response []V leads []Y' and []IA' .
ET ET ET
To do this for example, we can input one AC voltage source at one external terminal while
setting all other AC sources to zero, and repeat this for each external terminal. There will also
be one case where all AC sources are zero. When we solve the equations from real
measurement data, we can add the other drive patterns (the drive from plural ports) because
with measurement error, it is useful to use the least-squares method to optimize the
parameters.
5.5 Black box model including the reference terminal
The reference terminal is not included in []IA' and [Y'] described above. When we implement
ICs on a board, expanding []IA' and [Y'] so that they include the reference terminal is
convenient because generally the reference terminal is necessary when an IC is placed on a
board like the other terminals. As shown in detail in Annex A, IA' element of the reference
terminal is calculated from the summation of IA’ elements with the reference terminal set as
zero. The Y' element of the reference terminal is calculated from the summation of Y’
elements where the reference terminal along a row or a column is zero.
6 Implementation
6.1 General
This clause describes the methodology for implementation of the black box models into an
application board, taking as an example an application board with two black box models. An
example is given in Annex B.
6.2 Configuration of the application board
The configuration of the application board is shown in Figure 11. The board contains two ICs,
IC-A and IC-B, and these are connected to the application board using the terminal group A
and the terminal group B, respectively.

– 18 – TR 62433-2-1 © IEC:2010
The board is also equipped with the terminal group C. The application board receives power
supplies and ground from the outside environment using these terminals.
Application board, [Y ]
APP
IC-A IC-B
Y' ] × [V ] = [I ]+[IA' ]
[
B B B B
[Y' ] × [V ] = [I ]+[IA' ]
A A A A
Terminal group A
Terminal group B
Terminal group C
Z Z Z
Z
PG PG PG PG
Power supplies
IEC  2284/10
Figure 11 – Configuration of the application board
The components for simulation of the application board consist of IC-A black box model, IC-B
black box model, PDN model of the power/ ground network of the application board, and
models of the power supplies. The connection of the components for simulation is shown in
Figure 12.
TR 62433-2-1 © IEC:2010 – 19 –
Application board model
IC-B Black box model
IC-A Black box model
Equivalent PDN
Equivalent PDN
[Y' ]
B
[Y' ]
A
IA'
n
IA'
n
IA'
IA'
Equivalent IAs
Equivalent IAs
IA'
IA'
ET
B0 ET
B1 ET • • • ET
ET ET ET B2  Bn
A0 A1 ET • • •  An
A2
Equivalent PDN
[Y ]
APP
[Y ]
Z Z Z PS PS
PG Z PG PG
PG
Power supplies
IEC  2285/10
Figure 12 – Setup for simulation of the application board
Let's suppose that the black box models for IC-A and IC-B, and the admittance matrix of the
application board are already known as follows. Each IC model used here is the black box model
including its reference terminal.
[]Y' ×[V] =[I] +[IA'] (17)
A A A A
[]Y' ×[V] =[I] +[IA'] (18)
B B B B
Here, []V , []V and []V are the noise voltage vectors of terminal group A, B and C,
A B C
respectively. −[]I , −[]I and []I are the noise current vectors of terminal group A, B and C,
A B C
respectively.
And the admittance matrix of the application board is given as follows.
[]Y [Y ][Y ]
⎡ ⎤
A A A B A C
⎢ ⎥
[]Y =[]Y [Y ][Y ] (19)
APP B A B B B C
⎢ ⎥
⎢ ⎥
[]Y [Y ][Y ]
⎣ C A C B C C⎦
In Equation (19), the sub-matrix []Y represents the interactions between terminal A and
A B
terminal B, the sub-matrix []Y represents interactions between terminal A and terminal C,
A C
etc.
– 20 – TR 62433-2-1 © IEC:2010
6.3 Implementation of black box models
The whole application board can be expressed by Equation (20) as shown below.
[]Y [Y ][Y ] []V []I
⎡ ⎤ ⎡ ⎤ ⎡− ⎤
A A A B A C A A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ][Y ] []V []I (20)
× = −
B A B B B C B B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ][Y ] []V []I
C A C B C C C C
⎣ ⎦ ⎣ ⎦ ⎣ ⎦
The currents of terminal group A and B have negative signs, since the noise currents to the IC
models and the noise currents to the application board are opposite.
[]I and []I in Equation (20) can be eliminated out by substituting these using Equation (17)
A B
and (18). As the result, the following equation that represents the whole system is obtained.
[]Y +[Y'] [Y ] [Y ] ⎡[]V ⎤ ⎡[]IA' ⎤
⎡ ⎤
A A A A B A C A A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] +[Y'][Y ] ×[]V =[]IA' (21)
B A B B B B C B B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] [Y ] []V []I
⎣ C A C B C C⎦ ⎣ C⎦ ⎣ C ⎦
6.4 Solutions to noise voltages and noise currents
Initially, one supposes that as a general boundary condition of the system, an admittance
matrix of power supplies []Y is given. The relationship between []V and []I is given by
PS PS C C
the following equation.
[]Y ×[V] = −[I] (22)
PS PS C C
Equation (21) becomes Equation (23) by substituting []I using Equation (22).
C
⎡[]Y +[Y'] [Y ] [Y ] ⎤ ⎡[]V ⎤ ⎡[]IA' ⎤
A A A A B A C A A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] +[Y'] [Y ] ×[]V =[]IA' (23)
B A B B B B C B B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] [Y ] +[Y ] []V []0
C A C B C C PS PS C
⎣ ⎦ ⎣ ⎦ ⎣ ⎦
Then, the general solutions of []V , []V and []V can be derived as follows.
A B C
−1
⎡[]V ⎤ ⎡[]Y +[Y'] [Y ] [Y ] ⎤ ⎡[]IA' ⎤
A A A A A B A C A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]V = []Y [Y ] +[Y'] [Y ] ×[]IA' (24)
B B A B B B B C B
⎢ ⎥ ⎢ ⎥
⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]V []Y [Y ] [Y ] +[Y ] []0
⎣ C⎦ ⎣ C A C B C C PS PS⎦ ⎣ ⎦
And the general solutions of []I , []I and []I are obtained from Equation (20) using voltage
A B C
vectors given in Equation (24).
−[]I []Y [Y ][Y ] []V
⎡ ⎤ ⎡ ⎤ ⎡ ⎤
A A A A B A C A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
−[]I =[]Y [Y ][Y ] ×[]V
B B A B B B C B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]I []Y [Y ][Y ] []V
⎣ C ⎦ ⎣ C A C B C C⎦ ⎣ C⎦
−1
[]Y [Y ][Y ] []Y +[Y'] [Y ] [Y ] []IA'
⎡ ⎤ ⎡ ⎤ ⎡ ⎤
A A A B A C A A A A B A C A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ][Y ] × []Y [Y ] +[Y'] [Y ] ×[]IA' (25)
=
B A B B B C B A B B B B C B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ][Y ] []Y [Y ] [Y ][Y ] []0
+
C A C B C C ⎣ C A C B C C PS PS⎦ ⎣ ⎦
⎣ ⎦
TR 62433-2-1 © IEC:2010 – 21 –
Second, one considers a specific boundary condition that the impedances of the power
supplies are low enough compared to other components. This condition is specific but it is a
normal assumption for many applications. In this case, []V can be assumed as []0 .
C
The particular solutions of the noise voltage vectors for this condition are obtained from
Equation (21).
⎡[]Y +[Y'] [Y ] [Y ]⎤ ⎡[]V ⎤ ⎡[]IA' ⎤
A A A A B A C A A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] +[Y'][Y ] ×[]V =[]IA' (26)
B A B B B B C B B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]Y [Y ] [Y ] []0 []I
C A C B C C C
⎣ ⎦ ⎣ ⎦ ⎣ ⎦
−1
[]V []Y +[Y'] [Y ] []IA'
⎡ ⎤ ⎡ ⎤ ⎡ ⎤
A A A A A B A
= × (27)
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]V []Y [Y ] +[Y'] []IA'
⎣ B⎦ ⎣ B A B B B ⎦ ⎣ B⎦
By setting []V as []0 in Equation (20), the noise current vectors are derived as follows.
C
⎡−[]I ⎤ ⎡[]Y [Y ][Y ]⎤ ⎡[]V ⎤
A A A A B A C A
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
−[]I =[]Y [Y ][Y ] ×[]V (28)
B B A B B B C B
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[]I []Y [Y ][Y ] []0
C C A C B C C
⎣ ⎦ ⎣ ⎦ ⎣ ⎦
⎡−[]I ⎤ ⎡[]Y [Y ]⎤
A A A A B
[]V
⎡ ⎤
⎢ ⎥ ⎢ ⎥ A
−[]I =[]Y [Y ] × (29)
B B A B B ⎢ ⎥
⎢ ⎥ ⎢ ⎥
[]V
⎣ B⎦
⎢ ⎥ ⎢ ⎥
[]I []Y [Y ]
C C A C B
⎣ ⎦ ⎣ ⎦
As described in this clause, using the black box model, the noise voltages and the noise
currents of an application board can be obtained by simple matrix calculations.

– 22 – TR 62433-2-1 © IEC:2010
Annex A
(informative)
Nodal equation
A.1 Purpose
This annex is intended to review the fundamentals of the nodal equation. The annex gives
proof of Equation (1) that represents characteristics of a PDN using only its external nodes;
i.e. external terminals and internal terminals.
A.2 Review
Consider a passive distribution network with (n + 1) nodes. The 0 node is the reference node.
For each node, the following equation is derived from Kirchhoff's first law.
I = y × (V −V ) (A.1)
i ∑ i j i j
j ≠i
I = y ×V − y ×V (A.2)
i ∑ i j i ∑ i j j
j≠i j≠i
Here, V and I are the voltage and the current flowing into the node i, respectively. y is
i i i j
the admittance of the element that is located between node i and node j.
Using an admittance matrix, Equation (A.2) can be rewritten as a nodal equation as follows.
⎡ ⎤
y − y . − y − y − y . − y − y
∑ 0, j 0,1 0, i-1 0, i 0, i+1 0, n-1 0, n
⎢ ⎥
j≠0
⎢ ⎥
− y y . − y − y − y . − y − y
⎢ ⎥
1,0 ∑ 1, j 1,i-1 1, i 1, i+1 1, n-1 1, n
V I
⎡ ⎤ ⎡ ⎤
⎢ ⎥ 0 0
j≠1
⎢ ⎥ ⎢ ⎥
⎢ ⎥
. . . . . . . . . V I
1 1
⎢ ⎥ ⎢ ⎥
⎢ ⎥
⎢ ⎥ ⎢ ⎥
− y − y . y − y − y . − y − y . .
⎢ ⎥
i-1, 0 i-1, 1 ∑ i-1 ,j i-1, i i-1, i+1 i-1, n-1 i-1 ,n
⎢ ⎥ ⎢ ⎥
⎢ ⎥
j≠i−1
V I
⎢ i-1⎥ ⎢ i-1⎥
⎢ ⎥
− y − y . − y y − y . − y − y
i ,0 i ,1 i, i-1 ∑ i, j i ,i+1 i ,n-1 i, n ⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⋅ V = I (A.3)
i i
⎢ ⎥ ⎢ ⎥
j≠i
⎢ ⎥
V I
⎢ ⎥ ⎢ ⎥
i+1 i+1
⎢ ⎥
− y − y . − y − y y . − y − y
i+1,0 i+1 ,1 i+1, i-1 i+1, i i+1 ,j i+1, n-1 i+1 ,n
∑
⎢ ⎥ ⎢ ⎥
⎢ ⎥
. .
j≠i+1
⎢ ⎥ ⎢ ⎥
⎢ ⎥
. . . . . . . . .
⎢V ⎥ ⎢I ⎥
⎢ ⎥
n-1 n-1
⎢ ⎥ ⎢ ⎥
⎢ ⎥
− y − y . − y − y − y . y − y
V I
n-1 ,0 n-1,1 n-1, i-1 n-1, i n-1, i+1 ∑ n-1, j n-1,n
⎣ n⎦ ⎣ n⎦
⎢ ⎥
j≠n−1
⎢ ⎥
⎢ − y − y . − y − y − y . − y y ⎥
n, 0 n, 1 n, i-1 n, i n, i+1 n, n-1 n, j
∑
⎢ ⎥
j≠n
⎣ ⎦
The value of each diagonal element is the summation of admittances of passive elements that
are connected to the corresponding node. The matrix is symmetrical because y = y .
i j j i
In Equation (A.3) the summation of all elements in each column or each row becomes zero.
Namely this matrix is singular. Therefore we usually use the partial matrix and the partial

TR 62433-2-
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