IEC TS 62215-2:2007

Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method

Contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances.The objective is to describe general conditions to obtain a quantitative measure of immunity of ICs establishing a uniform testing environment. Critical parameters that are expected to influence the test results are described. Deviations from this specification should be explicitly noted in the individual test report. This synchronous transient immunity measurement method uses short impulses with fast rise times of different amplitude, duration and polarity in a conductive mode to the IC. In this method, the applied impulse has to be synchronized with the activity of the IC to make sure that controlled and reproducible conditions can be assured

General Information

• Status: Published
• Publication Date: 09-Sep-2007
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 9 - TC 47/SC 47A/WG 9
• Current Stage: PPUB - Publication issued
• Start Date: 30-Nov-2007
• Completion Date: 10-Sep-2007

Standards Content (Sample)

IEC/TS 62215-2
Edition 1.0 2007-09
TECHNICAL
SPECIFICATION

Integrated circuits – Measurement of impulse immunity –
Part 2: Synchronous transient injection method


IEC/TS 62215-2:2007(E)

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IEC/TS 62215-2
Edition 1.0 2007-09
TECHNICAL
SPECIFICATION

Integrated circuits – Measurement of impulse immunity –
Part 2: Synchronous transient injection method


INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
U
ICS 31.200 ISBN 2-8318-9305-4

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– 2 – TS 62215-2 © IEC:2007(E)
CONTENTS
FOREWORD.4
INTRODUCTION.6

1 Scope.7
2 Normative references .7
3 Terms and definitions .7
4 General .8
4.1 Introduction .8
4.2 Measurement philosophy.8
4.3 Set-up concept .9
4.4 Response signal.9
4.5 Coupling networks.10
4.5.1 General .10
4.5.2 Design of coupling networks .10
4.5.3 Coupling network for the ground/ V pin(s) .10
ss
4.5.4 Coupling network for the supply/ V pin(s) .11
dd
4.5.5 Coupling network for the I/O pin(s) .13
4.5.6 Coupling network for the reference pins.13
4.5.7 Coupling network verification.
...