IEC TS 62215-2:2007
(Main)Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method
Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method
Contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances.The objective is to describe general conditions to obtain a quantitative measure of immunity of ICs establishing a uniform testing environment. Critical parameters that are expected to influence the test results are described. Deviations from this specification should be explicitly noted in the individual test report. This synchronous transient immunity measurement method uses short impulses with fast rise times of different amplitude, duration and polarity in a conductive mode to the IC. In this method, the applied impulse has to be synchronized with the activity of the IC to make sure that controlled and reproducible conditions can be assured
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Standards Content (Sample)
IEC/TS 62215-2
Edition 1.0 2007-09
TECHNICAL
SPECIFICATION
Integrated circuits – Measurement of impulse immunity –
Part 2: Synchronous transient injection method
IEC/TS 62215-2:2007(E)
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IEC/TS 62215-2
Edition 1.0 2007-09
TECHNICAL
SPECIFICATION
Integrated circuits – Measurement of impulse immunity –
Part 2: Synchronous transient injection method
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
U
ICS 31.200 ISBN 2-8318-9305-4
– 2 – TS 62215-2 © IEC:2007(E)
CONTENTS
FOREWORD.4
INTRODUCTION.6
1 Scope.7
2 Normative references .7
3 Terms and definitions .7
4 General .8
4.1 Introduction .8
4.2 Measurement philosophy.8
4.3 Set-up concept .9
4.4 Response signal.9
4.5 Coupling networks.10
4.5.1 General .10
4.5.2 Design of coupling networks .10
4.5.3 Coupling network for the ground/ V pin(s) .10
ss
4.5.4 Coupling network for the supply/ V pin(s) .11
dd
4.5.5 Coupling network for the I/O pin(s) .13
4.5.6 Coupling network for the reference pins.13
4.5.7 Coupling network verification.14
4.6 Test circuit board .14
4.6.1 General .14
4.6.2 IC pin loading / termination.14
4.6.3 Power supply requirements .15
4.7 IC specific considerations.15
4.7.1 IC supply voltage.15
4.7.2 IC decoupling .15
4.7.3 Activity of IC .15
4.7.4 Guidelines for IC stimulation.15
4.7.5 IC monitoring.15
4.7.6 IC stability over time.15
5 Test conditions .16
5.1 Default test conditions.16
5.1.1 General .16
5.1.2 Ambient conditions .16
5.1.3 Ambient temperature .16
5.2 Impulse immunity of the test set-up .16
6 Test set-up .16
6.1 General .16
6.2 Test equipment .17
6.3 Set-up explanation .17
6.4 Explanation of signal relations.18
6.5 Calculation of time step and number of measurements to be conducted .18
6.6 Test procedure .19
6.7 Monitoring check .19
6.8 System verification .19
TS 62215-2 © IEC:2007(E) – 3 –
7 Test report.20
7.1 General .20
7.2 Immunity limits or levels .20
7.3 Performance classes .20
7.4 Interpretation and comparison of results.20
Annex A (informative) Flow chart of the software used in a microcontroller .21
Annex B (informative) Flow chart for the set-up control S/W (bus control program) .22
Annex C (informative) Test board requirements .23
Bibliography.27
Figure 1 – Synchronous transient injection immunity methodology waveforms .9
Figure 2 – Test set-up diagram for synchronous transient injection immunity testing.10
Figure 3 – Circuit diagram of the coupling network for ground/ V pin(s) of an IC.11
ss
Figure 4 – Method to impose synchronous transient injection into ground/ V pin(s).11
ss
Figure 5 – Circuit diagram of the coupling network for supply/ V pin(s) of an IC .12
dd
Figure 6 – Method to impose synchronous transient injection into supply/ V pin(s) .12
dd
Figure 7 – Method to impose synchronous transient injection into I/O pins.13
Figure 8 – Measurement set-up for synchronous transient injection .16
Figure 9 – The waveforms (not in scale) appearing in the test set-up.18
Figure A.1 – Test code flow chart.21
Figure B.1 – Test measurement flow chart .22
Figure C.1 – Typical test board topology.26
Table 1 – IC pin loading recommendations .14
Table C.1 – Position of vias over the board.23
– 4 – TS 62215-2 © IEC:2007(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
MEASUREMENT OF IMPULSE IMMUNITY –
Part 2: Synchronous transient injection method
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IEC 62215-2, which is a technical specification, has been prepared by subcommittee 47A:
Integrated circuits, of IEC technical committe
...
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