IEC TS 62215-2:2007

Integrated circuits - Measurement of impulse immunity - Part 2: Synchronous transient injection method

Contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances.The objective is to describe general conditions to obtain a quantitative measure of immunity of ICs establishing a uniform testing environment. Critical parameters that are expected to influence the test results are described. Deviations from this specification should be explicitly noted in the individual test report. This synchronous transient immunity measurement method uses short impulses with fast rise times of different amplitude, duration and polarity in a conductive mode to the IC. In this method, the applied impulse has to be synchronized with the activity of the IC to make sure that controlled and reproducible conditions can be assured

General Information

• Status: Published
• Publication Date: 09-Sep-2007
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 9 - TC 47/SC 47A/WG 9
• Current Stage: PPUB - Publication issued
• Start Date: 10-Sep-2007
• Completion Date: 30-Nov-2007

Standards Content (Sample)

IEC/TS 62215-2
Edition 1.0 2007-09
TECHNICAL
SPECIFICATION
Integrated circuits – Measurement of impulse immunity –
Part 2: Synchronous transient injection method

IEC/TS 62215-2:2007(E)
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IEC/TS 62215-2
Edition 1.0 2007-09
TECHNICAL
SPECIFICATION
Integrated circuits – Measurement of impulse immunity –
Part 2: Synchronous transient injection method

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
U
ICS 31.200 ISBN 2-8318-9305-4
– 2 – TS 62215-2 © IEC:2007(E)
CONTENTS
FOREWORD.4
INTRODUCTION.6

1 Scope.7
2 Normative references .7
3 Terms and definitions .7
4 General .8
4.1 Introduction .8
4.2 Measurement philosophy.8
4.3 Set-up concept .9
4.4 Response signal.9
4.5 Coupling networks.10
4.5.1 General .10
4.5.2 Design of coupling networks .10
4.5.3 Coupling network for the ground/ V pin(s) .10
ss
4.5.4 Coupling network for the supply/ V pin(s) .11
dd
4.5.5 Coupling network for the I/O pin(s) .13
4.5.6 Coupling network for the reference pins.13
4.5.7 Coupling network verification.14
4.6 Test circuit board .14
4.6.1 General .14
4.6.2 IC pin loading / termination.14
4.6.3 Power supply requirements .15
4.7 IC specific considerations.15
4.7.1 IC supply voltage.15
4.7.2 IC decoupling .15
4.7.3 Activity of IC .15
4.7.4 Guidelines for IC stimulation.15
4.7.5 IC monitoring.15
4.7.6 IC stability over time.15
5 Test conditions .16
5.1 Default test conditions.16
5.1.1 General .16
5.1.2 Ambient conditions .16
5.1.3 Ambient temperature .16
5.2 Impulse immunity of the test set-up .16
6 Test set-up .16
6.1 General .16
6.2 Test equipment .17
6.3 Set-up explanation .17
6.4 Explanation of signal relations.18
6.5 Calculation of time step and number of measurements to be conducted .18
6.6 Test procedure .19
6.7 Monitoring check .19
6.8 System verification .19

TS 62215-2 © IEC:2007(E) – 3 –
7 Test report.20
7.1 General .20
7.2 Immunity limits or levels .20
7.3 Performance classes .20
7.4 Interpretation and comparison of results.20

Annex A (informative) Flow chart of the software used in a microcontroller .21
Annex B (informative) Flow chart for the set-up control S/W (bus control program) .22
Annex C (informative) Test board requirements .23

Bibliography.27

Figure 1 – Synchronous transient injection immunity methodology waveforms .9
Figure 2 – Test set-up diagram for synchronous transient injection immunity testing.10
Figure 3 – Circuit diagram of the coupling network for ground/ V pin(s) of an IC.11
ss
Figure 4 – Method to impose synchronous transient injection into ground/ V pin(s).11
ss
Figure 5 – Circuit diagram of the coupling network for supply/ V pin(s) of an IC .12
dd
Figure 6 – Method to impose synchronous transient injection into supply/ V pin(s) .12

dd
Figure 7 – Method to impose synchronous transient injection into I/O pins.13
Figure 8 – Measurement set-up for synchronous transient injection .16
Figure 9 – The waveforms (not in scale) appearing in the test set-up.18
Figure A.1 – Test code flow chart.21
Figure B.1 – Test measurement flow chart .22
Figure C.1 – Typical test board topology.26

Table 1 – IC pin loading recommendations .14
Table C.1 – Position of vias over the board.23

– 4 – TS 62215-2 © IEC:2007(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
MEASUREMENT OF IMPULSE IMMUNITY –

Part 2: Synchronous transient injection method

FOREWORD
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9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
The main task of IEC technical committees is to prepare International Standards. In
exceptional circumstances, a technical committee may propose the publication of a technical
specification when
• the required support cannot be obtained for the publication of an International
Standard, despite repeated efforts, or
• the subject is still under technical development or where, for any other reason, there is
the future but no immediate possibility of an agreement on an International Standard.
Technical specifications are subject to review within three years of publication to decide
whether they can be transformed into International Standards.
IEC 62215-2, which is a technical specification, has been prepared by subcommittee 47A:
Integrated circuits, of IEC technical committee 47: Semiconductor devices.

TS 62215-2 © IEC:2007(E) – 5 –
The text of this technical specification is based on the following documents:
Enquiry draft Report on voting
47A/762/DTS 47A/769A/RVC
Full information on the voting for the approval of this technical specification can be found in
the report on voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 62215 series, under the general title Integrated circuits –
Measurement of impulse immunity, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• transformed into an International standard,
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.

– 6 – TS 62215-2 © IEC:2007(E)
INTRODUCTION
In future standards, test methods and measurement procedures will be given for transient
immunity of integrated circuits:
– ESD pulse with resemblance to IEC 61000-4-2;
– EFT pulse with resemblance to IEC 61000-4-4;
– Surge pulse with resemblance to IEC 61000-4-5.

TS 62215-2 © IEC:2007(E) – 7 –
INTEGRATED CIRCUITS –
MEASUREMENT OF IMPULSE IMMUNITY –

Part 2: Synchronous transient injection method

1 Scope
IEC/TS 62215-2, which is a technical specification, contains general information and
definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast
conducted synchronous transient disturbances. This information is followed by a description
of measurement conditions, test equipment and test set-up as well as the test procedures and
the requirements on the content of the test report.
The objective of this technical specification is to describe general conditions to obtain a
quantitative measure of immunity of ICs establishing a uniform testing environment. Critical
parameters that are expected to influence the test results are described. Deviations from this
specification should be explicitly noted in the individual test report.
This synchronous transient immunity measurement method, as described in this specification,
uses short impulses with fast rise times of different amplitude, duration and polarity in a
conductive mode to the IC. In this method, the applied impulse should be synchronized with
the activity of the IC to make sure that controlled and reproducible conditions can be assured.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 61967-4, Integrated circuits – Measurement of electromagnetic emissions, 150 kHz to
1 GHz – Part 4: Measurement of conducted emissions – 1 Ω/150 Ω direct coupling method
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 62215-1 (in
preparation), as well as the following, apply.
3.1
auxiliary equipment
AE
equipment not under test that is nevertheless indispensable for setting up all the functions
and assessing the correct performance (operation) of the equipment under test (EUT) during
its exposure to the disturbance
3.2
coupling network
electrical circuit for transferring energy from one circuit to another with well-defined
impedance and known transfer characteristics
3.3
device under test
DUT
device, equipment or system being evaluated

– 8 – TS 62215-2 © IEC:2007(E)
NOTE In this technical specification, it refers to a semiconductor device being tested.
3.4
electromagnetic compatibility
EMC
ability of an equipment or system to function satisfactorily in its electromagnetic environment
without introducing intolerable electromagnetic disturbance to anything in that environment
[IEC 60050(161):1990, definition 161-01-07]
3.5
electrical noise
unwanted electrical signals, which produce undesirable effects in the circuits of the control
system in which they occur
[IEEE std 100-1992-518-1982]
3.6
immunity (to a disturbance)
ability of a device, equipment or system to perform without degradation in the presence of an
electromagnetic disturbance
3.7
jitter (time related)
short-term variations of the significant instants of a digital signal from their ideal positions in
time
3.8
RF ambient
totality of electromagnetic phenomena existing at a given location
3.9
transient
pertaining to or designating a phenomenon or a quantity which varies between two
consecutive steady states during a time interval which is short compared with the time-scale
of interest
[IEC 60050(161):1990, definition 161-02-01]
4 General
4.1 Introduction
This immunity test method describes synchronous transient injection on digital and mixed-
signal ICs. In this method an impulse is injected into the V -, V -pin(s) or I/Os successively
ss dd
on the IC subjected to the test.
4.2 Measurement philosophy
This method is related to the 1 Ω resistor method, see IEC 61967-4. In this method a 1 Ω
resistor is added in series with the V , V pin(s) of the IC. It is assumed that the voltage
dd ss
drop across the 1 Ω resistor in parallel with the DC by-pass inductance is very small. For
injecting the impulse, a broadband coupling network is defined. The impulse injection is
synchronized to a program loop signal generated by the IC.
One cycle of this response signal is considered as one program loop. The aim of this
measurement method is to insert a synchronous but delayed impulse into the IC, related to
the program loop. The total time of one program loop period is calculated and then it is

TS 62215-2 © IEC:2007(E) – 9 –
divided into small time steps. At every delay step, a single impulse per program loop is
inserted into the IC and its response is measured.

Clock
signal
Program
loop
signal
Program loop
τ
Adjustable delay delay
pulse generator
Impulse
signal
IEC  1712/07
Figure 1 – Synchronous transient injection immunity methodology waveforms
Figure 1 shows the relevant signals occurring in this synchronous transient immunity test. The
clock signal is used to run the digital IC and the program loop signal is used as a reference
and response signal. A predetermined adjustable delay is used to shift the impulse delay time;
τ , along the program loop.; τ is typically a fraction (≤ 0,1) of the rise time of the clock
delay delay
signal. The rising edge of the program loop signal, synchronized with the rising edge of the
clock signal, is considered as a fixed reference point, see Figure 1, second line; program loop
sync circuitry. Thereafter, the impulse is inserted and the edges of the response signals have
to be observed. After every program loop, the delay step is increased and the injection
moment of the impulse is shifted. In this way, the full scan can be completed through the
program cycle to evaluate the impulse immunity.
The test method will show sensitive time windows, i.e. modes of operation at which the device
is sensitive. The non-sensitive time windows can be skipped thereafter while repeating the
measurements.
NOTE This measurement methodology is different from to the stochastic i.e. random application of impulses.
4.3 Set-up concept
In Figure 2, the block diagram of the test set-up for the synchronous impulse immunity test is
given. A trigger signal, e.g. generated by the DUT, is used as an indication to start the
measurement. This signal is also used to trigger the delay pulse generator to produce the
programmable delay. The delayed pulse triggers the impulse generator that produces an
impulse. This impulse is then inserted into the DUT through a suitable coupling network.
Measurement equipment such as an oscilloscope or time domain analyser is used to measure
the response of the DUT versus the delay of the impulse in the program loop. This measuring
equipment is also synchronized with the test signal to acquire the response data over a
program loop. A computer interface is used to control the measurement test set-up and to
acquire the response data from the test set-up.
In general, the test set-up shall be in accordance with the specific test procedure as
described in the future IEC 62215-1. All the test relevant parameters shall be recorded as
exactly as possible to ensure that the test results become reproducible.
4.4 Response signal
The response signal is a signal generated by the IC under test (DUT). A clock signal may be
externally provided. If the DUT is a microcontroller, then the response signal can be

– 10 – TS 62215-2 © IEC:2007(E)
generated by a microcontroller by loading a small software program. If DUT is a logic device,
then the output signal of the logic device is considered as the response signal. The immunity
can be quantified based on jitter occurring in the response signal (or any other errors) due to
the impulse disturbances applied.
Trigger
Program loop signal Delay
sync circuit generator
Program
loop signal
Impulse
signal
Clock Coupling Impulse
DUT
generator network generator
GPIB
bus
Measurement
equipment
Computer
IEC  1713/07
Figure 2 – Test set-up diagram for synchronous transient injection immunity testing
4.5 Coupling networks
4.5.1 General
The coupling network will always introduce a time delay for the applied impulse signal since a
network presents a path (line) of a certain physical length for the signal.
4.5.2 Design of coupling networks
For synchronous transient immunity testing, it is important that the coupling networks have a
flat transfer characteristics over a broad frequency range. This flatness will help to couple the
impulse to the DUT without disturbing its impulse characteristics and will maintain the normal
operating conditions of the DUT. The coupling networks are designed in such a way that the
impulses of different amplitude, duration, rise and fall time can be injected into the DUT ports.
4.5.3 Coupling network for the ground/ V pin(s)
ss
pin(s) is via a 1 Ω resistor
The principle used to couple the impulse into the ground/ V
ss
connected in series with a ground pin(s) of the IC and where the impulse signal is applied in
series equivalently. Figure 3 shows an example of a coupling network.
Two 4:1 transmission line (Guanella) transformers are used. A resistor network follows these
two transformers together with an RF choke. When the two TL (transmission line)
transformers having impedance ratio 4:1 are connected in series, it results in an impedance
step down from 50 Ω to about 3 Ω. The resistor network of 3 Ω is connected as an RF load.
To minimize the DC voltage drop across the 1 Ω resistor, an RF choke of 10 μH is connected
in parallel. This inductor acts as a DC short-circuit and represents high impedance for the
impulse signal which is referred to a parallel impedance of 1 Ω. The overall attenuation in the
coupling network is approximately 22 dB; 6 dB attenuation by each transformer and 10 dB by
the resistive network.
TS 62215-2 © IEC:2007(E) – 11 –
2 Ω
Transformer #1 Transformer #2
2 Ω
2 Ω
10 μH
Ground
IEC  1714/07
Figure 3 – Circuit diagram of the coupling network for ground/ V pin(s) of an IC
ss
While designing the coupling network, care should be taken that the transfer characteristic is
flat enough (-3 dB) over the bandwidth of 1 MHz to 1 GHz.
V supply
dd
V
dd
Coupling network
DUT
2 Ω
Transformer #1 Transformer #2
2 Ω V
ss
50 Ω
2 Ω
10 μH
Ground
IEC  1715/07
Figure 4 – Method to impose synchronous transient injection into ground/ V pin(s)
ss
When an impulse is applied to the coupling network, the impulse energy appears across the
1 Ω resistor with a 22 dB attenuation. Since this 1 Ω resistor is in series with the ground/ V
ss
pin(s) of the DUT, i.e. the IC, it suffers from such an impulse disturbance. Figure 4 shows how
the coupling network is connected to the IC.
pin(s)
4.5.4 Coupling network for the supply/ V
dd
To couple an impulse to the supply/ V pin(s), one can use the same coupling network as
dd
used for the ground pin(s), but with a modification as shown in Figure 5 to by-pass the DC
voltage on the supply/ V .
dd
Z = 50 Ω
in
Z = 1 Ω
out
– 12 – TS 62215-2 © IEC:2007(E)
DC decoupling
2 Ω
Transformer #1 Transformer #2
2 Ω
2 Ω
10 μH
Ground
V
dd
supply
IEC  1716/07
Figure 5 – Circuit diagram of the coupling network for supply/ V pin(s) of an IC
dd
The coupling network incorporating the TL transformer and the 1 Ω resistor network is the
same as in the ground pin(s) coupling network, but only one DC decoupling capacitor is
added between the transformer and the resistor network. This capacitor will pass the impulse
circuit; however it decouples the DC voltages to pass towards the
to the supply/ V
dd
transformers (which might cause saturation of the core material used). The decoupling
capacitors play a very important roll to have the RF return path for the impulse.
The RF choke provides the necessary DC by-pass for the high supply/ V current. An RF
dd
lossy inductor and the high pass capacitor will ensure that the impulse does not influence the
rest of the supply system. The overall attenuation in the coupling network is again 22 dB
approximately, 6 dB attenuation by each transformer and 10 dB by the resistive network. The
transfer characteristic of the coupling network needs to be flat (–3 dB) over a frequency range
of 1 MHz to 1 GHz.
DC decoupling
2 Ω
Transformer #1 Transformer #2
2 Ω
V
dd
50 Ω
2 Ω
DUT
V
ss
Ground
V
dd
supply
IEC  1717/07
Figure 6 – Method to impose synchronous transient injection into supply/ V pin(s)

dd
Figure 6 gives a schematic diagram on the method to insert an impulse into the supply/ V
dd
pin(s) of the IC. When an impulse is applied to the coupling network, it will be superimposed
in series with the supply voltage and this total voltage is applied to a supply pin of the digital/
mixed-signal IC. The coupling network is designed in such a way that the impulse energy will
be inserted into the supply/ V pin of IC and will not be reflected back to the main power
dd
supply.
Since the coupling network has approximately 22 dB attenuation, to get a 4 V to 5 V impulse
amplitude across a 1 Ω resistor, the amplitude of the input impulse should be in the range of
48 V to 60 V.
...