Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions

IEC 61691-6:2021(E) defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models. This standard is published as a double logo IEC-IEEE standard.

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Status
Published
Publication Date
07-Jun-2021
Current Stage
PPUB - Publication issued
Completion Date
08-Jun-2021
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IEC 61691-6:2021 - Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
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IEC 61691-6
Edition 2.0 2021-06
IEEE Std 1076.1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
IEC 61691-6:2021-06(en) IEEE Std 1076.1-2017
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---------------------- Page: 2 ----------------------
IEC 61691-6
Edition 2.0 2021-06
IEEE Std 1076.1™
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01; 35.060 ISBN 978-2-8322-9830-5

Warning! Make sure that you obtained this publication from an authorized distributor.

® Registered trademark of the International Electrotechnical Commission
---------------------- Page: 3 ----------------------
IEC 61691-6:2021 © IEC 2021
IEEE Std 1076.1™-2017
Contents

1. Overview............................................................................................................................................ 15

1.1 Scope....................................................................................................................................... 15

1.2 Purpose.................................................................................................................................... 15

1.3 Structure and terminology of this standard ............................................................................. 15

2. Normative references......................................................................................................................... 18

3. Design entities and configurations..................................................................................................... 19

3.1 General.................................................................................................................................... 19

3.2 Entity declarations................................................................................................................... 19

3.3 Architecture bodies ................................................................................................................. 22

3.4 Configuration declarations...................................................................................................... 25

4. Subprograms and packages................................................................................................................ 32

4.1 General.................................................................................................................................... 32

4.2 Subprogram declarations......................................................................................................... 32

4.3 Subprogram bodies ................................................................................................................. 36

4.4 Subprogram instantiation declarations.................................................................................... 39

4.5 Subprogram overloading......................................................................................................... 40

4.6 Resolution functions ............................................................................................................... 42

4.7 Package declarations ............................................................................................................... 43

4.8 Package bodies........................................................................................................................ 45

4.9 Package instantiation declarations .......................................................................................... 46

4.10 Conformance rules .................................................................................................................. 47

5. Types and natures .............................................................................................................................. 48

5.1 General.................................................................................................................................... 48

5.2 Scalar types ............................................................................................................................. 49

5.3 Composite types...................................................................................................................... 57

5.4 Access types............................................................................................................................ 67

5.5 File types................................................................................................................................. 69

5.6 Protected types ........................................................................................................................ 72

5.7 String representations.............................................................................................................. 75

5.8 Natures .................................................................................................................................... 76

6. Declarations ....................................................................................................................................... 81

6.1 General.................................................................................................................................... 81

6.2 Type declarations .................................................................................................................... 82

6.3 Subtype declarations ............................................................................................................... 82

6.4 Objects .................................................................................................................................... 84

6.5 Interface declarations .............................................................................................................. 95

6.6 Alias declarations.................................................................................................................. 113

6.7 Attribute declarations............................................................................................................ 116

6.8 Component declarations........................................................................................................ 117

6.9 Group template declarations ................................................................................................. 117

6.10 Group declarations ................................................................................................................ 117

Copyright © 2018 IEEE. All rights reserved.
Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.
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IEC 61691-6:2021 © IEC 2021
IEEE Std 1076.1™-2017

6.11 Nature and subnature declarations ........................................................................................ 118

6.12 PSL clock declarations.......................................................................................................... 119

7. Specifications................................................................................................................................... 120

7.1 General.................................................................................................................................. 120

7.2 Attribute specification........................................................................................................... 120

7.3 Configuration specification................................................................................................... 123

7.4 Disconnection specification ..................................................................................................129

7.5 Step limit specification.......................................................................................................... 131

8. Names .............................................................................................................................................. 134

8.1 General.................................................................................................................................. 134

8.2 Simple names ........................................................................................................................ 135

8.3 Selected names...................................................................................................................... 136

8.4 Indexed names....................................................................................................................... 138

8.5 Slice names ........................................................................................................................... 139

8.6 Attribute names ..................................................................................................................... 139

8.7 External names...................................................................................................................... 140

9. Expressions ...................................................................................................................................... 144

9.1 General.................................................................................................................................. 144

9.2 Operators............................................................................................................................... 145

9.3 Operands ............................................................................................................................... 158

9.4 Static expressions.................................................................................................................. 166

9.5 Universal expressions ........................................................................................................... 170

9.6 Linear forms.......................................................................................................................... 170

10 Sequential statements....................................................................................................................... 173

10.1 General.................................................................................................................................. 173

10.2 Wait statement....................................................................................................................... 173

10.3 Assertion statement ............................................................................................................... 175

10.4 Report statement ................................................................................................................... 176

10.5 Signal assignment statement .................................................................................................177

10.6 Variable assignment statement.............................................................................................. 188

10.7 Procedure call statement ....................................................................................................... 192

10.8 If statement............................................................................................................................ 192

10.9 Case statement....................................................................................................................... 193

10.10 Loop statement...................................................................................................................... 195

10.11 Next statement....................................................................................................................... 195

10.12 Exit statement........................................................................................................................ 196

10.13 Return statement ................................................................................................................... 196

10.14 Null statement ....................................................................................................................... 197

10.15 Break statement..................................................................................................................... 197

11. Architecture statements.................................................................................................................... 198

11.1 General.................................................................................................................................. 198

11.2 Block statement..................................................................................................................... 199

11.3 Process statement .................................................................................................................. 200

11.4 Concurrent procedure call statements ................................................................................... 202

Copyright © 2018 IEEE. All rights reserved.
Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.
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IEC 61691-6:2021 © IEC 2021
iii
IEEE Std 1076.1™-2017

11.5 Concurrent assertion statements............................................................................................ 203

11.6 Concurrent signal assignment statements ............................................................................. 204

11.7 Component instantiation statements ..................................................................................... 206

11.8 Generate statements .............................................................................................................. 212

11.9 Concurrent break statement ..................................................................................................214

11.10 Simple simultaneous statement............................................................................................. 215

11.11 Simultaneous if statement ..................................................................................................... 216

11.12 Simultaneous case statement................................................................................................. 216

11.13 Simultaneous procedural statement ...................................................................................... 217

11.14 Simultaneous null statement ................................................................................................. 220

12. Scope and visibility.......................................................................................................................... 221

12.1 Declarative region ................................................................................................................. 221

12.2 Scope of declarations ............................................................................................................ 221

12.3 Visibility................................................................................................................................ 223

12.4 Use clauses............................................................................................................................ 227

12.5 The context of overload resolution ....................................................................................... 228

13. Design units and their analysis ........................................................................................................ 230

13.1 Design units........................................................................................................................... 230

13.2 Design libraries ..................................................................................................................... 230

13.3 Context declarations.............................................................................................................. 232

13.4 Context clauses ..................................................................................................................... 232

13.5 Order of analysis ................................................................................................................... 233

14. Elaboration and execution ............................................................................................................... 234

14.1 General.................................................................................................................................. 234

14.2 Elaboration of a design hierarchy ......................................................................................... 234

14.3 Elaboration of a block, package, or subprogram header....................................................... 238

14.4 Elaboration of a declarative part ...........................................................................................241

14.5 Elaboration of a statement part .............................................................................................246

14.6 Dynamic elaboration ............................................................................................................. 250

14.7 Execution of a model ............................................................................................................ 251

14.8 Time and the analog solver ................................................................................................... 266

14.9 Frequency and noise calculation ........................................................................................... 267

15. Lexical elements .............................................................................................................................. 269

15.1 General.................................................................................................................................. 269

15.2 Character set.......................................................................................................................... 269

15.3 Lexical elements, separators, and delimiters ........................................................................ 271

15.4 Identifiers .............................................................................................................................. 273

15.5 Abstract literals ..................................................................................................................... 274

15.6 Character literals ................................................................................................................... 275

15.7 String literals ......................................................................................................................... 275

15.8 Bit string literals.................................................................................................................... 276

15.9 Comments ............................................................................................................................. 278

15.10 Reserved words ..................................................................................................................... 279

15.11 Tool directives....................................................................................................................... 281

Copyright © 2018 IEEE. All rights reserved.
Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.
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IEC 61691-6:2021 © IEC 2021
IEEE Std 1076.1™-2017

16. Predefined language environment ................................................................................................... 282

16.1 General.................................................................................................................................. 282

16.2 Predefined attributes ............................................................................................................. 282

16.3 Package STANDARD........................................................................................................... 304

16.4 Package TEXTIO.................................................................................................................. 319

16.5 Standard environment package ............................................................................................. 325

16.6 Standard mathematical packages .......................................................................................... 326

16.7 Standard multivalue logic package ....................................................................................... 327

16.8 Standard synthesis packages .................................................................................................327

16.9 Standard synthesis context declarations................................................................................ 333

16.10 Fixed-point package.............................................................................................................. 334

16.11 Floating-point package.......................................................................................................... 334

16.12 Standard packages for multiple energy domain support....................................................... 335

17. VHDL Procedural Interface overview............................................................................................. 336

17.1 General.................................................................................................................................. 336

17.2 Organization of the interface................................................................................................. 336

17.3 Capability sets....................................................................................................................... 337

17.4 Handles.................................................................................................................................. 339

18. VHPI access functions ..................................................................................................................... 341

18.1 General.................................................................................................................................. 341

18.2 Information access functions ................................................................................................341

18.3 Property access functions...................................................................................................... 343

18.4 Access by name function ...................................................................................................... 344

19. VHPI information model ................................................................................................................. 345

19.1 General.................................................................................................................................. 345

19.2 Formal notation ..................................................................................................................... 345

19.3 Class inheritance hierarchy ................................................................................................... 346

19.4 Name properties .................................................................................................................... 347

19.5 The stdUninstantiated package ............................................................................................. 360

19.6 The stdHierarchy package..................................................................................................... 363

19.7 The stdTypes package........................................................................................................... 370

19.8 The stdExpr package............................................................................................................. 372

19.9 The stdSpec package............................................................................................................. 375

19.10 The stdSubprograms package ............................................................................................... 377

19.11 The stdStmts package............................................................................................................ 379

19.12 The stdConnectivity package ................................................................................................385

19.13 The stdCallbacks package..................................................................................................... 390

19.14 The stdEngine package ......................................................................................................... 391

19.15 The stdForeign package ........................................................................................................ 391

19.16 The stdMeta package ............................................................................................................ 391

19.17 The stdTool package ............................................................................................................. 393

19.18 Application contexts ............................................................................................................. 394

20. VHPI tool execution ........................................................................................................................ 395

20.1 General.................................................................................................................................. 395

20.2 Registration phase ................................................................................................................. 395

Copyright © 2018 IEEE. All rights reserved.
Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.
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IEC 61691-6:2021 © IEC 2021
IEEE Std 1076.1™-2017

20.3 Analysis phase....................................................................................................................... 401

20.4 Elaboration phase.................................................................................................................. 401

20.5 Initialization phase ................................................................................................................ 403

20.6 Simulation phase ................................................................................................................... 403

20.7 Save phase............................................................................................................................. 403

20.8 Restart phase ......................................................................................................................... 404

20.9 Reset phase................................................................................................

...

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