IEC 61691-6:2021
(Main)Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
IEC 61691-6:2021(E) defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models. This standard is published as a double logo IEC-IEEE standard.
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IEC 61691-6 ®
Edition 2.0 2021-06
™
IEEE Std 1076.1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
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IEC 61691-6 ®
Edition 2.0 2021-06
IEEE Std 1076.1™
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01; 35.060 ISBN 978-2-8322-9830-5
i
IEEE Std 1076.1™-2017
Contents
1. Overview. 15
1.1 Scope. 15
1.2 Purpose. 15
1.3 Structure and terminology of this standard . 15
2. Normative references. 18
3. Design entities and configurations. 19
3.1 General. 19
3.2 Entity declarations. 19
3.3 Architecture bodies . 22
3.4 Configuration declarations. 25
4. Subprograms and packages. 32
4.1 General. 32
4.2 Subprogram declarations. 32
4.3 Subprogram bodies . 36
4.4 Subprogram instantiation declarations. 39
4.5 Subprogram overloading. 40
4.6 Resolution functions . 42
4.7 Package declarations . 43
4.8 Package bodies. 45
4.9 Package instantiation declarations . 46
4.10 Conformance rules . 47
5. Types and natures . 48
5.1 General. 48
5.2 Scalar types . 49
5.3 Composite types. 57
5.4 Access types. 67
5.5 File types. 69
5.6 Protected types . 72
5.7 String representations. 75
5.8 Natures . 76
6. Declarations . 81
6.1 General. 81
6.2 Type declarations . 82
6.3 Subtype declarations . 82
6.4 Objects . 84
6.5 Interface declarations . 95
6.6 Alias declarations. 113
6.7 Attribute declarations. 116
6.8 Component declarations. 117
6.9 Group template declarations . 117
6.10 Group declarations . 117
Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.
ii
IEEE Std 1076.1™-2017
6.11 Nature and subnature declarations . 118
6.12 PSL clock declarations. 119
7. Specifications. 120
7.1 General. 120
7.2 Attribute specification. 120
7.3 Configuration specification. 123
7.4 Disconnection specification .129
7.5 Step limit specification. 131
8. Names . 134
8.1 General. 134
8.2 Simple names . 135
8.3 Selected names. 136
8.4 Indexed names. 138
8.5 Slice names . 139
8.6 Attribute names . 139
8.7 External names. 140
9. Expressions . 144
9.1 General. 144
9.2 Operators. 145
9.3 Operands . 158
9.4 Static expressions. 166
9.5 Universal expressions . 170
9.6 Linear forms. 170
10 Sequential statements. 173
10.1 General. 173
10.2 Wait statement. 173
10.3 Assertion statement . 175
10.4 Report statement . 176
10.5 Signal assignment statement .177
10.6 Variable assignment statement. 188
10.7 Procedure call statement . 192
10.8 If statement. 192
10.9 Case statement. 193
10.10 Loop statement. 195
10.11 Next statement. 195
10.12 Exit statement. 196
10.13 Return statement . 196
10.14 Null statement .
...
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