IEC TR 63051:2017
(Main)Documentation on design automation subjects - Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)
Documentation on design automation subjects - Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)
IEC TR 63051:2017(E) describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.
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IEC TR 63051 ®
Edition 1.0 2017-01
TECHNICAL
REPORT
colour
inside
Documentation on design automation subjects – Mathematical algorithm
hardware description languages for system level modeling and verification
(HDLMath)
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IEC TR 63051 ®
Edition 1.0 2017-01
TECHNICAL
REPORT
colour
inside
Documentation on design automation subjects – Mathematical algorithm
hardware description languages for system level modeling and verification
(HDLMath)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01; 35.240.50 ISBN 978-2-8322-3772-4
– 2 – IEC TR 63051:2017 © IEC 2017
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Definition and positioning of HDLMath . 7
4.1 General . 7
4.2 Current HDLMaths . 7
4.3 Design abstraction level of HDLMath . 8
5 Functional requirements of HDLMath . 9
5.1 General . 9
5.2 Mathematical expressions . 9
5.3 Various kinds of precision computation . 10
5.4 Exception and error handling . 10
5.5 Multi-dimensional arrays . 11
5.6 Mathematical functions . 11
5.7 Mixed numerical and symbolic computations . 12
5.8 Feedback process . 12
5.9 User-defined functions in C-code . 13
5.10 Verification environment . 14
6 Comparison of current HDLMath languages . 14
7 Conclusion . 15
Bibliography . 16
Figure 1 – Numbers of description lines . 9
Figure 2 – Examples of mathematical expressions . 10
Figure 3 – Multi-dimensional arrays and mathematical functions in HDLMath1 . 11
Figure 4 – Multi-dimensional arrays and mathematical functions in HDLMath2 . 12
Figure 5 – Mixed numerical and symbolic computations in HDLMath1 and HDLMath2 . 12
Figure 6 – Example of a feedback process . 12
Figure 7 – Example of feedback process in HDLMath1 and HDLMath2 . 13
Figure 8 – Examples of user-defined functions in C-code in HDLMath1 and HDLMath2 . 13
Figure 9 – Structure of test-bench description of HDLMath1 and HDLMath2 . 14
Table 1 – Examples of mathematics applications . 5
Table 2 – Examples of precision type . 10
Table 3 – Examples of overflow handling . 11
Table 4 – Comparison of current HDLMaths . 15
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DOCUMENTATION ON DESIGN AUTOMATION SUBJECTS –
MATHEMATICAL ALGORITHM HARDWARE DESCRIPTION LANGUAGES
FOR SYSTEM LEVEL MODELING AND VERIFICATION (HDLMath)
FOREWORD
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IEC 63051, which is a Technical Report, has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this Technical Report is based on the following documents:
Enquiry draft Report on voting
91/1349/DTR 91/1396/RVC
Full information on the voting for the approval of this Technical Report can be found in the report
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– 4 – IEC TR 63051:2017 © IEC 2017
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INTRODUCTION
Around the world, engineers in industries such as electronics and automobiles are developing
many kinds of systems and products. However, these are developed based on conventional
design processes and suffer from many design problems and long design times. Because the
laws of nature can be expressed mathematically, mathematics is a good algorithmic method for
the description and modeling of such systems. Mathematical modeling is also an important
approach for both solving problems and visualizing the abstract concepts involved.
System LSI (Large Scale Integration) can be described at three levels of complexity as follows:
1) The the algorithmic level, which specifies only the algorithm used by the hardware for the
problem solution;
2) the register transfer level, in which the registers are system elements and the data transfer
between these registers is specified according to some rule;
3) the circuit level, where gates and flip-flops are replaced by the circuit elements such as
transistors, diodes, resistors, etc.
For levels 2) and 3), VHDL (IEC 61691-1-1:2011 [1] ) and SystemVerilog (IEC 62530:2011[2])
have already been standardized by the IEC and IEEE and have been in practical use for over
twenty years.
For level 1), System C is able to describe hardware systems at the behavioral level.
The purpose of this document is to accelerate the standardization of a mathematical algorithm
description language (HDLMath). HDLMath will be used to describe and verify the entire
behavior of systems and/or products using mathematical algorithms of electronic systems. It is
a higher level language than conventional HDL (Hardware Descripti
...
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