IEC 63378-3:2025

Thermal standardization on semiconductor packages - Part 3: Thermal circuit simulation models of discrete semiconductor packages for transient analysis

IEC 63378-3:2025 specifies the thermal circuit network model of discrete (TO‑243, TO‑252 and TO‑263) packages, which is used in the transient analysis of electronic devices to estimate precise junction temperatures without experimental verification.
This model is intended to be made and provided by semiconductor suppliers and to be used by assembly makers of electronic devices.

Normalisation thermique des boîtiers de semiconducteurs - Partie 3: Modèles de simulation de circuits thermiques de boîtiers de semiconducteurs discrets pour analyse transitoire

L’IEC 63378-3:2025 spécifie le modèle de réseau de circuits thermiques des boîtiers discrets (TO‑243, TO‑252 et TO‑263), qui est utilisé dans l’analyse transitoire des dispositifs électroniques pour estimer avec précision les températures de jonction sans vérification expérimentale.
Ce modèle est destiné à être fabriqué et fourni par les fournisseurs de semiconducteurs, et à être utilisé par les assembleurs de dispositifs électroniques.

General Information

• Status: Published
• Publication Date: 05-May-2025
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: SC 47D - Semiconductor devices packaging
• Drafting Committee: WG 2 - TC 47/SC 47D/WG 2
• Current Stage: PPUB - Publication issued
• Start Date: 06-May-2025
• Completion Date: 28-May-2025

Standards Content (Sample)

IEC 63378-3 ®
Edition 1.0 2025-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Thermal standardization on semiconductor packages –
Part 3: Thermal circuit simulation models of discrete semiconductor packages
for transient analysis
Normalisation thermique des boîtiers de semiconducteurs –
Partie 3: Modèles de simulation de circuits thermiques de boîtiers de
semiconducteurs discrets pour analyse transitoire
ICS 31.080.01  ISBN 978-2-8327-0399-1

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or
by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either
IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC copyright
or have an enquiry about obtaining additional rights to this publication, please contact the address below or your local
IEC member National Committee for further information.

Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduite ni
utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopie et
les microfilms, sans l'accord écrit de l'IEC ou du Comité national de l'IEC du pays du demandeur. Si vous avez des
questions sur le copyright de l'IEC ou si vous désirez obtenir des droits supplémentaires sur cette publication, utilisez
les coordonnées ci-après ou contactez le Comité national de l'IEC de votre pays de résidence.

IEC Secretariat Tel.: [phone]
3, rue de Varembé [e-mail]
CH-1211 Geneva 20 www.iec.ch
Switzerland
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigendum or an amendment might have been published.

IEC publications search - IEC Products & Services Portal - products.iec.ch
webstore.iec.ch/advsearchform Discover our powerful search engine and read freely all the
The advanced search enables to find IEC publications by a publications previews, graphical symbols and the glossary.
variety of criteria (reference number, text, technical With a subscription you will always have access to up to date
committee, …). It also gives information on projects, content tailored to your needs.

replaced and withdrawn publications.
Electropedia - www.electropedia.org
IEC Just Published - webstore.iec.ch/justpublished The world's leading online dictionary on electrotechnology,
Stay up to date on all new IEC publications. Just Published containing more than 22 500 terminological entries in English
details all new publications released. Available online and and French, with equivalent terms in 25 additional languages.
once a month by email. Also known as the International Electrotechnical Vocabulary
(IEV) online.
IEC Customer Service Centre - webstore.iec.ch/csc
If you wish to give us your feedback on this publication or
need further assistance, please contact the Customer
Service Centre: [e-mail].
A propos de l'IEC
La Commission Electrotechnique Internationale (IEC) est la première organisation mondiale qui élabore et publie des
Normes internationales pour tout ce qui a trait à l'électricité, à l'électronique et aux technologies apparentées.

A propos des publications IEC
Le contenu technique des publications IEC est constamment revu. Veuillez vous assurer que vous possédez l’édition la
plus récente, un corrigendum ou amendement peut avoir été publié.

Recherche de publications IEC -  IEC Products & Services Portal - products.iec.ch
webstore.iec.ch/advsearchform Découvrez notre puissant moteur de recherche et consultez
La recherche avancée permet de trouver des publications gratuitement tous les aperçus des publications, symboles
IEC en utilisant différents critères (numéro de référence, graphiques et le glossaire. Avec un abonnement, vous aurez
texte, comité d’études, …). Elle donne aussi des toujours accès à un contenu à jour adapté à vos besoins.
informations sur les projets et les publications remplacées
ou retirées. Electropedia - www.electropedia.org
Le premier dictionnaire d'électrotechnologie en ligne au
IEC Just Published - webstore.iec.ch/justpublished monde, avec plus de 22 500 articles terminologiques en
Restez informé sur les nouvelles publications IEC. Just anglais et en français, ainsi que les termes équivalents
Published détaille les nouvelles publications parues. dans 25 langues additionnelles. Egalement appelé
Disponible en ligne et une fois par mois par email. Vocabulaire Electrotechnique International (IEV) en ligne.

Service Clients - webstore.iec.ch/csc
Si vous désirez nous donner des commentaires sur cette
publication ou si vous avez des questions contactez-
nous: [e-mail].
– 2 – IEC 63378-3:2025 © IEC 2025
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Procedure of thermal circuit network model . 6
4.1 General . 6
4.2 Detailed model analysis . 6
4.3 Delphi model preparation . 9
4.4 Thermal circuit model topology . 9
4.5 Determination of thermal capacitance values . 10
Annex A (normative) Validation for TO-252 case . 13
A.1 General . 13
A.2 Simulation parameters . 13
A.3 Comparison of detailed thermal model versus D2elphi model . 13
Bibliography . 15

Figure 1 – Two-resistor model. 6
Figure 2 – Delphi model . 6
Figure 3 – Detailed model (example) . 7
Figure 4 – PCB model . 8
Figure 5 – Simulation volume . 8
Figure 6 – Topology . 10
Figure A.1 – Heatsink model . 13

Table 1 – Dimensions and material properties of detailed model (Example) . 7
Table 2 – Dimensions and material properties of PCB model . 8
Table 3 – Thermal capacitance of the portions (Example) . 10
Table 4 – Thermal capacitance assignment . 11
Table 5 – The combination of α, β, γ (example) . 11
Table A.1 – Comparison with detailed thermal model and D2elphi model . 14

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES –

Part 3: Thermal circuit simulation models of discrete
semiconductor packages for transient analysis

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
Publicly Available Specifications (PAS) and Guides (hereafter referred to as "IEC Publication(s)"). Their
preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
may participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence between
any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
respect thereof. As of the date of publication of this document, IEC had not received notice of (a) patent(s), which
may be required to implement this document. However, implementers are cautioned that this may not represent
the latest information, which may be obtained from the patent database available at https://patents.iec.ch. IEC
shall not be held responsible for identifying any or all such patent rights.
IEC 63378-3 has been prepared by subcommittee 47D: Semiconductor devices packaging, of
IEC technical committee 47: Semiconductor devices. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47D/967/CDV 47D/979/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.

– 4 – IEC 63378-3:2025 © IEC 2025
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 63378 series, published under the general title Thermal
standardization on semiconductor packages, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES –

Part 3: Thermal circuit simulation models of discrete
semiconductor packages for transient analysis

1 Scope
This part of IEC 63378 specifies the thermal circuit network model of discrete (TO-243, TO-252
and TO-263) packages, which is used in the transient analysis of electronic devices to estimate
precise junction temperatures without experimental verification.
This model is intended to be made and provided by semiconductor suppliers and to be used by
assembly makers of electronic devices.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
3.1
detailed model
semiconductor package model which has both the geometrical dimensions of each portion, such
as die or moulding or lead, and the material properties, for thermal analysis
Note 1 to entry: This model is often simplified to some extent.
3.2
thermal circuit network model
RC network model
thermal model of semiconductor packages which comprises multiple nodes, thermal resistances
between nodes and thermal capacitances for each node
3.3
thermal resistance model
thermal circuit network model which is composed of multiple nodes and resistances between
nodes for steady-state analysis
3.4
two-resistor model
thermal resistance model which has three nodes and two resistances
Note 1 to entry: Figure 1 shows this model.

– 6 – IEC 63378-3:2025 © IEC 2025

Figure 1 – Two-resistor model
3.5
Delphi model
thermal resistance model in which multiple resistors are connected in two dimensions
Note 1 to entry: Figure 2 shows the basic type of this model which contains six nodes and nine resistances.

Figure 2 – Delphi model
4 Procedure of thermal circuit network model
4.1 General
Clause 4 describes how a conventional Delphi model is transformed into a proposed transient
model. The procedure is described using a specific package as an "example".
4.2 Detailed model analysis
At first, the thermal analysis using the detailed model shall be done in order to obtain the profile
of semiconductor temperature versus time. The power (heat quantity) shall be constant.
The detailed example model is shown in Figure 3. This model is composed of a moulding, a
semiconductor die, a die attach, a heat spreader and leads.

Figure 3 – Detailed model (example)
The dimensions and material properties shall then be prepared as shown in Table 1.
Table 1 – Dimensions and material properties of detailed model (Example)
Thermal
Material Size Density Specific heat
conductivity
3 3
(W/m∙K) (J/kg∙K)
(mm ) (kg/m )
Semiconductor die 2,0 × 2,0 × 0,3 117,5 2 330 700
Die attach 2,0 × 2,0 × 0,025 50,0 14 500 151
Moulding 6,1 × 6,54 × 2,29 0,649 1 840 882
4,32 × 4,32 × 0,67
Heat spreader 301,5 8 900 385
1,08 × 5,21 × 0,67
Width: 0,76
Lead 188 8 900 410
Thickness: 0,51
This package model shall be mounted on a printed circuit board (PCB) model. The PCB model
used in this case is shown in Figure 4. Copper traces of the PCB model shall be drawn as
follows:
1) recommended footprints of the package shall be drawn. The lengths of A, B and C which are
indicated in Figure 4, should be the same;
2) the footprints of the leads shall be extended in parallel to the edge of the PCB.
In this figure, the yellow area is Cu trace and the green one is insulator. The size of the PCB
model is 76,2 × 114,3 × 1,6 (mm ).

– 8 – IEC 63378-3:2025 © IEC 2025

Figure 4 – PCB model
Table 2 shows the dimensions and material properties of the PCB model.
Table 2 – Dimensions and material properties of PCB model
Thermal
Material Thickness Density Specific heat
conductivity
(mm) (W/m∙K) (kg/m ) (J/kg∙K)
Cu layer 0,07 385 8 930 385
1 200 880
Insulator 1,53 0,3
The simulation volume, which is filled with air, is 300 × 300 × 300 (mm ) as indicated in Figure 5.
Six surfaces of this volume have thermal convection constant of 6 W/m ∙K as boundary
conditions considering natural convection. The semiconductor package model shall be set at
the centre of this volume [1] .

Figure 5 – Simulation volume
___________
Numbers in square brackets refer to the Bibliography.

The end time of the simulation shall be long enough to reach steady state conditions and it
th
should be 1 800 s. The n calculation time shall be selected using Equation (1).
n
(1)
tn = t ⋅
( )
e 

where
n is the calculation times which is from 1 to 200;
th
t(n) is the n calculation time;
t is the end time of simulation (1 800 s is recommended).
e
The die temperature of each time above is calculated using transient thermal analysis in case
of the conditions explained above.
4.3 Delphi model preparation
A Delphi model of the package shall be prepared [2]. The model shall have six nodes and nine
resistances. These nodes are called "solid node". Note that the analysis accuracy depends on
the prepared Delphi model, especially for the steady-state temperature. Figure 2 shows the
prepared Delphi model.
4.4 Thermal circuit model topology
A new node called "lower half" shall be made between the "semiconductor die node" and
"bottom inner node" because the main heat path has to be modelled finely. The resistance
between them shall be divided into two resistances.
The thermal resistance of the semiconductor die (Equation (2)) was given to the thermal
resistance between the semiconductor die node and the lower half node, the rest of the thermal
resistance was given to the resistance between the "lower half" node and the "bottom inner"
node.
l
R =
(2)
d
kA⋅
d
where
R is the thermal resistance of the semiconductor die;
d
k is the thermal conductivity of the semiconductor die (in this example, silicon is used as
d
shown in Table 1);
-6 2
A is the cross-sectional area of the die (in this example, the area is 4,0 × 10 m as shown
in Table 1);
-4
l is the thickness of the die (in this example, the thickness is 3,0 × 10 m as indicated in
Table 1).
In addition to this lower half node, six ground nodes shall be prepared. Solid nodes and ground
nodes shall be connected with thermal capacitance. Figure 6 shows the topology.

– 10 – IEC 63378-3:2025 © IEC 2025

Figure 6 – Topology
4.5 Determination of thermal capacitance values
The values of all thermal capacitances shall be calculated using a design of experiment (DoE) .
Table 3 shows the thermal capacitance of each portion. These thermal capacitances are
calculated by volume, density and specific heat of the components as indicated in Equation (3).
C= Vd⋅⋅ c
(3)
p p pp
where
C is the heat capacity of the portion such as moulding;
p
V is the volume of the portion;
p
d is the density of the portion;
p
c is the specific heat of the portion.
p
Table 3 – Thermal capacitance of the portions (Example)
Thermal
Portion Volume Density Specific heat
capacitance
3 3
(J/K) (m ) (kg/m ) (J/kg-K)
Moulding 0,122 5 7,549 5e-8 1 840 882
Semiconductor die 0,002 0 1,200 0e-9 2 330 700
Die attach 0,000 2 1,000 0e-10 14 500 151
Heat spreader 0,055 7 1,627 4e-8 8 900 385
Lead 0,019 9 5,441 9e-9 8 900 410
Bonding wire 0,000 1 3,927 0e-11 10 500 235

The thermal capacitances of the portions shall be fitted to the model capacitance. One method
is described below with the formulas of Table 4. The capacitance of bonding wire is so small
that it can be ignored.
Table 4 – Thermal capacitance assignment
Symbol Thermal capacitance value
C1 C
semiconductor die
C2 (1-α-β)·C
moulding
C3 α·C
moulding
C4 β·C
moulding
C5
(1-γ)·C
heat spreader
C6
γ·C
heat spreader
Where α, β, γ are constant parameters, their ranges are between 0,01 and 0,99.
A large number of combinations, more than 31, should be adopted. In case of 31 combinations,
the values of α, β, γ parameters should be used as shown in Table 5.
Table 5 – The combination of α, β, γ (example)
Number 0 1 2 3 4 5 6 7 8 9 10
α 0,050 0 0,123 1 0,490 6 0,170 2 0,481 2 0,311 5 0,066 5 0,019 4 0,038 3 0,094 8 0,057 1
β 0,900 0 0,865 2 0,434 0 0,819 8 0,502 1 0,445 4 0,456 7 0,967 3 0,695 0 0,626 9 0,479 4
γ 0,500 0 0,115 4 0,638 5 0,361 5 0,869 2 0,561 5 0,207 7 0,238 5 0,330 8 0,330 8 0,838 5
Number 11 12 13 14 15 16 17 18 19 20 21
α 0,339 8 0,076 0 0,255 0 0,179 6 0,085 4 0,010 0 0,321 0 0,207 9 0,471 7 0,283 3 0,377 5
β 0,422 7 0,717 7 0,729 0 0,581 5 0,672 3 0,978 7 0,524 8 0,400 0 0,513 5 0,706 3 0,604 2
γ 0,284 6 0,623 1 0,176 9 0,376 9 0,884 6 0,792 3 0,900 0 0,807 7 0,423 1 0,853 8 0,669 2
Number 22 23 24 25 26 27 28 29 30
α 0,236 2 0,500 0 0,028 8 0,132 5 0,386 9 0,189 0 0,349 2 0,141 9 0,226 7
β 0,751 7 0,468 1 0,536 2 0,853 8 0,592 9 0,570 2 0,638 3 0,411 3 0,490 8
γ 0,592 3 0,161 5 0,546 2 0,823 1 0,146 2 0,684 6 0,407 7 0,407 7 0,130 8

Then all combinations of thermal analysis shall be executed in order to define the constants of
α, β, γ. The same PCB model, simulation volume and time period as the detailed analysis shall
be used.
Then, square summation (SS) shown in Equation (4) shall be calculated.
SS T− T
(4)
( )
∑ d, nnn,
n=1
where
th
T is the temperature of the n calculation time step which is calculated using the
d, n
detailed model;
th
is the temperature of the n calculation time step which is calculated using this
T
n, n
thermal circuit network model.
Finally, the least case of square summation shall be selected.
=
– 12 – IEC 63378-3:2025 © IEC 2025
In the presented example, α, β, γ of number 25 (α = 0,132 5 and β = 0,853 8 and γ = 0,823 1)
results in the least square summation. The unknown parameters of thermal capacitance are
determined using these processes.
Simulation accuracy of this thermal simulation model is explained in Annex A.

Annex A
(normative)
Validation for TO-252 case
A.1 General
Annex A provides a description of the relationship between the detailed model and the
developed transient thermal circuit model.
This transient thermal circuit model is named as dynamic Delphi and its abbreviation is D2elphi.
A.2 Simulation parameters
There are two simulation parameters. One is the size of semiconductor die (1 × 1 × 0,3 (mm )
3 3
or 2 × 2 × 0,3 (mm )
...