IEC 62418:2010

Semiconductor devices - Metallization stress void test

IEC 62418:2010 describes a method of metallization stress void test and associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.

Dispositifs à semiconducteurs - Essai sur les cavités dues aux contraintes de la métallisation

La CEI 62418:2010 décrit une méthode d'essai sur les cavités dues aux contraintes générées par la métallisation et les critères associés. Elle s'applique à la métallisation à l'aluminium (Al) ou au cuivre (Cu).

General Information

• Status: Published
• Publication Date: 21-Apr-2010
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 5 - TC 47/WG 5
• Current Stage: PPUB - Publication issued
• Start Date: 15-May-2010
• Completion Date: 22-Apr-2010

Standards Content (Sample)

IEC 62418 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Metallization stress void test

Dispositifs à semiconducteurs – Essai sur les cavités dues aux contraintes
de la métallisation
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IEC 62418 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Metallization stress void test

Dispositifs à semiconducteurs – Essai sur les cavités dues aux contraintes
de la métallisation
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
Q
CODE PRIX
ICS 31.080 ISBN 978-2-88910-697-4
– 2 – 62418 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Test equipment.5
3 Test structure .5
3.1 Test structure patterns .5
3.2 Line pattern.5
3.3 Via chain pattern .5
3.3.1 Pattern types .5
3.3.2 Pattern for aluminium (Al) process.5
3.3.3 Pattern for copper (Cu) process.6
4 Stress temperature.6
5 Procedure .6
5.1 Stress void evaluation methods .6
5.2 Resistance measurement method.6
5.3 Inspection method .7
6 Failure criteria .8
6.1 Resistance method.8
6.2 Inspection method .8
7 Data interpretation and lifetime extrapolation (resistance change method).8
8 Items to be specified and reported.9
8.1 Resistance change method .9
8.2 Inspection method .10
Annex A (informative) Stress migration mechanism .11
Annex B (informative) Technology-dependent factors for aluminium .13
Annex C (informative) Technology-dependent factors for copper .14
Annex D (informative) Precautions.15
Bibliography.17

Figure A.1 – Schematic representation of the stress-void formation mechanism in Al.11

Table 1 – Void classification .7

62418 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST

FOREWORD
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International Standard IEC 62418 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2043/FDIS 47/2050/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – 62418 © IEC:2010
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
62418 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST

1 Scope
This International Standard describes a method of metallization stress void test and
associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.
This standard is applicable for reliability investigation and qualification of semiconductor
process.
2 Test equipment
A calibrated hot chuck or thermal chamber is required to subject the wafers or packaged test
structures to the specified temperature (±5 °C) for the specified time. For resistance
measurements dedicated equipment is needed. For void inspection deprocessing equipment
is required to remove the scratch protection layer. The inspections are performed with a
scanning electron microscope (SEM).
3 Test structure
3.1 Test structure patterns
Test structures shall be used for all metal layers which have to be inspected and several
different types of structure may be used. The following two types of test structures are
applicable for this test standard.
NOTE For metallization without refractory shunt layers reflective notching at steps can occur in test structures
with underlying topography, which will therefore tend to indicate a relatively worse stress-voiding behaviour.
3.2 Line pattern
Parallel lines which are patterned at the minimum linewidth allowed by design form an
appropriate test structure. Unless otherwise specified a minimum length of 500 μm and a total
length of 1 cm to 1 000 cm are recommended condition. Single long isolated lines are
recommended because stress voiding is often sensitive to line-to-line separation.
NOTE 1 Narrow lines ar
...