IEC TR 62878-2-2:2015

Device embedded substrate - Part 2-2: Guidelines - Electrical testing

IEC TR 62878-2-2:2015 describes the necessary information on electrical testing for device embedded substrate. This includes the interconnection open- and short-circuit tests as well as the device functional test. It also provides guidelines by demonstrating the electrical test for device embedded substrate.

Substrat avec appareil(s) integre(s) - Partie 2-2: Directives - Essai électrique

L'IEC 62878-2-2:2015 décrit les informations nécessaires aux essais électriques de substrat avec appareil(s) intégré(s). Elle décrit en outre les essais d'interconnexion en circuit ouvert et en court-circuit et l'essai fonctionnel de l'appareil. Elle fournit également des directives de démonstration des essais électriques de substrat avec appareil(s) intégré(s).

General Information

• Status: Published
• Publication Date: 03-Dec-2015
• ICS: 31.180 - Printed circuits and boards
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 6 - TC 91/WG 6
• Current Stage: PPUB - Publication issued
• Start Date: 04-Dec-2015
• Completion Date: 15-Feb-2016

Standards Content (Sample)

IEC TR 62878-2-2 ®
Edition 1.0 2015-12
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-2: Guidelines – Electrical testing

Substrat avec appareil(s) intégré(s) –
Partie 2-2: Directives – Essai électrique

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IEC TR 62878-2-2 ®
Edition 1.0 2015-12
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-2: Guidelines – Electrical testing

Substrat avec appareil(s) intégré(s) –

Partie 2-2: Directives – Essai électrique

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-3032-9

– 2 – IEC TR 62878-2-2:2015 © IEC 2015
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Electrical tests . 6
2.1 Test level 1A for device embedded substrate . 6
2.2 Test level 1B for component embedded substrate . 7
2.3 Test level 2A for component embedded substrate . 7
2.4 Test level 2B for passive device embedded substrate . 9
2.5 Test level 3 for device embedded substrate . 10
3 Electrical test procedure for device embedded substrate . 12
Bibliography . 15

Figure 1 – Interconnection open/short test . 5
Figure 2 – Test level 1A . 7
Figure 3 – Test level 1B . 7
Figure 4 – Test level 2A . 8
Figure 5 – Test level 2B . 9
Figure 6 – Device embedded substrate with two or more passive devices . 10
Figure 7 – Test level 3 for functional test . 11
Figure 8 – Circuit model and simulation result . 12
Figure 9 – Preparation for the test setup . 13
Figure 10 – Test procedure flow . 14

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDED SUBSTRATE –
Part 2-2: Guidelines – Electrical testing

FOREWORD
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The main task of IEC technical committees is to prepare International Standards. However, a
technical committee may propose the publication of a Technical Report when it has collected
data of a different kind from that which is normally published as an International Standard, for
example "state of the art".
IEC TR 62878-2-2, which is a Technical Report, has been prepared by IEC technical
committee 91: Electronics assembly technology.
The text of this Technical Report is based on the following documents:
Enquiry draft Report on voting
91/1220/DTR 91/1245/RVC
Full information on the voting for the approval of this Technical Report can be found in the
report on voting indicated in the above table.

– 4 – IEC TR 62878-2-2:2015 © IEC 2015
The French version of this Technical Report has not been voted upon.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62878 series, published under the general title Device embedded
substrate, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
INTRODUCTION
Current electrical package designs are becoming more complex, more functionally integrated,
more reliable and more miniaturized than ever. Hence, electrical tests should be classified
into levels in order to ensure the performance and quality of device embedded substrates
since the substrate contains active/passive devices within it. While the interconnection
open/short test is enough for general substrates, functional tests should be done when
active/passive devices are embedded inside the substrate. However, the main problem is that
we need to understand which devices are embedded and how they are connected functionally
to each other. This is the main reason that there should be standardized test methods for
device embedded substrate. Figure 1 shows the existing substrate test method: the
interconnection open/short test.

P1 P2
P1
P2
+
V
V
–
IEC IEC
a) Open test b) Short test
Figure 1 – Interconnection open/short test

– 6 – IEC TR 62878-2-2:2015 © IEC 2015
DEVICE EMBEDDED SUBSTRATE –
Part 2-2: Guidelines – Electrical testing

1 Scope
This part of IEC 62878, which is a Technical Report, describes the necessary information on
electrical testing for device embedded substrate. This includes the interconnection open- and
short-circuit tests as well as the device functional test. It also provides guidelines by
demonstrating the electrical test for device embedded substrate.
This part of IEC 62878 is applicable to device embedded substrates fabricated by use of
organic base material, which include for example active or passive devices, discrete
components formed in the fabrication process of electronic wiring board, and sheet formed
components.
The IEC 62878 series does not apply to the re-distribution layer (RDL) nor to the electronic
modules defined as an M-type business model in IEC 62421.
2 Electrical tests
2.1 Test level 1A for device embedded substrate
Test level 1A for device embedded substrate is to check the continuity and isolation of
interconnections which are not connected to any embedded components. This is shown in
Figure 2. Test point 1 and test point 2 are on different networks. After measuring the
resistance between net 1 and net 2, it can be found that net 1 and net 2 are short if the
measured resistances are below a certain resistance. Test point 3 and test point 4 are on the
same net, which is net 3. They are open if the measured resistance between the two test
points is over a certain resistance. It means that they are not electrically connected.
Multi-testers which can measure voltage and current are commercially available. The source
meter can measure the resistance directly since it has its own power supply. In terms of
reliability, a high-current or low-level voltage test can be done to check the micro-open which
causes the latent defects in the printed-circuit board and to check the micro-short which
causes noise in the RF system.

Test point 1
Test point 2
Test point 3
Net 3
+
–
A V
Voltage
Current
source
source
Current
meter
Voltage
meter
Net 1 Net 2 Net 4
Test point 4
IEC
Figure 2 – Test level 1A
2.2 Test level 1B for component embedded substrate
Test level 1B is for testing electrical interconnection between wiring nets and component nets.
This is shown in Figure 3. The test method of this level is the same as that of test level 1A
because test level 1B is to check the isolation interconnection. Electrical interconnections are
short if the measured resistance between wiring nets and component nets is below a certain
resistance. It means that they are electrically connected.
Component nets
A
Current
meter
+
–
Voltage
source
Wiring nets
Resistor Capacitor
IEC
Figure 3 – Test level 1B
2.3 Test level 2A for component embedded substrate
Test level 2A is for testing a single component embedded substrate. Figure 4 a) shows the
passive component scheme. Through this test, the electrical performance of the passive
component and the continuity of the net can be measured. However, only the electrical
performance test is suitable because the performance of the passive component will be
affected if there is a problem with the continuity. In order to measure the performance of the
passive component, the test method and the test signal need to be changed along with the

– 8 – IEC TR 62878-2-2:2015 © IEC 2015
type of passive component. In the case of resistors, resistance can be measured by detecting
the current/voltage ratio using constant voltage and constant current as in test levels 1A and
1B. However, in the case of capacitors and inductors, capacitance and inductance need to
use an AC source to get the values. LCR meters and impedance analyzers are commercially
available to measure resistance, capacitance, inductance and impedance. The equipment
should be selected based on the frequency range to be measured.
Figure 4 b) shows the active component circuit diagram, the method and the design of the
electrostatic discharge (ESD) protection diode. Test level 2A is achieved by applying
positive/negative bias to the circuit.
AC
V
A
Voltage Voltage
Inductor Current
Resistor Capacitor
meter source
meter
IEC
a) Passive component scheme
Input V
dd
pMOS
nMOS
V
ss
V
↑
Current
Voltage
source
measure
IEC
b) Active component circuit diagram and the method
Key
V drain voltage
dd
V source voltage
ss
pMOS p-channel metal oxide semiconductor
nMOS n-channel metal oxide semiconductor
Figure 4 – Test level 2A
2.4 Test level 2B for passive device embedded substrate
Test level 2B is for a simple passive structure which consists of a few passive components.
These components are connected either in parallel or in series (Figure 5). This test will
measure the electrical performance of the structure and the continuity of the transmission
lines. For this case, only the electrical performance test is suitable because the performance
of the passive components will be affected if there is a problem with the continuity, as for test
level 2A. To be able to test passive components, test level 2B uses an AC source like test
level 2A. However, it cannot measure the performance of individual passive components
because the measured impedance will be the combination of impedances of all passive
components. Moreover, tolerance values are introduced when the passive components are
measured.
A V AC
Resistor
Voltage Voltage
Current
Capacitor meter source
meter
Inductor
Capacitor
Inductor
Resistor
IEC
Figure 5 – Test level 2B
For example, as shown in Figure 6 a), if the capacitance of C1 is 1 µF with a tolerance of
± 20 %, the capacitance of C2 is 0,1 µF with a tolerance of ± 10 % and they are good
components, then the total capacitance will be 0,89 µF ≤ (C1 + C2) ≤ 1,31 µF because of their
tolerances. Thus, the passive component is good if the measured capacitance is between
0,89 µF and 1,31 µF. However, if C1 is good and C2 (< 0,09 µF) is bad, or C1 is good and C2
(> 0,11 µF) is bad, then the results are 0,8 µF ≤ (C1 + C2) ≤ 1,29 µF and (C1 + C2) > 0,91 µF,
respectively. In these cases, we cannot judge if the passive components are good or bad
because the results of both experiments are good even though one component is bad.
However, if the frequency dependence of impedance is measured as in Figure 6 b), then the
performances of each individual capacitor can be seen. Hence we can decide if C1 and/or C2
are good or bad depending on the frequency difference of resonance frequency. The
inductance case between L1 and L2 of Figure 6 a) is similar to the capacitance case of
Figure 6 a).
– 10 – IEC TR 62878-2-2:2015 © IEC 2015
C1: 1 µF L1: 1 µH
(Tolerance ± 20 %) (Tolerance ± 20 %)
C2: 0,1 µF L2: 0,1 µH
(Tolerance ± 10 %) (Tolerance ± 10 %)

IEC
a) Parallel and series structures of passive devices with tolerances
0 0
–20 –20
–40 –40
–60 –60
–80 –80
–100
–100
Frequency (㎐)
Frequency (㎐)
IEC
b) Graph for frequency dependence of impedance from the structure in a)
Figure 6 – Device embedded substrate with two or more passive devices
Therefore, it is necessary to judge whether each series or parallel passive component is good
or bad at more than two specific frequency points by measuring total impedance and phase
difference as test level 2B. The frequency points will be selected from simulation results or
calculation. For more detailed analysis, continuous changes of impedance or phase difference
need to be measured along with the frequency.
There is commercially available measurement equipment such as impedance analyzer and
network analyzer. If the equipment has a wider measurable frequency range, the
measurement result from the equipment will be more accurate. When a very high frequency
measurement is required, the equipment setting such as probe tips and transmission lines to
the equipment should be changed for a very high frequency measurement. One tip for easier
measurement at high frequency is to design external test pads well so as not to use a high-
cost probe card for high frequency measurement but to use RF probe tips which are
commercially available.
2.5 Test level 3 for device embedded substrate
Figure 7 shows the functional test method of device embedded substrate which acts like a
signal filter. The passive components in the substrate are connected to each other either in
parallel or in series. In case of such a structure, the test result will not be the performance of
individual passive components, but the performance of the filter. Typical open/short tests are
dB (S(1,1))
dB (S(1,1))
not required since the performance of the filter will be affected when the continuity of nets has
a problem.
Network analyzer
Inductors
Capacitors
IEC
Figure 7 – Test level 3 for functional test
Test level 3 is to test the functional performance of passive device embedded substrate when
the embedded passive devices function as a filter or filter banks. The scattering parameter
(S-parameter) is measured to test the embedded substrate with the network analyzer, time
domain reflectometry (TDR) and time domain transmission (TDT) within the specific frequency
range. Each of the ports of the filter in Figure 8 will be connected to each measuring port of
the network analyzer to get input and output signal distributions. The S-parameter can be
measured by dividing the input voltage into the output voltage. For example, the embedded
filter which consists of embedded passive components can be modelled and simulated. The
circuit model of the filter is shown in Figure 8 a) and the response is shown in Figure 8 b).
The simulation result becomes a basis for deciding if the filter is either good or bad. Since the
filter is measured as one device, the individual passive components cannot be measured or
tested. Therefore, we do not know which passive component is bad if there is a problem with
the filter. Comparing the measured data to the simulation data, the specifications to pay
attention to are insertion loss, bandwidth skirt properties, ripple level, rejection loss, noise
level, etc.
– 12 – IEC TR 62878-2-2:2015 © IEC 2015

Z Z
–20
C4
–40
L1
C3
–60
L2
C2
–80
–100
C1
–120
Z –140
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
Frequency (GHz)
IEC IEC
a) Circuit model b) Simulation result
Key
Z C2 22 pF
50 Ω
L1 47 nH C3 22 pF
L2 100 nH C4 47 pF
C1 47 pF
NOTE In case of testing device embedded substrate, all of the functional testing such as digital testing, analogue
testing, mixed signal testing, RF testing, memory testing, and image sensor testing may be needed. For this test,
the performance board, substrate handler for a double side probing, and automatic test equipment are prepared.
Figure 8 – Circuit model and simulation result
3 Electrical test procedure for device embedded substrate
A test design review is important to decide how to test device embedded substrate and how to
define test specifications. In order to decide test specifications, active device information is
especially required. This is the main reason that the test method of device embedded
substrate has not been standardized. For the standardization test for device embedded
substrate, the test specification of the embedded active device may be required for evaluating
the embedded active device.
In order to set up the test for device embedded substrate, information such as the design and
the structure of device embedded substrate and embedded passive component specifications
is required. Also, information on test pattern and performance measurement should be
gathered to test embedded devices before the actual test. It will affect the final yield on device
embedded substrate and will be the important indicator when test specifications are defined.
Figure 9 and Figure 10 show the test design review and the preparation flow for the test setup.
dB (S(3,1))
dB (S(2,1))
Start
 Design review of product
 Chip design/test engineer
Product design/test engineer from embedded
Kick off meeting
PCB supplier
Preparation for test setup
 Product information
 Requirement for hardware
 Application
 Package information (size, pitch)
 Specifications
 Pad size, pitch and centre coordinate
 Block diagram for the
 Pin definition and connections
device
 Unused pin information
 Data sheet and references
 Power pin information
Information for load board application and
special parts
 Information for developing test program
 Test vectors or ASCII vectors for target tester
 Timing table showing period, delay, setup, hold time
 Explanation of each test vector
 Cycle by cycle waveforms, setup conditions, and electrical specs including min. and
max. conditions
 Functional table
IEC
Figure 9 – Preparation for the test setup
The first thing to do, after finishing the test design review and the preparation for the test
setup, is to make a test plan. The plan includes a test circuit and test interface such as test
socket and test board. After that, a test interface will be made with the selected test circuit.
Meanwhile, the test program will be written so that the whole pilot test can be done by using
the test program after making the test interface.
Using the test result, the original test design will be verified. If there is a problem with the test
design, the test should be redesigned. Or, the program needs to be debugged if the test
program causes any problems. If the test passes, the specifications of device embedded
substrate need to be registered after the final test and the design review. Afterwards, the
manufacturing test on device embedded substrate can be applied with the registered
specifications.
NOTE A total plan is developed for the final test design and any debugging that needs to take
...