IEC 61883-1:2008
(Main)Consumer audio/video equipment - Digital interface - Part 1: General
Consumer audio/video equipment - Digital interface - Part 1: General
IEC 61883-1:2008 specifies a digital interface for consumer electronic audio/video equipment using IEEE 1394. It describes the general packet format, data flow management and connection management for audio-visual data, and also the general transmission rules for control commands. It defines a transmission protocol for audio-visual data and control commands which provides for the interconnection of digital audio and video equipment, using IEEE 1394. This third edition of IEC 61883-1 cancels and replaces the second edition, published in 2003 and it constitutes a technical revision. The significant technical changes with respect to the second edition are:
- allocation of a new FMT code for the 1394 Trade Association specification '601 over 1394';
- Clarification of the meaning of FMT code;
- harmonization of IEC 61883-1 with IEEE 1394.1 for speeds over S400. This bilingual version (2012-08) corresponds to the monolingual English version, published in 2008-02.
Matériel audio/vidéo grand public - Interface numérique - Partie 1: Généralités
La CEI 61883-1:2008 spécifie une interface numérique pour matériel électronique audio/vidéo grand public, en utilisant la norme IEEE 1394. Elle décrit la structure générale en paquets, la gestion du flux de données et la gestion de la connexion de données audio-visuelles; elle décrit également les règles générales de transmission des commandes de contrôle. Elle définit un protocole de transmission de données audio-visuelles et une commande de contrôle assurant l'interconnexion du matériel numérique audio et vidéo, en appliquant la norme IEEE 1394. Cette troisième édition de la CEI 61883-1 annule et remplace la deuxième édition parue en 2003. Elle constitue une révision technique. Les modifications techniques significatives par rapport à la deuxième édition sont:
- attribution d'un nouveau code FMT (Identification du format, en anglais " Format ID ") à l'Association commerciale 1394 " 601 sur 1394 ";
- Clarification de la signification du code FMT;
- harmonisation de la CEI 61883-1 avec l'IEEE 1394.1 pour les vitesses supérieures à S400. La présente version bilingue (2012-08) correspond à la version anglaise monolingue publiée en 2008-02.
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Standards Content (Sample)
IEC 61883-1
Edition 3.0 2008-02
INTERNATIONAL
STANDARD
Consumer audio/video equipment – Digital interface –
Part 1: General
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IEC 61883-1
Edition 3.0 2008-02
INTERNATIONAL
STANDARD
Consumer audio/video equipment – Digital interface –
Part 1: General
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
X
ICS 33.160.01; 35.200 ISBN 2-8318-9610-X
– 2 – 61883-1 © IEC:2008(E)
CONTENTS
FOREWORD.5
1 Scope and object.7
2 Normative references .7
3 Abbreviations .7
4 High-performance serial bus layers .8
4.1 Cable physical layer .8
4.2 Link layer .8
4.3 Transaction layer.8
5 Minimum node capabilities .8
5.1 Serial bus management.8
5.2 Command and status registers .8
5.2.1 CSR core registers .8
5.2.2 Serial bus node registers .9
5.2.3 Configuration ROM requirements.9
6 Real time data transmission protocol .12
6.1 Common isochronous packet (CIP) format.12
6.1.1 Isochronous packet structure.12
6.1.2 Packet header structure.12
6.1.3 CIP header structure .13
6.2 Transmission of fixed length source packet .13
6.2.1 Two-quadlet CIP header (form_0=0, form_1=0) .14
6.2.2 Isochronous packet transmission.17
7 Isochronous data flow management.17
7.1 General .17
7.2 Plugs and plug control registers .18
7.3 Connections .19
7.4 Plug states .20
7.5 OUTPUT_MASTER_PLUG register definition .22
7.6 INPUT_MASTER_PLUG register definition .23
7.7 OUTPUT_PLUG_CONTROL register definition .23
7.8 INPUT_PLUG_CONTROL register definition.25
7.9 Plug control register modification rules .26
7.10 Bus reset.27
7.11 Plug control register access rules.27
8 Connection management procedures (CMP).28
8.1 Introduction .28
8.2 Managing point-to-point connections .29
8.2.1 Procedure for establishing a point-to-point connection.29
8.2.2 Procedure for overlaying a point-to-point connection .30
8.2.3 Procedure for breaking a point-to-point connection.31
8.3 Managing broadcast-out connections .32
8.3.1 Procedure for establishing a broadcast-out connection .32
8.3.2 Procedure for overlaying a broadcast-out connection.33
8.3.3 Procedure for breaking a broadcast-out connection .33
8.4 Managing broadcast-in connections.34
61883-1 © IEC:2008(E) – 3 –
8.4.1 Procedure for establishing a broadcast-in connection .34
8.4.2 Procedure for overlaying a broadcast-in connection.35
8.4.3 Procedure for breaking a broadcast-in connection .35
8.5 Managing connections after a bus reset .36
8.5.1 Procedure for restoring a point-to-point connection after a bus reset .36
8.5.2 Procedure for restoring a broadcast-out connection after a bus reset .37
8.5.3 Procedure for restoring a broadcast-in connection after a bus reset .38
9 Function control protocol (FCP) .38
9.1 Introduction .38
9.2 Asynchronous packet structure.39
9.3 FCP frame structure .40
9.3.1 Vendor unique command/transaction set .41
9.3.2 Extended command/transaction set .42
Figure 1 – Configuration ROM .10
Figure 2 – Isochronous packet .12
Figure 3 – CIP header.13
Figure 4 – Model of transmission of source packets.14
Figure 5 – Two quadlets CIP header (Form_0, Form_1=0) .14
Figure 6 – Source packet header format .15
Figure 7 – Plug and PR usage .19
Figure 8 – Connections.20
Figure 9 – Plug state diagram .21
Figure 10 – oMPR format.22
Figure 11 – iMPR format .23
Figure 12 – oPCR format .24
Figure 13 – iPCR format .26
Figure 14 – PCR address map .27
Figure 15 – Point-to-point and broadcast connection counter modifications .29
Figure 16 – Establishing a point-to-point connection .30
Figure 17 – Overlaying a point-to-point connection .31
Figure 18 – Breaking a point-to-point connection .32
Figure 19 – Establishing a broadcast-out connection .33
Figure 20 – Overlaying a broadcast-out connection.33
Figure 21 – Breaking a broadcast-out connection .34
Figure 22 – Establishing a broadcast-in connection .35
Figure 23 – Overlaying a broadcast-in connection.35
Figure 24 – Breaking a broadcast-in connection.36
Figure 25 – Time chart of connection management and PCR activities .36
Figure 26 – Restoring a point-to-point connection .37
Figure 27 – Restoring a broadcast-out connection .38
Figure 28 – Restoring a broadcast-in connection .38
Figure 29 – Command register and response register .39
Figure 30 – Write request for data block packet of IEEE 1394.40
Figure 31 – Write request for data quadlet packet of IEEE 1394 .40
– 4 – 61883-1 © IEC:2008(E)
Figure 32 – FCP frame structure.41
Figure 33 – Vendor unique frame format.42
Table 1 – Unit_SW_Version code assignment.11
Table 2 – Code allocation of FN.15
Table 3 – Time stamp field of source packet header .16
Table 4 – Placing of data block sequence .16
Table 5 – Code allocation of FMT .16
Table 6 – Time stamp of SYT field .17
Table 7 – oMPR/iMPR/oPCR speed encoding spd and extended speed encoding xspd.22
Table 8 – oPCR overhead ID encoding .25
Table 9 – CTS: Command/transaction set encoding.41
61883-1 © IEC:2008(E) – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
CONSUMER AUDIO/VIDEO EQUIPMENT –
DIGITAL INTERFACE –
Part 1: General
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61883-1 has been prepared by technical area 4, Digital system
interfaces and protocols, of IEC technical committee 100: Audio, video and multimedia
systems and equipment.
This third edition of IEC 61883-1 cancels and replaces the second edition, published in 2003,
of which it constitutes a technical revision.
The significant technical changes with respect to the second edition are as follows:
– allocation of a new FMT code for the 1394 Trade Association specification ‘601 over
1394’;
– Clarification of the meaning of FMT code;
– harmonization of IEC 61883-1 with IEEE 1394.1 for speeds over S400.
– 6 – 61883-1 © IEC:2008(E)
The text of this standard is based on the following documents:
CDV Report on voting
100/1236/CDV 100/1336/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 61883 series, under the general title Consumer audio/video
equipment – Digital interface, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.
61883-1 © IEC:2008(E) – 7 –
CONSUMER AUDIO/VIDEO EQUIPMENT –
DIGITAL INTERFACE –
Part 1: General
1 Scope and object
This part of IEC 61883 specifies a digital interface for consumer electronic audio/video
equipment using IEEE 1394. It describes the general packet format, data flow management
and connection management for audio-visual data, and also the general transmission rules for
control commands.
The object of this standard is to define a transmission protocol for audio-visual data and
control commands which provides for the interconnection of digital audio and video
equipment, using IEEE 1394.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEEE 212:2001, Standard for a Control and Status Registers (CSR) – Architecture for
microcomputer buses
IEEE 1394:1995, Standard for a High Performance Serial Bus
IEEE 1394a:2000, Standard for a High Performance Serial Bus – Amendment 1
NOTE Throughout this document, the term “IEEE 1394” indicates a reference to the standard that is the result of
the editorial combination of IEEE 1394:1995 and IEEE 1394a:2000. Devices conforming solely to IEEE 1394:1995
may conform to IEC 61883. Devices conforming to IEC 61883 should conform to IEEE 1394a:2000.
3 Abbreviations
For the purpose of this document, the following abbreviations apply.
AV/C Audio Video Control
CHF CIP Header Field
CIP Common Isochronous Packet
CMP Connection Management Procedures
CSR Command and Status Register
CTS Command/Transaction Set
CRC Cyclic Redundancy Check Code
DVCR Digital Video Cassette Recorder
EOH End of CIP Header
FCP Function Control Protocol
iPCR Input Plug Control Register
iMPR Input Master Plug Register
MPEG Motion Picture Experts Group
oPCR Output Plug Control Register
– 8 – 61883-1 © IEC:2008(E)
oMPR Output Master Plug Register
ROM Read Only Memory
spd Speed Encoding
xspd Extended Speed Encoding
For clarity, field names are shown in italics in this standard.
4 High-performance serial bus layers
4.1 Cable physical layer
All cable physical layer implementations conforming to this standard shall meet the
performance criteria specified by IEEE 1394. Either the cable and connector defined in
IEEE 1394:1995, or the cables and connector defined in IEEE 1394a:2000, shall be used.
When necessary for an AV device to generate a bus reset, it shall follow the requirements of
IEEE 1394a:2000, 8.2.1. An AV device that initiates a bus reset should generate an arbitrated
(short) bus reset, as specified by IEEE 1394a:2000, in preference to the long bus reset
defined by IEEE 1394:1995.
4.2 Link layer
All link layer implementations conforming to this standard shall meet the specifications of
IEEE 1394.
4.3 Transaction layer
All transaction layer implementations conforming to this standard shall meet the specifications
of IEEE 1394.
5 Minimum node capabilities
A node shall conform to the following requirements.
– A node shall be cycle master capable. This is because every node has the possibility to be
assigned as a root.
− A node shall be isochronous resource manager capable, as specified by IEEE 1394:1995,
and shall implement the additional isochronous resource manager facilities and
responsibilities specified by IEEE 1394a:2000 in 8.3.1.5, 8.3.2.3.8, 8.3.2.3.11, 8.4.2.3 and
8.4.2.6A.
− A node which transmits or receives isochronous packets shall have plug control registers
(see 7.2).
5.1 Serial bus management
Bus manager capability is optional for AV devices, but, if implemented by devices conforming
to this standard, shall conform to IEEE 1394.
5.2 Command and status registers
5.2.1 CSR core registers
This standard conforms to the CSR architecture. Details of its registers are specified by
IEEE 1394.
The STATE_CLEAR.cmstr bit shall be implemented as specified by IEEE 1394a:2000, 8.3.2.2.1.
61883-1 © IEC:2008(E) – 9 –
NOTE The cmstr bit is set automatically (see IEEE 1394a:2000, 8.3.2.2.1) by system software or hardware when
a node becomes the new root after the bus reset process is completed. In this manner, it is possible to ensure the
fast resumption and continuity of data transmission where the time scale is critical at the level of microseconds.
The rapid activation of a new cycle master decreases the likelihood of a gap in the transmission of cycle start
packets; uninterrupted transmission of cycle start packets at nominal 125 µs intervals is critical to the delivery of
isochronous data within its latency requirements.
5.2.2 Serial bus node registers
Implementation requirements for bus-dependent registers in this standard conform to
IEEE 1394. A node shall have the following registers:
CYCLE_TIME register
BUS_TIME register
BUS_MANAGER_ID register
BANDWIDTH_AVAILABLE register
CHANNELS_AVAILABLE register
A node should have the following register specified by IEEE 1394a:2000:
BROADCAST_CHANNEL register
5.2.3 Configuration ROM requirements
A node shall implement the general ROM format as defined in IEEE 1212:2001 and
IEEE 1394. Additional information required for implementations of this standard shall be
included in one of the unit directories. Figure 1 shows an example of the configuration ROM
implementation for this standard.
– 10 – 61883-1 © IEC:2008(E)
)
Offset (Base address FFFF F000 0000
Bus_info_block
04 00 04 crc_length rom_crc_value
16 16
04 04
" 1 3 9 4
04 08 Reserved cyc_clk_acc max_rec Reserved
04 0C node_vendor_id
chip_id_hi
04 10
chip_id_lo
Root_directory
04 14
root_length CRC
04 18
16 03 module_vendor_id
04 1C
0C
16 16 node_capabilities
04 20
16 8D node_unique_id offset
04 24
D1 unit_directory offset
16 16
04 28
:
Optional
Unit_directory
unit_directory_length
CRC
12 unit_spec_id
13 unit_sw_version
:
Optional
Node_unique_id leaf
00 02
CRC
node_vendor_id
chip_id_hi
chip_id_lo
IEC 305 9/02
Figure 1 – Configuration ROM
irmc
cmc
isc
bmc
61883-1 © IEC:2008(E) – 11 –
5.2.3.1 Bus_Info_Block entry
Implementation requirements for the Bus_Info_Block in this standard shall conform to
IEEE 1394.
5.2.3.2 Root directory
The following entries shall be present:
− Module_Vendor_ID;
− Node_Capabilities;
− Unit_Directory (offset to a unit directory defined by this standard).
Other entries may be implemented in addition to the above required entries.
5.2.3.3 Unit directory
The following entries shall be present:
− Unit_Spec_ID;
− Unit_SW_Version.
The value of the Unit_Spec_ID and the Unit_SW_Version for this standard are given as
follows:
Unit_Spec_ID: First octet = 00
Second octet = A0
Third octet = 2D
Unit_SW_Version: First octet = 01
The second and third octets of Unit_SW_Version for this standard are specified in Table 1
and indicate capabilities for command/transaction sets. The Unit_SW_Version field is used to
identify which protocol is supported by the device. If a device supports more than one
protocol, the device shall have a separate unit directory for each protocol supported.
Table 1 – Unit_SW_Version code assignment
Unit_SW_Version Command/transaction set
01 00 00 Reserved
01 00 01 AV/C protocol
01 00 02 Reserved for standardization by CAL
01 00 04 Reserved for standardization by EHS
01 00 0816 HAVi protocol
01 00 0A Automotive
01 40 00 Vendor unique
01 40 01 Vendor unique
Other values Reserved for future standardization
– 12 – 61883-1 © IEC:2008(E)
6 Real time data transmission protocol
6.1 Common isochronous packet (CIP) format
6.1.1 Isochronous packet structure
The structure of the isochronous packet utilized by this standard is illustrated in Figure 2. The
packet header and header CRC are the first two quadlets of an IEEE 1394 isochronous
packet. The CIP header is placed at the beginning of the data field of an IEEE 1394
isochronous packet, immediately followed by zero or more data blocks.
Transmitted first
Data_length ChannelTcode Sy
Tag
CIP header
Header_CRC
Data field
Zero or more data blocks
Data_CRC
Transmitted last
1 quadlet = 32 bits
Isochronous packet
CIP header and real time data
IEC 3060/02
Figure 2 – Isochronous packet
6.1.2 Packet header structure
The packet header consists of the following items as specified in IEEE 1394.
Data_length: specifies the length of the data field of the isochronous packet in bytes, which
is determined as follows:
CIP header size + signal data size
Tag: provides a high level label for the format of data carried by the isochronous
packet
00 = No CIP header included
01 = CIP header included as specified in 6.1.3
10 = Reserved
11 = Reserved
Channel: specifies the isochronous channel number for the packet
Tcode: specifies the packet format and the type of transaction that shall be performed
(fixed at 1010 )
Sy: application-specific control field
61883-1 © IEC:2008(E) – 13 –
6.1.3 CIP header structure
The CIP header is placed at the beginning of the data field of an IEEE 1394 isochronous
packet. It contains information on the type of the real time data contained in the data field
following it. The structure of the CIP header is shown in Figure 3.
1 quadlet = 32 bits
1bit 1bit
CHF_0
EOH_0 = 0
Form_0
Form_1 CHF_1
EOH_1 = 0
EOH_n = 1 CHF_n
Form_n
IEC 3061/02
Figure 3 – CIP header
The definitions of the fields are given as follows:
EOH_n (End of CIP header): means the last quadlet of a CIP header
0 = Another quadlet will follow
1 = The last quadlet of a CIP header
Form_n: in combination with EOH, shows the additional structure of
CHF_n
th
CHF_n (CIP header field):
CIP header field of n quadlet. The additional structure of
CHF_n depends on EOH_0, form_0, EOH_1, form_1, .
EOH_n, and form_n
6.2 Transmission of fixed-length source packet
This protocol transfers a stream of source packets from an application on a device to an
application on other device(s). A source packet is assumed to have a fixed length, which is
defined for each type of data. The data rate can be variable.
A source packet may be split into 1, 2, 4 or 8 data blocks, and zero or more data blocks are
contained in an IEEE 1394 isochronous packet. A receiver of the packet shall collect the data
blocks in the isochronous packet and combine them to reconstruct the source packet to send
to the application.
A model conforming to these requirements is shown in Figure 4.
– 14 – 61883-1 © IEC:2008(E)
Source packets
Source
packet
header
Padding
Data blocks
Bus packets
Packet header
Cycle sync Empty packet
and CIP header
Data blocks
Cycle start packet IEC 3062/02
Figure 4 – Model of transmission of source packets
6.2.1 Two-quadlet CIP header (form_0=0, form_1=0)
This standard defines the two-quadlet CIP header for a fixed length source packet. There are
two types for the structure of the two-quadlet CIP header as shown in Figure 5. One is the
CIP header with SYT field (Figure 5a), and the other is the CIP header without SYT field
(Figure 5b). If a device transmits real time data (identified by FMT) and requires time stamp in
the CIP header, it shall use the SYT format.
SP
00 SID DBS FN QPC rsv DBC
H
10 FMT FDF SYT
IEC 3063/02
Figure 5a – CIP header with SYT field
SP
00 SID DBS FN QPC rsv DBC
H
10 1 FMT FDF
IEC 3064/02
Figure 5b – CIP header without SYT field
Figure 5 – Two quadlets CIP header (Form_0, Form_1=0)
The definitions of the fields are given as follows.
− SID: Source node ID (node ID of transmitter)
− DBS: Data block size in quadlets
61883-1 © IEC:2008(E) – 15 –
DBS field is 8 bits because 256 quadlets is the maximum payload size for S100 mode.
When 8 bits are all 0, it means 256 quadlets; and 00000001 to 11111111 means
2 2
1 quadlet to 255 quadlets accordingly.
00000000 = 256 quadlets
00000001 = 1 quadlet
00000010 = 2 quadlets
............ ...............
= 255 quadlets
Several data blocks may be put into a bus packet, which is a packet to be transmitted on
the bus, if a higher bandwidth is required for S200 and S400 speed.
NOTE S100, S200 and S400 are transmission speeds as defined in IEEE 1394.
− FN: Fraction number
The number of data blocks into which a source packet is divided. The allowable numbers
and allocated FN codes are listed in Table 2.
Table 2 – Code allocation of FN
FN Description
00 Not divided
01 Divided into two data blocks
10 Divided into four data blocks
11 Divided into eight data blocks
− QPC: Quadlet padding count (0 quadlet to 7 quadlets)
The number of dummy quadlets padded at the end of every source packet to enable
division into equally sized data blocks. The value of all bits in padding quadlets is always
zero.
The number of padding quadlets shall be less than the number of data blocks into which
every source packet is divided, as encoded by FN.
The number of padding quadlets shall be less than the size of a single data block, as
encoded by DBS. Consequently, a data block shall never consist entirely of padding
quadlets.
− SPH: Source packet header
The value one indicates that the source packet has a source packet header. The format
of the source packet header is shown in Figure 6. Code allocation of the time stamp field
is shown in Table 3. When a time stamp is indicated, the time stamp field shall be
encoded as the lower 25 bits of the IEEE 1394 CYCLE_TIME register. Other bits are
reserved for future extension and shall be zeros.
Reserved Time stamp
IEC 3065/02
Figure 6 – Source packet header format
– 16 – 61883-1 © IEC:2008(E)
Table 3 – Time stamp field of source packet header
Time stamp field
Description
Higher 13 bits Lower 12 bits
0 0000 0000 0000 0000 0000 0000
2 2
to and to Time stamp
0 1111 0011 1111 1011 1111 1111
2 2
1 1111 1111 1111 and 1111 1111 1111 No information
2 2
Other values Reserved
− Rsv: Reserved for future extension and shall be zeros
− DBC: Continuity counter of data blocks for detecting a loss of data blocks
The value refers to the first data block following the CIP header in the bus packet. The
lower FN bits contain the sequence number of the data block within its source packet.
The remaining 8-FN bits form the sequence number of the source packet. The first data
block of any source packet always has a sequence number with value zero. If FN is zero,
then all 8 bits of DBC are used to represent a source packet sequence number. See also
Table 4.
Table 4 – Placing of data block sequence
FN Bits of DBC showing the place of data block sequence
00 (Not divided)
01 Shown in the lowest 1 bit
10 Shown in the lowest 2 bits
11 Shown in the lowest 3 bits
Table 5 – Code allocation of FMT
FMT Description
00 0000 DVCR
00 0001 601 over 1394
00 0010
to Reserved
00 1111
Audio and music
01 0000
01 0001
to Reserved
01 1101
01 1110 Free (vendor unique)
01 1111 Reserved
MPEG2-TS
10 0000
10 0001 ITU-R B0.1294 System B
10 0010
to Reserved
10 1101
11 1110 Free (vendor unique)
No data
11 1111
61883-1 © IEC:2008(E) – 17 –
− FMT: Format ID.
The code allocation is illustrated in Table 5.
If FMT is 111111 (no data), the fields for DBS, FN, QPC, SPH and DBC are ignored and
no data blocks shall be transmitted. For other values of FMT, data is present and the
most significant bit of the FMT field indicates whether or not a time stamp in SYT format
is present. When the most significant bit of FMT is zero, the FMT-dependent field
contains a time stamp in the format specified by SYT. Otherwise, the FMT-dependent
field shall not contain an absolute time stamp. See also Figure 5 and Table 5.
NOTE The distinction between absolute time stamps, for example, those in the SYT format, and relative time
stamps is crucial to the operation of Serial Bus bridges. Absolute time stamps require readjustment by each
bridge whereas relative time stamps do not. Consult IEEE 1394.1:2004 for details.
− FDF: Format dependent field
This field is defined for each FMT.
− SYT: The code allocation of the SYT field is shown in Table 6. When a time stamp is
indicated by the most significant bit of the FMT field, the SYT field shall be encoded as
the lower 16 bits of the IEEE 1394 CYCLE_TIME register.
Table 6 – Time stamp of SYT field
SYT
Description
Higher 4 bits Lower 12 bits
0000 0000 0000 0000
2 2
to and to Time stamp
1111 1011 1111 1111
2 2
1111 and 1111 1111 1111 No information
2 2
Other values Reserved
6.2.2 Isochronous packet transmission
Active transmitters shall send an isochronous packet in every cycle. If no data block is
available, an empty packet shall be sent. An empty packet shall always contain a two-quadlet
CIP header. The DBC field of an empty packet shall show the count for the first data block
contained in the first non-empty IEEE 1394 isochronous packet for the same transmission
stream following this empty packet. The other fields shall match the fields of the CIP header
of non-empty packets on the same transmission stream.
7 Isochronous data flow management
7.1 General
To start and stop isochronous data flows on the bus and to control their attributes, the
concept of plugs and plug control registers is used. Plug control registers are special purpose
CSR registers.
NOTE Plugs do not physically exist on an AV device. Only the concept of a plug is used to establish an analogy
with existing AV devices where each flow of information is routed via a physical plug.
This clause describes the contents of the plug control registers and how they may be
modified. The set of procedures that use the plug control registers to control an isochronous
data flow are called connection management procedures (CMP). The CMP that shall be used
by AV devices are described in Clause 8.
– 18 – 61883-1 © IEC:2008(E)
7.2 Plugs and plug control registers
An isochronous data flow flows from one transmitting AV device to zero or more receiving AV
devices by sending isochronous packets on one isochronous channel of the IEEE 1394 bus.
An isochronous channel shall carry not more than one isochronous data flow and each
isochronous data flow shall be carried on one isochronous channel.
Each isochronous data flow is transmitted to an isochronous channel through one output plug
on the transmitting AV device and it is received from that isochronous channel through one
input plug on each of the receiving AV devices. Each input and output plug shall not carry
more than one isochronous data flow.
The transmission of an isochronous data flow through an output plug is controlled by one
output plug control register (oPCR) and one output master plug register (oMPR) located on the
transmitting AV device. On each AV device there is only one OUTPUT_MASTER_PLUG
register for all output plugs. The OUTPUT_MASTER_PLUG register controls all attributes that
are common to all isochronous data flows transmitted by the corresponding AV device. The
OUTPUT_PLUG_CONTROL register controls all attributes of the corresponding isochronous
data flow that are independent from attributes of other isochronous data flows transmitted by
that AV device.
The reception of an isochronous data flow through an input plug is controlled by one input
plug control register (iPCR) and one input master plug register (iMPR) located on the
receiving AV device. On each AV device there is only one INPUT_MASTER_PLUG register
for all input plugs. The INPUT_MASTER_PLUG register controls all attributes that are com-
mon to all isochronous data flows received by the corresponding AV device. The
INPUT_PLUG_CONTROL register controls all attributes of the corresponding isochronous
data flow that are independent from attributes of other isochronous data flows received by
that AV device.
An isochronous data flow can be controlled by any device connected to the IEEE 1394 bus by
modifying the corresponding plug control registers. Plug control registers can be modified
by means of asynchronous transactions on the IEEE 1394 bus or by internal modifications if
the plug control registers are located on the controlling device.
The use of plugs and plug control registers is illustrated in Figure 7.
61883-1 © IEC:2008(E) – 19 –
AV–device
iMPR
iPCR[0]
iPCR[1]
IEEE 1394 bus
Isochronous. channel x
Isochronous channel y
iPCR[0]
oPCR[1]
oPCR[0] oPCR[1] oPCR[2]
iMPR
oMPR oMPR
AV–device AV–device
Isochronous data flow
IEC 3066/02
Figure 7 – Plug and PR usage
Let #iPCR and #oPCR denote the number of isochronous data flows that can be
simultaneously received and transmitted respectively by an AV device (such as a multiple
viewing device or a multiple tuner device). Both #iPCR and #oPCR shall be constants in the
range [0 to 31] that are AV device-dependent.
Each AV device shall implement #oPCR output plugs, each controlled by one separate
OUTPUT_PLUG_CONTROL register, and #iPCR input plugs, each controlled by one separate
INPUT_PLUG_CONTROL register. For AV devices implementing INPUT_PLUG_CONTROL
registers, a single INPUT_PLUG_CONTROL register within that AV device shall be
denoted as INPUT_PLUG_CONTROL[i], where i is in the range [0 to #iPCR-1]. The
INPUT_MASTER_PLUG register is optional when #iPCR = 0 and required otherwise.
For AV devices implementing OUTPUT_PLUG_CONTROL registers, a single
OUTPUT_PLUG_CONTROL register within that AV device shall be denoted
as OUTPUT_PLUG_CONTROL[i], where i is in the range [0 to #oPCR-1]. The
OUTPUT_MASTER_PLUG register is optional if #oPCR = 0 and required otherwise.
The mapping between an INPUT_PLUG_CONTROL register and an isochronous data flow in
a receiving AV device, and the mapping between an OUTPUT_PLUG_CONTROL register and
an isochronous data flow in a transmitting AV device, are AV device-dependent.
7.3 Connections
To transport isochronous data between two AV devices on the IEEE 1394 bus, it is necessary
for an application to connect an output plug on the transmitting AV device to an input plug on
the receiving AV device using one isochronous channel. The relationship between one input
plug, one output plug and one isochronous channel is called a point-to-point connection.
A point-to-point connection can only be broken by the same application that established it.
It is also possible that an application just starts the transmission or the reception of an
isochronous data flow on its own AV device by connecting one of its output or input plugs
respectively to an isochronous channel. The relationship between one output plug and one
– 20 – 61883-1 © IEC:2008(E)
isochronous channel is called a broadcast-out connection. The relationship between one input
plug and one isochronous channel is called a broadcast-in connection. Broadcast-out and
broadcast-in connections are collectively called broadcast connections. A broadcast
connection can be established only by the AV device on which the plug is located but it can
be broken by any device. The concept of connections is illustrated in Figure 8.
AV–device AV–device AV–device
iMPR iMPR
iMPR
iPCR[0] iPCR[1] iPCR[0] iPCR[0]
IEEE 1394 bus
Isochronous channel
iPCR[0] iPCR[1]
oPCR[0]
iMPR
oMPR
AV–device AV–device
Point to point–connection Broadcast connection Isochronous data flow
IEC 3067/02
Figure 8 – Connections
Only one broadcast-out connection can exist in an output plug and only one broadcast-in
connection can exist in an input plug. One broadcast connection and multiple point-to-point
connections can exist simultaneously in one plug. This can be achieved by overlaying a
connection over existing connections in the same input or output plug. It should be note that
all connections that exist in one plug use the same isochronous channel and transport the
same isochronous data flow. Multiple independent applications can create point-to-point
connections between the same input and output plug.
7.4 Plug states
A plug can be in four states as described in Figure 9: idle, ready, active and suspended.
61883-1 © IEC:2008(E) – 21 –
Off–line On–line
a
Idle b Ready
Unconnected
gh i c d i
e
Connected Suspended Active
f
IEC 3068/02
Key
a triggered internally; no action
b triggered internally; no action
c triggered by establishing the first connection; start isochronous data flow transmission/reception
d triggered by breaking the last connection; stop isochronous data flow transmission/reception
e triggered internally; suspend isochronous data flow transmission/
...
IEC 61883-1 ®
Edition 3.0 2008-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Consumer audio/video equipment – Digital interface –
Part 1: General
Matériel audio/vidéo grand public – Interface numérique –
Partie 1: Généralités
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IEC 61883-1 ®
Edition 3.0 2008-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Consumer audio/video equipment – Digital interface –
Part 1: General
Matériel audio/vidéo grand public – Interface numérique –
Partie 1: Généralités
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX X
ICS 33.160.01; 35.200 ISBN 978-2-83220-237-1
– 2 – 61883-1 IEC:2008
CONTENTS
FOREWORD . 5
1 Scope and object . 7
2 Normative references . 7
3 Abbreviations . 7
4 High-performance serial bus layers . 8
4.1 Cable physical layer . 8
4.2 Link layer . 8
4.3 Transaction layer . 8
5 Minimum node capabilities . 8
5.1 Serial bus management . 8
5.2 Command and status registers . 8
5.2.1 CSR core registers . 8
5.2.2 Serial bus node registers . 9
5.2.3 Configuration ROM requirements . 9
6 Real time data transmission protocol . 12
6.1 Common isochronous packet (CIP) format . 12
6.1.1 Isochronous packet structure . 12
6.1.2 Packet header structure . 12
6.1.3 CIP header structure . 13
6.2 Transmission of fixed length source packet . 13
6.2.1 Two-quadlet CIP header (form_0=0, form_1=0) . 14
6.2.2 Isochronous packet transmission . 17
7 Isochronous data flow management . 17
7.1 General . 17
7.2 Plugs and plug control registers . 18
7.3 Connections . 19
7.4 Plug states . 20
7.5 OUTPUT_MASTER_PLUG register definition . 22
7.6 INPUT_MASTER_PLUG register definition . 23
7.7 OUTPUT_PLUG_CONTROL register definition . 23
7.8 INPUT_PLUG_CONTROL register definition . 25
7.9 Plug control register modification rules . 26
7.10 Bus reset . 27
7.11 Plug control register access rules . 27
8 Connection management procedures (CMP) . 28
8.1 Introduction . 28
8.2 Managing point-to-point connections . 29
8.2.1 Procedure for establishing a point-to-point connection . 29
8.2.2 Procedure for overlaying a point-to-point connection . 30
8.2.3 Procedure for breaking a point-to-point connection . 31
8.3 Managing broadcast-out connections . 32
8.3.1 Procedure for establishing a broadcast-out connection . 32
8.3.2 Procedure for overlaying a broadcast-out connection. 33
8.3.3 Procedure for breaking a broadcast-out connection . 33
8.4 Managing broadcast-in connections. 34
61883-1 IEC:2008 – 3 –
8.4.1 Procedure for establishing a broadcast-in connection . 34
8.4.2 Procedure for overlaying a broadcast-in connection . 35
8.4.3 Procedure for breaking a broadcast-in connection . 35
8.5 Managing connections after a bus reset . 36
8.5.1 Procedure for restoring a point-to-point connection after a bus reset . 36
8.5.2 Procedure for restoring a broadcast-out connection after a bus reset . 37
8.5.3 Procedure for restoring a broadcast-in connection after a bus reset . 38
9 Function control protocol (FCP) . 38
9.1 Introduction . 38
9.2 Asynchronous packet structure . 39
9.3 FCP frame structure . 40
9.3.1 Vendor unique command/transaction set . 41
9.3.2 Extended command/transaction set . 42
Figure 1 – Configuration ROM . 10
Figure 2 – Isochronous packet . 12
Figure 3 – CIP header . 13
Figure 4 – Model of transmission of source packets . 14
Figure 5 – Two quadlets CIP header (Form_0, Form_1=0) . 14
Figure 6 – Source packet header format . 15
Figure 7 – Plug and PR usage . 19
Figure 8 – Connections . 20
Figure 9 – Plug state diagram . 21
Figure 10 – oMPR format . 22
Figure 11 – iMPR format . 23
Figure 12 – oPCR format . 24
Figure 13 – iPCR format . 26
Figure 14 – PCR address map . 27
Figure 15 – Point-to-point and broadcast connection counter modifications . 29
Figure 16 – Establishing a point-to-point connection . 30
Figure 17 – Overlaying a point-to-point connection . 31
Figure 18 – Breaking a point-to-point connection . 32
Figure 19 – Establishing a broadcast-out connection . 33
Figure 20 – Overlaying a broadcast-out connection. 33
Figure 21 – Breaking a broadcast-out connection . 34
Figure 22 – Establishing a broadcast-in connection . 35
Figure 23 – Overlaying a broadcast-in connection . 35
Figure 24 – Breaking a broadcast-in connection. 36
Figure 25 – Time chart of connection management and PCR activities . 36
Figure 26 – Restoring a point-to-point connection . 37
Figure 27 – Restoring a broadcast-out connection . 38
Figure 28 – Restoring a broadcast-in connection . 38
Figure 29 – Command register and response register . 39
Figure 30 – Write request for data block packet of IEEE 1394 . 40
Figure 31 – Write request for data quadlet packet of IEEE 1394 . 40
– 4 – 61883-1 IEC:2008
Figure 32 – FCP frame structure . 41
Figure 33 – Vendor unique frame format . 42
Table 1 – Unit_SW_Version code assignment . 11
Table 2 – Code allocation of FN . 15
Table 3 – Time stamp field of source packet header . 16
Table 4 – Placing of data block sequence . 16
Table 5 – Code allocation of FMT . 16
Table 6 – Time stamp of SYT field . 17
Table 7 – oMPR/iMPR/oPCR speed encoding spd and extended speed encoding xspd . 22
Table 8 – oPCR overhead ID encoding . 25
Table 9 – CTS: Command/transaction set encoding . 41
61883-1 IEC:2008 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
CONSUMER AUDIO/VIDEO EQUIPMENT –
DIGITAL INTERFACE –
Part 1: General
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
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4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
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5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
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other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61883-1 has been prepared by technical area 4, Digital system
interfaces and protocols, of IEC technical committee 100: Audio, video and multimedia
systems and equipment.
This third edition of IEC 61883-1 cancels and replaces the second edition, published in 2003,
of which it constitutes a technical revision.
The significant technical changes with respect to the second edition are as follows:
– allocation of a new FMT code for the 1394 Trade Association specification ‘601 over
1394’;
– Clarification of the meaning of FMT code;
– harmonization of IEC 61883-1 with IEEE 1394.1 for speeds over S400.
This bilingual version (2012-08) corresponds to the monolingual English version, published in
2008-02.
– 6 – 61883-1 IEC:2008
The text of this standard is based on the following documents:
CDV Report on voting
100/1236/CDV 100/1336/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The French version of this standard has not been voted upon.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 61883 series, under the general title Consumer audio/video
equipment – Digital interface, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
61883-1 IEC:2008 – 7 –
CONSUMER AUDIO/VIDEO EQUIPMENT –
DIGITAL INTERFACE –
Part 1: General
1 Scope and object
This part of IEC 61883 specifies a digital interface for consumer electronic audio/video
equipment using IEEE 1394. It describes the general packet format, data flow management
and connection management for audio-visual data, and also the general transmission rules for
control commands.
The object of this standard is to define a transmission protocol for audio-visual data and
control commands which provides for the interconnection of digital audio and video
equipment, using IEEE 1394.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEEE 212:2001, Standard for a Control and Status Registers (CSR) – Architecture for
microcomputer buses
IEEE 1394:1995, Standard for a High Performance Serial Bus
IEEE 1394a:2000, Standard for a High Performance Serial Bus – Amendment 1
NOTE Throughout this document, the term “IEEE 1394” indicates a reference to the standard that is the result of
the editorial combination of IEEE 1394:1995 and IEEE 1394a:2000. Devices conforming solely to IEEE 1394:1995
may conform to IEC 61883. Devices conforming to IEC 61883 should conform to IEEE 1394a:2000.
3 Abbreviations
For the purpose of this document, the following abbreviations apply.
AV/C Audio Video Control
CHF CIP Header Field
CIP Common Isochronous Packet
CMP Connection Management Procedures
CSR Command and Status Register
CTS Command/Transaction Set
CRC Cyclic Redundancy Check Code
DVCR Digital Video Cassette Recorder
EOH End of CIP Header
FCP Function Control Protocol
iPCR Input Plug Control Register
iMPR Input Master Plug Register
MPEG Motion Picture Experts Group
oPCR Output Plug Control Register
– 8 – 61883-1 IEC:2008
oMPR Output Master Plug Register
ROM Read Only Memory
spd Speed Encoding
xspd Extended Speed Encoding
For clarity, field names are shown in italics in this standard.
4 High-performance serial bus layers
4.1 Cable physical layer
All cable physical layer implementations conforming to this standard shall meet the
performance criteria specified by IEEE 1394. Either the cable and connector defined in
IEEE 1394:1995, or the cables and connector defined in IEEE 1394a:2000, shall be used.
When necessary for an AV device to generate a bus reset, it shall follow the requirements of
IEEE 1394a:2000, 8.2.1. An AV device that initiates a bus reset should generate an arbitrated
(short) bus reset, as specified by IEEE 1394a:2000, in preference to the long bus reset
defined by IEEE 1394:1995.
4.2 Link layer
All link layer implementations conforming to this standard shall meet the specifications of
IEEE 1394.
4.3 Transaction layer
All transaction layer implementations conforming to this standard shall meet the specifications
of IEEE 1394.
5 Minimum node capabilities
A node shall conform to the following requirements.
– A node shall be cycle master capable. This is because every node has the possibility to be
assigned as a root.
− A node shall be isochronous resource manager capable, as specified by IEEE 1394:1995,
and shall implement the additional isochronous resource manager facilities and
responsibilities specified by IEEE 1394a:2000 in 8.3.1.5, 8.3.2.3.8, 8.3.2.3.11, 8.4.2.3 and
8.4.2.6A.
− A node which transmits or receives isochronous packets shall have plug control registers
(see 7.2).
5.1 Serial bus management
Bus manager capability is optional for AV devices, but, if implemented by devices conforming
to this standard, shall conform to IEEE 1394.
5.2 Command and status registers
5.2.1 CSR core registers
This standard conforms to the CSR architecture. Details of its registers are specified by
IEEE 1394.
The STATE_CLEAR.cmstr bit shall be implemented as specified by IEEE 1394a:2000, 8.3.2.2.1.
61883-1 IEC:2008 – 9 –
NOTE The cmstr bit is set automatically (see IEEE 1394a:2000, 8.3.2.2.1) by system software or hardware when
a node becomes the new root after the bus reset process is completed. In this manner, it is possible to ensure the
fast resumption and continuity of data transmission where the time scale is critical at the level of microseconds.
The rapid activation of a new cycle master decreases the likelihood of a gap in the transmission of cycle start
packets; uninterrupted transmission of cycle start packets at nominal 125 µs intervals is critical to the delivery of
isochronous data within its latency requirements.
5.2.2 Serial bus node registers
Implementation requirements for bus-dependent registers in this standard conform to
IEEE 1394. A node shall have the following registers:
CYCLE_TIME register
BUS_TIME register
BUS_MANAGER_ID register
BANDWIDTH_AVAILABLE register
CHANNELS_AVAILABLE register
A node should have the following register specified by IEEE 1394a:2000:
BROADCAST_CHANNEL register
5.2.3 Configuration ROM requirements
A node shall implement the general ROM format as defined in IEEE 1212:2001 and
IEEE 1394. Additional information required for implementations of this standard shall be
included in one of the unit directories. Figure 1 shows an example of the configuration ROM
implementation for this standard.
– 10 – 61883-1 IEC:2008
)
Offset (Base address FFFF F000 0000
Bus_info_block
04 00 04 crc_length rom_crc_value
16 16
04 04
" 1 3 9 4
04 08 Reserved cyc_clk_acc max_rec Reserved
04 0C node_vendor_id chip_id_hi
04 10
16 chip_id_lo
Root_directory
04 14
16 root_length CRC
04 18
16 03 module_vendor_id
04 1C
0C
16 16 node_capabilities
04 20
16 8D node_unique_id offset
04 24 D1 unit_directory offset
04 28
:
Optional
Unit_directory
unit_directory_length
CRC
12 unit_spec_id
13 unit_sw_version
:
Optional
Node_unique_id leaf
00 02 CRC
node_vendor_id
chip_id_hi
chip_id_lo
IEC 305 9/02
Figure 1 – Configuration ROM
irmc
cmc
isc
bmc
61883-1 IEC:2008 – 11 –
5.2.3.1 Bus_Info_Block entry
Implementation requirements for the Bus_Info_Block in this standard shall conform to
IEEE 1394.
5.2.3.2 Root directory
The following entries shall be present:
− Module_Vendor_ID;
− Node_Capabilities;
− Unit_Directory (offset to a unit directory defined by this standard).
Other entries may be implemented in addition to the above required entries.
5.2.3.3 Unit directory
The following entries shall be present:
− Unit_Spec_ID;
− Unit_SW_Version.
The value of the Unit_Spec_ID and the Unit_SW_Version for this standard are given as
follows:
Unit_Spec_ID: First octet = 00
Second octet = A0
Third octet = 2D
Unit_SW_Version: First octet = 01
The second and third octets of Unit_SW_Version for this standard are specified in Table 1
and indicate capabilities for command/transaction sets. The Unit_SW_Version field is used to
identify which protocol is supported by the device. If a device supports more than one
protocol, the device shall have a separate unit directory for each protocol supported.
Table 1 – Unit_SW_Version code assignment
Unit_SW_Version Command/transaction set
01 00 00 Reserved
01 00 01 AV/C protocol
01 00 02 Reserved for standardization by CAL
01 00 04 Reserved for standardization by EHS
01 00 08 HAVi protocol
01 00 0A Automotive
01 40 00 Vendor unique
01 40 01 Vendor unique
Other values Reserved for future standardization
– 12 – 61883-1 IEC:2008
6 Real time data transmission protocol
6.1 Common isochronous packet (CIP) format
6.1.1 Isochronous packet structure
The structure of the isochronous packet utilized by this standard is illustrated in Figure 2. The
packet header and header CRC are the first two quadlets of an IEEE 1394 isochronous
packet. The CIP header is placed at the beginning of the data field of an IEEE 1394
isochronous packet, immediately followed by zero or more data blocks.
IEC 3060/02
Figure 2 – Isochronous packet
6.1.2 Packet header structure
The packet header consists of the following items as specified in IEEE 1394.
Data_length: specifies the length of the data field of the isochronous packet in bytes, which
is determined as follows:
CIP header size + signal data size
Tag: provides a high level label for the format of data carried by the isochronous
packet
00 = No CIP header included
01 = CIP header included as specified in 6.1.3
10 = Reserved
11 = Reserved
Channel: specifies the isochronous channel number for the packet
Tcode: specifies the packet format and the type of transaction that shall be performed
(fixed at 1010 )
Sy: application-specific control field
61883-1 IEC:2008 – 13 –
6.1.3 CIP header structure
The CIP header is placed at the beginning of the data field of an IEEE 1394 isochronous
packet. It contains information on the type of the real time data contained in the data field
following it. The structure of the CIP header is shown in Figure 3.
1 quadlet = 32 bits
1bit 1bit
CHF_0
EOH_0 = 0
Form_0
Form_1 CHF_1
EOH_1 = 0
EOH_n = 1 CHF_n
Form_n
IEC 3061/02
Figure 3 – CIP header
The definitions of the fields are given as follows:
EOH_n (End of CIP header): means the last quadlet of a CIP header
0 = Another quadlet will follow
1 = The last quadlet of a CIP header
Form_n: in combination with EOH, shows the additional structure of
CHF_n
th
CHF_n (CIP header field):
CIP header field of n quadlet. The additional structure of
CHF_n depends on EOH_0, form_0, EOH_1, form_1, .
EOH_n, and form_n
6.2 Transmission of fixed-length source packet
This protocol transfers a stream of source packets from an application on a device to an
application on other device(s). A source packet is assumed to have a fixed length, which is
defined for each type of data. The data rate can be variable.
A source packet may be split into 1, 2, 4 or 8 data blocks, and zero or more data blocks are
contained in an IEEE 1394 isochronous packet. A receiver of the packet shall collect the data
blocks in the isochronous packet and combine them to reconstruct the source packet to send
to the application.
A model conforming to these requirements is shown in Figure 4.
– 14 – 61883-1 IEC:2008
IEC 3062/02
Figure 4 – Model of transmission of source packets
6.2.1 Two-quadlet CIP header (form_0=0, form_1=0)
This standard defines the two-quadlet CIP header for a fixed length source packet. There are
two types for the structure of the two-quadlet CIP header as shown in Figure 5. One is the
CIP header with SYT field (Figure 5a), and the other is the CIP header without SYT field
(Figure 5b). If a device transmits real time data (identified by FMT) and requires time stamp in
the CIP header, it shall use the SYT format.
SP
0 0 SID DBS FN QPC rsv DBC
H
1 0 FMT FDF SYT
IEC 3063/02
Figure 5a – CIP header with SYT field
SP
0 0 SID DBS FN QPC rsv DBC
H
1 0 1 FMT FDF
IEC 3064/02
Figure 5b – CIP header without SYT field
Figure 5 – Two quadlets CIP header (Form_0, Form_1=0)
The definitions of the fields are given as follows.
− SID: Source node ID (node ID of transmitter)
− DBS: Data block size in quadlets
61883-1 IEC:2008 – 15 –
DBS field is 8 bits because 256 quadlets is the maximum payload size for S100 mode.
When 8 bits are all 0, it means 256 quadlets; and 00000001 to 11111111 means
2 2
1 quadlet to 255 quadlets accordingly.
00000000 = 256 quadlets
00000001 = 1 quadlet
00000010 = 2 quadlets
............ ...............
11111111 = 255 quadlets
Several data blocks may be put into a bus packet, which is a packet to be transmitted on
the bus, if a higher bandwidth is required for S200 and S400 speed.
NOTE S100, S200 and S400 are transmission speeds as defined in IEEE 1394.
− FN: Fraction number
The number of data blocks into which a source packet is divided. The allowable numbers
and allocated FN codes are listed in Table 2.
Table 2 – Code allocation of FN
FN Description
00 Not divided
01 Divided into two data blocks
10 Divided into four data blocks
11 Divided into eight data blocks
− QPC: Quadlet padding count (0 quadlet to 7 quadlets)
The number of dummy quadlets padded at the end of every source packet to enable
division into equally sized data blocks. The value of all bits in padding quadlets is always
zero.
The number of padding quadlets shall be less than the number of data blocks into which
every source packet is divided, as encoded by FN.
The number of padding quadlets shall be less than the size of a single data block, as
encoded by DBS. Consequently, a data block shall never consist entirely of padding
quadlets.
− SPH: Source packet header
The value one indicates that the source packet has a source packet header. The format
of the source packet header is shown in Figure 6. Code allocation of the time stamp field
is shown in Table 3. When a time stamp is indicated, the time stamp field shall be
encoded as the lower 25 bits of the IEEE 1394 CYCLE_TIME register. Other bits are
reserved for future extension and shall be zeros.
Reserved Time stamp
IEC 3065/02
Figure 6 – Source packet header format
– 16 – 61883-1 IEC:2008
Table 3 – Time stamp field of source packet header
Time stamp field
Description
Higher 13 bits Lower 12 bits
0 0000 0000 0000 0000 0000 0000
2 2
to and to Time stamp
0 1111 0011 1111 1011 1111 1111
2 2
1 1111 1111 1111 and 1111 1111 1111 No information
2 2
Other values Reserved
− Rsv: Reserved for future extension and shall be zeros
− DBC: Continuity counter of data blocks for detecting a loss of data blocks
The value refers to the first data block following the CIP header in the bus packet. The
lower FN bits contain the sequence number of the data block within its source packet.
The remaining 8-FN bits form the sequence number of the source packet. The first data
block of any source packet always has a sequence number with value zero. If FN is zero,
then all 8 bits of DBC are used to represent a source packet sequence number. See also
Table 4.
Table 4 – Placing of data block sequence
FN Bits of DBC showing the place of data block sequence
(Not divided)
01 Shown in the lowest 1 bit
Shown in the lowest 2 bits
11 Shown in the lowest 3 bits
Table 5 – Code allocation of FMT
FMT Description
00 0000 DVCR
00 0001 601 over 1394
00 0010
to Reserved
00 1111
01 0000 Audio and music
01 0001
to Reserved
01 1101
01 1110 Free (vendor unique)
01 1111 Reserved
10 0000 MPEG2-TS
10 0001 ITU-R B0.1294 System B
10 0010
to Reserved
10 1101
11 1110 Free (vendor unique)
11 1111 No data
61883-1 IEC:2008 – 17 –
− FMT: Format ID.
The code allocation is illustrated in Table 5.
If FMT is 111111 (no data), the fields for DBS, FN, QPC, SPH and DBC are ignored and
no data blocks shall be transmitted. For other values of FMT, data is present and the
most significant bit of the FMT field indicates whether or not a time stamp in SYT format
is present. When the most significant bit of FMT is zero, the FMT-dependent field
contains a time stamp in the format specified by SYT. Otherwise, the FMT-dependent
field shall not contain an absolute time stamp. See also Figure 5 and Table 5.
NOTE The distinction between absolute time stamps, for example, those in the SYT format, and relative time
stamps is crucial to the operation of Serial Bus bridges. Absolute time stamps require readjustment by each
bridge whereas relative time stamps do not. Consult IEEE 1394.1:2004 for details.
− FDF: Format dependent field
This field is defined for each FMT.
− SYT: The code allocation of the SYT field is shown in Table 6. When a time stamp is
indicated by the most significant bit of the FMT field, the SYT field shall be encoded as
the lower 16 bits of the IEEE 1394 CYCLE_TIME register.
Table 6 – Time stamp of SYT field
SYT
Description
Higher 4 bits Lower 12 bits
0000 0000 0000 0000
2 2
to and to Time stamp
1111 1011 1111 1111
2 2
11112 and 1111 1111 11112 No information
Other values Reserved
6.2.2 Isochronous packet transmission
Active transmitters shall send an isochronous packet in every cycle. If no data block is
available, an empty packet shall be sent. An empty packet shall always contain a two-quadlet
CIP header. The DBC field of an empty packet shall show the count for the first data block
contained in the first non-empty IEEE 1394 isochronous packet for the same transmission
stream following this empty packet. The other fields shall match the fields of the CIP header
of non-empty packets on the same transmission stream.
7 Isochronous data flow management
7.1 General
To start and stop isochronous data flows on the bus and to control their attributes, the
concept of plugs and plug control registers is used. Plug control registers are special purpose
CSR registers.
NOTE Plugs do not physically exist on an AV device. Only the concept of a plug is used to establish an analogy
with existing AV devices where each flow of information is routed via a physical plug.
This clause describes the contents of the plug control registers and how they may be
modified. The set of procedures that use the plug control registers to control an isochronous
data flow are called connection management procedures (CMP). The CMP that shall be used
by AV devices are described in Clause 8.
– 18 – 61883-1 IEC:2008
7.2 Plugs and plug control registers
An isochronous data flow flows from one transmitting AV device to zero or more receiving AV
devices by sending isochronous packets on one isochronous channel of the IEEE 1394 bus.
An isochronous channel shall carry not more than one isochronous data flow and each
isochronous data flow shall be carried on one isochronous channel.
Each isochronous data flow is transmitted to an isochronous channel through one output plug
on the transmitting AV device and it is received from that isochronous channel through one
input plug on each of the receiving AV devices. Each input and output plug shall not carry
more than one isochronous data flow.
The transmission of an isochronous data flow through an output plug is controlled by one
output plug control register (oPCR) and one output master plug register (oMPR) located on the
transmitting AV device. On each AV device there is only one OUTPUT_MASTER_PLUG
register for all output plugs. The OUTPUT_MASTER_PLUG register controls all attributes that
are common to all isochronous data flows transmitted by the corresponding AV device. The
OUTPUT_PLUG_CONTROL register controls all attributes of the corresponding isochronous
data flow that are independent from attributes of other isochronous data flows transmitted by
that AV device.
The reception of an isochronous data flow through an input plug is controlled by one input
plug control register (iPCR) and one input master plug register (iMPR) located on the
receiving AV device. On each AV device there is only one INPUT_MASTER_PLUG register
for all input plugs. The INPUT_MASTER_PLUG register controls all attributes that are com-
mon to all isochronous data flows received by the corresponding AV device. The
INPUT_PLUG_CONTROL register controls all attributes of the corresponding isochronous
data flow that are independent from attributes of other isochronous data flows received by
that AV device.
An isochronous data flow can be controlled by any device connected to the IEEE 1394 bus by
modifying the corresponding plug control registers. Plug control registers can be modified
by means of asynchronous transactions on the IEEE 1394 bus or by internal modifications if
the plug control registers are located on the controlling device.
The use of plugs and plug control registers is illustrated in Figure 7.
61883-1 © IEC:2008 – 19 –
AV–device
iMPR
iPCR[0]
iPCR[1]
IEEE 1394 bus
Isochronous. channel x
Isochronous channel y
iPCR[0]
oPCR[1]
oPCR[0] oPCR[1] oPCR[2]
iMPR
oMPR oMPR
AV–device AV–device
Isochronous data flow
IEC 3066/02
Figure 7 – Plug and PR usage
Let #iPCR and #oPCR denote the number of isochronous data flows that can be
simultaneously received and transmitted respectively by an AV device (such as a multiple
viewing device or a multiple tuner device). Both #iPCR and #oPCR shall be constants in the
range [0 to 31] that are AV device-dependent.
Each AV device shall implement #oPCR output plugs, each controlled by one separate
OUTPUT_PLUG_CONTROL register, and #iPCR input plugs, each controlled by one separate
INPUT_PLUG_CONTROL register. For AV devices implementing INPUT_PLUG_CONTROL
registers, a single INPUT_PLUG_CONTROL register within that AV device shall be
denoted as INPUT_PLUG_CONTROL[i], where i is in the range [0 to #iPCR-1]. The
INPUT_MASTER_PLUG register is optional when #iPCR = 0 and required otherwise.
For AV devices implementing OUTPUT_PLUG_CONTROL registers, a single
OUTPUT_PLUG_CONTROL register within that AV device shall be denoted
as OUTPUT_PLUG_CONTROL[i], where i is in the range [0 to #oPCR-1]. The
OUTPUT_MASTER_PLUG register is optional if #oPCR = 0 and required otherwise.
The mapping between an INPUT_PLUG_CONTROL register and an isochronous data flow in
a receiving AV device, and the mapping between an OUTPUT_PLUG_CONTROL register and
an isochronous data flow in a transmitting AV device, are AV device-dependent.
7.3 Connections
To transport isochronous data between two AV devices on the IEEE 1394 bus, it is necessary
for an application to connect an output
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