IEC TR 62856:2013

Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)

IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.

Documentation sur les sujets concernant l'automatisation de la conception - Langages BVDL (Bird's-eye View of Design Languages)

La CEI/TR 62856:2013 décrit des caractéristiques pour des langages de conception existants, ainsi que pour améliorer et renouveler des langages de conception qui appartiennent aux processus de conception définis du Système sur puce (SoC) allant de la conception au niveau système, de la mise en oeuvre et de la vérification SoC, de la création de bloc IP et de la conception de bloc analogique jusqu'à la préparation des données d'interface pour la fabrication. Trente-trois langages de conception sont choisis et la dernière version de chaque langage est reprise dans le présent rapport, à la date de mars 2011:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL et IP-XACT.

General Information

• Status: Published
• Publication Date: 06-Aug-2013
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.240.50 - IT applications in industry
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 13 - TC 91/WG 13
• Current Stage: PPUB - Publication issued
• Start Date: 07-Aug-2013
• Completion Date: 30-Nov-2013

Overview

IEC TR 62856:2013, titled Documentation on Design Automation Subjects - The Bird's-eye View of Design Languages (BVDL), is a comprehensive technical report published by the International Electrotechnical Commission (IEC). This report provides an in-depth analysis and overview of thirty-three widely used electronic design languages essential for the System on a Chip (SoC) design ecosystem. Covering the full spectrum from system-level design to manufacturing data preparation, the standard is a critical resource for professionals involved in electronic design automation (EDA), semiconductor industries, and SoC development.

The standard’s primary goal is to present a clear, consolidated understanding of existing design languages, their features, and potential enhancements to support future development. It helps facilitate consistent EDA standardization across diverse design processes, thereby improving productivity, interoperability, and quality in electronic system design.

Key Topics

• Scope of Design Languages
  The report surveys 33 design languages, such as UML, SystemC, VHDL, Verilog HDL, System Verilog, SPICE, and IP-XACT. It covers languages relevant to various stages of SoC design including:

  • System level design and specification
  • SoC implementation, verification, and IP block creation
  • Analog/mixed-signal block design
  • Interface data preparation for manufacturing

• Comprehensive Design Process Mapping
  The BVDL documentation breaks down the design ecosystem into a chart and tables classified into:

  • Electronic system design
  • SoC design and verification
  • Mixed-signal verification and analog design
  • Characterization and IP preparation
    This structure enables users to quickly identify which design languages apply to specific phases and roles in the SoC workflow.

• Standardization and Evolution
  The report aids design language developers and technical managers by helping to:

  • Assess language feature overlaps and redundancies
  • Understand consistency within the evolving design ecosystem
  • Address future challenges and emerging technological advances
    It supports ongoing international collaboration toward harmonized EDA standards.

• Use Cases
  Practical use cases include ensuring design flow consistency, monitoring language evolution, and anticipating new standardization demands driven by innovative technology trends.

Applications

IEC TR 62856:2013 serves a broad range of stakeholders in the electronics and semiconductor industries, especially:

• EDA Tool Developers:
  Gain insights into supported languages, enabling more integrated design toolchains that span multiple phases of SoC development.

• Chip Designers and System Architects:
  Identify appropriate languages for design specification, verification, and implementation-improving design quality and turnaround times.

• Standardization Bodies and Industry Consortia:
  Use BVDL as a strategic reference to streamline standardization efforts, reduce duplication, and coordinate language development internationally.

• Academic and Research Institutions:
  Utilize the report as a teaching resource and to guide research on design automation and language features suitable for next-generation SoC challenges.

Related Standards

The IEC TR 62856 complements other international standards and frameworks in the realm of electronic design automation including:

• Hardware Description Languages (HDL):
  Standards such as IEEE VHDL, IEEE Verilog HDL, and SystemVerilog provide formal syntax and semantics for hardware modeling.

• Electronic System Level (ESL) Languages:
  SystemC and SystemC-AMS standards for system-level modeling and mixed-signal simulation.

• Standardized Design Data Formats:
  Formats such as DEF, LEF, Liberty, and IP-XACT facilitate interoperability between various EDA tools across the physical design and manufacturing interface stages.

• Verification Languages and Methodologies:
  Standards like PSL (Property Specification Language) and UVM for hardware verification enhance design validation approaches.

By unifying the view of these languages and formats, IEC TR 62856 enhances global coordination and efficiency in SoC design automation.

---

Keywords:
IEC TR 62856, BVDL, design automation, System on a Chip, SoC design, electronic design languages, EDA standards, hardware description languages, design ecosystem, standardization, semiconductor design, verification languages, analog block design, IP block creation, electronic system design

Standards Content (Sample)

IEC/TR 62856 ®
Edition 1.0 2013-08
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
Documentation on design automation subjects – The Bird’s-eye View of Design
Languages (BVDL)
Documentation sur les sujets concernant l'automatisation de la conception –
Langages BVDL (Bird’s-eye View of Design Languages)
IEC/TR 62856:2013
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IEC/TR 62856 ®
Edition 1.0 2013-08
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
Documentation on design automation subjects – The Bird’s-eye View of Design

Languages (BVDL)
Documentation sur les sujets concernant l'automatisation de la conception –

Langages BVDL (Bird’s-eye View of Design Languages)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX S
ICS 25.040 ISBN 978-2-8322-1028-4

– 2 – TR 62856 © IEC:2013
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Structure and content of the Bird’s-eye View of Design Languages . 8
2.1 Structure of the Bird’s-eye View of Design Languages . 8
2.2 Chart of design processes. 9
2.3 Table of “Electronic system design” . 10
2.4 Table of “SoC design” . 10
2.5 Table of “Mixed-signal verification” and analog block design” . 11
2.6 Table of “Characterization and IP preparation” . 12
2.7 Reading the Bird’s-eye View of Design Languages . 13
2.7.1 General . 13
2.7.2 Case 1): Multiple marks in one design object . 13
2.7.3 Case 2): Multiple marks in the same design objects in the
different processes . 14
3 Use case of the Bird’s-eye View of Design Languages . 14
3.1 Case 1): Investigation of consistency of flow . 14
3.2 Case 2): Evolution of language and standardization . 15
3.3 Case 3): Emergence of new technology . 15
4 The Bird’s-eye View of Design Languages (BVDL), version 1.0 . 15
4.1 Design processes . 15
4.2 Electronic system design . 16
4.3 SoC design . 17
4.4 Mixed-signal verification and analog block design . 20
4.5 Characterization and IP preparation . 21

Figure 1 – Electronic design ecosystem . 7
Figure 2 – Chart and table of BVDL . 8
Figure 3 – Structure of the table. 9
Figure 4 – Chart of design processes . 9
Figure 5 – “Electronic system design” table . 10
Figure 6 – Part of “SoC design” table . 11
Figure 7 – Part of “Mixed-signal verification and analog block design” table . 12
Figure 8 – “Characterization and IP preparation” table . 13
Figure 9 – Multiple marks in one design object . 14
Figure 10 – Multiple marks in the same design objects in the different processes . 14
Figure 11 – Chart of design processes . 15

TR 62856 © IEC:2013 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DOCUMENTATION ON DESIGN AUTOMATION SUBJECTS –
THE BIRD’S-EYE VIEW OF DESIGN LANGUAGES (BVDL)

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in
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The main task of IEC technical committees is to prepare International Standards. However, a
technical committee may propose the publication of a technical report when it has collected data
of a different kind from that which is normally published as an International Standard, for
example "state of the art".
IEC 62856, which is a technical report, has been prepared by IEC technical committee 91:
Electronics assembly technology:
The text of this technical report is based on the following documents:
Enquiry draft Report on voting
91/1085/DTR 91/1101/RVC
Full information on the voting for the approval of this technical report can be found in the report
on voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until the
stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data related to
the specific publication. At this date, the publication will be

– 4 – TR 62856 © IEC:2013
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

TR 62856 © IEC:2013 – 5 –
INTRODUCTION
The automation of design and manufacturing technologies in electronic industries has been
evolving world-wide for over three decades with remarkable development speed. Electronic
design automation (EDA) technology enables the conceptualization, implementation and
validation of electronic systems, that is, transforms the ideas and objectives of the system
designers into manufacturable and testable representations in a cost-effective way. It is
classified into three key categories such as design methodologies, design libraries and design
tools. Standardization involves computer-sensible representations throughout the overall
design processes which integrate design libraries and design tools to build a design ecosystem.
In the semiconductor industry EDA technologies have been substantially contributing to the
unprecedented industry growth for three decades. To emerging new product lines such as
microcontroller, microprocessor, ASIC, FPGA, memories, analog and mixed-signal and System
on a chip (SoC) they have been continuously providing a wide range of solutions to meet critical
requirements on design productivity enhancement and design quality improvement.
The EDA technical committee (EDA-TC) was formed in JEITA in 1990 in order to take initiatives
for international EDA standardization in Japan. Since then, it has been contributing design
language standardization such as EDIF, VHDL, Verilog HDL, Delay and Power Calculation
(DPC), System C, System Verilog and Power Format, which led to forming the new working
group at which experts from the industry and academia were invited and to work with IEC TC93,
IEEE DASC, Accellera, Open SystemC Initiatives (OSCI) and others. After having been active
for over two decades the need was felt for a bird’s-eye view of the existing tens of design
languages, and to enhance or develop them in order to set the strategy towards international
EDA standardization. EDA-TC initiated the project in early 2009 to develop the Bird’s-eye View
of Design Languages (BVDL) spreadsheet documentation. It developed the first version in
March 2010, in order to have an important participation of design technology experts from the
semiconductor industry and academia. It finalized the BVDL documentation combined with the
spreadsheet as a JEITA technical report in March 2011.

– 6 – TR 62856 © IEC:2013
DOCUMENTATION ON DESIGN AUTOMATION SUBJECTS –
THE BIRD’S-EYE VIEW OF DESIGN LANGUAGES (BVDL)

1 Scope
The BVDL originally aims to make full use of planning and decision-making on EDA
standardization activities for a technical expert as well as a manager in JEITA. It facilitates the
understanding of the various design languages to show their positioning and features. Also it
provides easy overviews of each design language for a newcomer to the EDA standards
community and/or for a designer as a user of an EDA design ecosystem. Especially for a
design language developer that aims to directly join design language development and voting
for standardization, it provides metrics to check for duplication among similar languages,
consistency to develop the design ecosystem and future challenges for design languages.
EDA standards provide a mechanism to define common semantics for electronic design
ecosystems among various design tools depicted in Figure 1. The state-of-the-art standards
are classified into hardware description languages, hardware verification languages, electronic
system level design languages, library formats, design constrain formats, interface formats with
manufacturing and testing, design data exchange formats, data models and application
procedure interfaces (API), etc. Therefore they are generally called standard design languages
in a narrow sense. The semiconductor industry has been facing new design complexity barriers
and is today facing unprecedented complexities brought by the convergence of product
features in terms of silicon process technology, system technology, high gate count and
embedded software incorporation. This new design complexity requires integrated EDA
solutions and at the same time impacts design ecosystem and standard design languages as
well. So a new design language development or new features enhancement to an existing
design language is needed. As a result tens of design languages, which might be classified into
de jure standard language, de facto standard language, forum standard language and common
language used in some community, are developed, enhanced or actually used in the industries,
academia and communities world-wide.

TR 62856 © IEC:2013 – 7 –
IEC  1944/13
Figure 1 – Electronic design ecosystem
This technical report describes features for existing design languages, as well as for enhancing
and newly developing design languages belonging to the defined design processes of System
on a chip (SoC) which ranges from system level design, SoC design implementation and
verification, IP block creation and analog block design down to interface data preparation for
manufacturing. These simplified design processes might not become obsolete despite the
remarkable speed of the evolution of electronic design automation and seem easier to
understand for a non-EDA expert.
Thirty-three design languages have been chosen and each feature of their latest version as of
March 2011 is reflected in this report:
UML
Esterel
Rosetta
SystemC
SystemC-AMS
IBIS
CITI
TouchStone
BSDL
System Verilog
VHDL
Verilog HDL
UPF
CPF
– 8 – TR 62856 © IEC:2013
e language
PSL
FSDB
SDC
DEF
Open Access
SDF
GDS II
OASIS
STIL
WGL
Verilog-A
Verilog-AMS
SPICE
VHDL-AMS
LEF
Liberty
CDL
IP-XACT.
2 Structure and content of the Bird’s-eye View of Design Languages
2.1 Structure of the Bird’s-eye View of Design Languages
In 2.1, the overall structure of the Bird’s-eye View of Design Languages (BVDL) is described.
BVDL consists of one chart and four tables (see Figure 2).
Chart Table
IEC  1945/13
Figure 2 – Chart and table of BVDL
The purpose of BVDL is to show the positions and features of the design languages in the
design processes. To help recognize them, major design processes are defined and design
processes are classified into four processes such as “Electronic system design”, “SoC design”,
“Mixed-signal verification and analog block design", and “Characterization and IP preparation”.
The chart of BVDL shows the relations between the major design processes.
The design processes which belong to each major design process are listed in the four tables.
Each table has a structure which makes it suitable to recognize the positions and features of
the design languages. The design languages which are grouped according to design flow are in
the columns of the tables. Design objects are in the rows of the tables. The design objects are
what designers design in the design processes. For example, they are hardware description,

TR 62856 © IEC:2013 – 9 –
verification description, design constraint, and so on. They are grouped into “object groups”
which represent the category. The tables have marks which show the positions and features of
the languages. One language may appear in only one column or may appear in several
columns (see Figure 3).
Design
Processes
Design Objects
IEC  1946/13
Figure 3 – Structure of the table
2.2 Chart of design processes
In 2.2, the content of the chart of design processes is explained (see Figure 4).

IEC  1947/13
Figure 4 – Chart of design processes
In Figure 4, the four major design processes, “Electronic system design”, “SoC design”,
“Mixed-signal verification and analog block design", and “Characterization and IP preparation”
are defined.
The “Electronic system design” process is a design process to develop electronic systems. In
the design process, system requirements are analysed and then the system specifications are
defined. Printed wiring boards, packages, system architectures, and algorithms are
implemented according to the specifications.
The “SoC design” process is a design process to develop Systems on a chip (SoCs). They are
designed according to the specifications, system architectures, and algorithms which are

– 10 – TR 62856 © IEC:2013
designed in the “Electronic system design” process. In the BVDL, only the digital parts of SoC
designs are chosen. Although SoCs include analog circuits, the design processes of analog
circuits are considered in the “Analog block design” process.
The “Analog block design” process is a design process to develop analog blocks. They are
provided to the SoC design process as IPs through the “Characterization and IP preparation”
process. In the “Mixed-signal verification” process, interfaces between digital parts and analog
parts in SoC are verified.
In the “Characterization and IP preparation” process, digital IPs and analog IPs are prepared.
These IPs are provided to the other design processes.
2.3 Table of “Electronic system design”
In 2.3, the content of the “Electronic system design” table is explained (see
Figure 5).
IEC  1948/13
Figure 5 – “Electronic system design” table
The columns show the design processes in the “Electronic system design” major design
process. The design processes are printed wiring board and package designs, architecture and
algorithm designs, and requirement analyses and specifications definition. The design
languages related to the design processes are listed in the columns.
The rows show design objects which are designed in the design processes in the columns.
They are structures, logical behaviors and functions, performances and characteristics,
verification environments, I/O buffer information, boundary scan circuits, and device
characteristics. Their granularity should be small enough to make clear the difference between
languages.
The design objects are grouped into four object groups: electronic system, SoC hardware, SoC
testing, and device characteristics. The design objects, structures, logical behaviors and
functions, performances and characteristics, and verification environments belong to the
electronic system object group. The design object I/O buffer information belongs to the SoC
hardware object group. The design object boundary scan circuits belongs to the SoC testing
object group. The design object device characteristics belongs to the device characteristics
object group.
2.4 Table of “SoC design”
In 2.4, the content of the “SoC design” table is explained (see Figure 6).

TR 62856 © IEC:2013 – 11 –
IEC  1949/13
Figure 6 – Part of “SoC design” table
The columns show the design processes in the “Soc design” major design process. The design
processes are high-level designs and verifications, RTL designs and verifications, logic
synthesis, logic verifications, place and route, sign-off verification, and design manufacturing
interface. The design languages related to the design processes are listed in the columns.
The rows show design objects which are designed in the design processes in the columns.
They are structures, logical behaviors and functions, gate-level circuits, timing constraints,
power structures, floor plans, place and route data, layout data, test benches, properties,
assertions, functional coverage, transactors, test patterns, random verifications, logic and
circuit simulation results, parasitic wire capacitance and resistance, wire end point
coordinations, LVS netlist, delay time, boundary scan circuits, test data, core tests, and on-chip
scan compression structures. Their granularity should be small enough to make clear the
difference between languages.
The design objects are grouped into four object groups: SoC hardware, functional verification,
intermediate data between EDA tools, and SoC testing. In each object group, the design
objects are as follows:
In the SoC hardware object group: structures, logical behaviors and functions, gate-level
circuits, timing constraints, power structures, floor plans, place-and-route data, and layout data;
in the functional verification object group: test benches, properties, assertions, functional
coverage, transactors, test patterns, and random verifications; in the intermediate data
between EDA tools object group: logic and circuit simulation results, parasitic wire
capacitances and resistances, wire end point coordinations, LVS netlists, and delay time; and
in the SoC testing object group: boundary scan circuits, test data, core tests, and on-chip scan
compression structures.
2.5 Table of “Mixed-signal verification” and analog block design”
In 2.5, the content of the “Mixed-signal verification and analog block design” is explained (see
Figure 7).
– 12 – TR 62856 © IEC:2013
IEC  1950/13
Figure 7 – Part of “Mixed-signal verification and analog block design” table
The columns show the design processes in the “Mixed-signal verification and analog block
design” major design process. The design processes are analog functional designs,
architecture designs, transistor-level circuit designs, layout designs, post-layout circuit
verifications, and mixed-signal verifications. The design languages related to the design
processes are listed in the columns.
The rows show design objects which are designed in the design processes in the columns.
They are structures, logical behaviors and functions, logical behaviors and functions (extended
for AMS), analog behaviors and functions, gate-level circuits, transistor-level circuits, timing
constraints, power structures, floor plans, place-and-route data, layout data, test benches (also
extended for AMS), properties, assertions, functional coverage, transactors, test patterns,
random verifications, logic and circuit simulation results, parasitic wire capacitances and
resistances, wire end point coordinations, LVS netlists, delay time, and device characteristics.
Their granularity should be small enough to make clear the difference between languages.
The design objects are grouped into four design groups: SoC hardware, functional verification,
intermediate data between EDA tools, and device characteristics. In each design group, the
design objects are as follows:
In the SoC hardware design group: structures, logical behaviors and functions, logical
behaviors and functions (extended for AMS), analog behaviors and functions, gate-level
circuits, transistor-level circuits, timing constraints, power structures, floor plans,
place-and-route data, and layout data; in the functional verification object group: test benches
(also extended for AMS), properties, assertions, functional coverage, transactors, test patterns,
and random verifications; in the intermediate data between EDA tools object group: logic and
circuit simulation results, parasitic wire capacitances and resistances, wire end point
coordinations, LVS netlists, and delay time; and in the device characteristics object group:
device characteristics.
2.6 Table of “Characterization and IP preparation”
In 2.6, the content of the “Characterization and IP preparation” is explained (see Figure 8).

TR 62856 © IEC:2013 – 13 –
IEC  1951/13
Figure 8 – “Characterization and IP preparation” table
The columns show the design processes in the “Characterization and IP preparation” major
design process. The design processes are characterization and IP model preparation. The
design languages related to the design processes are listed in the columns.
The rows show design objects which are designed in the design processes in the columns.
They are logic library models, library models for place-and-route tools, layout data, delay
calculation models, LVS netlists, and IP metadata. Their granularity should be small enough to
make clear the difference between languages.
The design objects are grouped into two object group: libraries and component-models, and IP.
In each object group, the design objects are as follows:
In the libraries and component-models object group: logic library models, library model for
place-and-route tools, layout data, delay calculation models, and LVS netlists; and in the IP
object group, IP metadata.
2.7 Reading the Bird’s-eye View of Design Languages
2.7.1 General
In 2.7, what you can read from the BVDL is explained.
2.7.2 Case 1): Multiple marks in one design object
In the case where more than one language is marked in one design object in one design
process, you can read that these languages are used to develop the same design objects in the
same design process. In the example of Figure 9, in the “RTL design and verification” design
process, the design languages, SystemVerilog, Verilog, and VHDL are used to write “Logical
behavior and function” objects.

– 14 – TR 62856 © IEC:2013
These languages are used to develop one design
objects in the “RTL design & verification” process.

IEC  1952/13
Figure 9 – Multiple marks in one design object
2.7.3 Case 2): Multiple marks in the same design objects in the different processes
In the case where one language is marked in the same design objects in different design
processes, you can read that one language is used to develop the same design objects in the
different design processes. In the example of Figure 10, Verilog is used to express the same
objects, “Structure”, “Logical behavior and function”, and “Gate-level circuit” design objects in
four different design processes such as “RTL design and verification”, “Logic (gate-level)
synthesis”, “Logic (gate-level) verification”, and “Place-and-route” design processes.

One language is used to develop the
same design objects in three design
processes.
IEC  1953/13
Figure 10 – Multiple marks in the same design objects in the different processes
3 Use case of the Bird’s-eye View of Design Languages
3.1 Case 1): Investigation of consistency of flow
When you focus on the marks of one language in the different design processes, you can
recognize its continuance or discontinuance in a design flow. From this recognition, you can
make clear the problems that emerge from the fact that one language is used to design the
same objects in the different processes, and the requirements for design languages from the
design flow view.
TR 62856 © IEC:2013 – 15 –
3.2 Case 2): Evolution of language and standardization
Marks in the BVDL will change through the evolution of design languages and design
processes. By keeping track of the changes of the mark in the BVDL, you can recognize the
changes in roles of languages. These data can help make decisions on activities about
standardization.
3.3 Case 3): Emergence of new technology
The design processes in the BVDL are to be changed when new technologies emerge. In this
case, new design languages may be added in the BVDL. When marking the new BVDL, you can
recognize the roles of new languages and consistency of flow. These recognitions can help
make decisions on activities about standardization.
4 The Bird’s-eye View of Design Languages (BVDL), version 1.0
4.1 Design processes
According to the design process as illustrated in Figure 11, four spreadsheets, “Electronic
system design”, “SoC design”, “Mixed-signal verification and analog block design”, and
“Characterization and IP preparation”, are shown in 4.2, 4.3, 4.4 and 4.5 respectively.
Design Process
Electric System
1. Electronic System Design
Manufacturing
4. Characterization / IP Preparation
2. SoC Design
IP Development
3.1 Analog Block Design
(Subset of SoC Design Process)
3.2 Mixed-Signal Verification
SoC Manufacturing
IEC  1954/13
Figure 11 – Chart of design processes

– 16 – TR 62856 © IEC:2013
BSDL
TouchStone
CITI
IBIS
SystemCーAMS
SystemC
Rosetta
Esterel
UML
4.2 Electronic system design
Design Process
BVDL
PWB（Printed Wiring Board）Design , Package Design
Architecture Design, Algorithm Design
1. Elect ronic Syst em Design
Requirement Analysis, Specification Definition
Design
Language
IEEE # P1778 P1699 1666 - 1149.1b
Descript ion Object s
IEC # 62014 -
Object Group Object s
Electronic System Structure X X X X
Electronic System Logical Behavior & Function X X X X X
Electronic System Logical Behavior & Function - Extended for AMS X
Electronic System Performances & Characteristics X X X X
Electronic System Performances & Characteristics- Extended for AMS X
Electronic System Verification Environment X - X X X
Electronic System Verification Environment - Extended for AMS X
SoC Hardware I/ O Buffer Information X
SoC Testing Boundary Scan Circuits X
Device Characteristics Device Characteristics（S- Parameter, etc ） X X

TR 62856 © IEC:2013 – 17 –
CPF
UPF
SDC
VHDL
Verilog
SystemVerilog
FSDB
PSL
e
CPF
UPF
VHDL
Verilog
SystemVerilog
SystemC
4.3 SoC design
BVDL　 Design Process
Design - Manufacturing Interface
Sign- off Verification
2. SoC Design Place- and- Route
Logic (Gate- level) Verification
Logic (Gate- level) Synthesis
RTL Design & Verification
High- Level Design & Verification
Design
Language
IEEE # 1666 1800 1364 1076 1801 1647 1850 - 1800 1364 1076 1801
Descript ion Object s
IEC # 62530 61691ー4 62248 62531 - 62530 61691ー4 62248
Object Group Object s
SoC Hardware Structure X X X X X X X
SoC Hardware Logical Behavior & Function X X X X X X X
SoC Hardware Gate- Level Circuit X X X X X X
SoC Hardware Timing Constraints X
SoC Hardware Power Structure X X X X
SoC Hardware Floor plan
SoC Hardware Place- and- Route Data
SoC Hardware Layout Data
Functional Verification Test Bench X X X X X X X X
Functional Verification Property X X X X
Functional Verification Assertion X X X X
Functional Verification Functional Coverage X X X X
Functional Verification Transactor X X X
Functional Verification Test Pattern X X X X X X X
Functional Verification Random Verification X X X X
Intermediate Data between EDA tools Logic & Circuit Simulation Results X
Intermediate Data between EDA tools Parasitic Wire Capacitance
Intermediate Data between EDA tools Parasitic Wire Resistance
Intermediate Data between EDA tools Wire End Point Coordination
Intermediate Data between EDA tools LVS Netlist
Intermediate Data between EDA tools Delay Time
SoC Testing Boundary Scan Circuits
SoC Testing Test Data
SoC Testing Core Test
SoC Testing On- chip scan compression structure

– 18 – TR 62856 © IEC:2013
OASIS
GDS II
SDF
Open Access
DEF
CPF
UPF
SDC
VHDL
Verilog
SystemVerilog
FSDB
CPF
UPF
SDC
VHDL
Verilog
SystemVerilog
Design Process
BVDL
Design - Manufacturing Interface
Sign- off Verification
2. SoC Design Place- and- Route
Logic (Gate- level) Verification
Logic (Gate- level) Synthesis
RTL Design & Verification
High- Level Design & Verification
Design
Language
IEEE # 1800 1364 1076 1801 - 1800 1364 1076 1801 - 1497
Descript ion Object s
IEC # 62530 61691ー4 62248 - 62530 61691ー4 62248 -
Object Group Object s
SoC Hardware Structure X X X X X X
SoC Hardware Logical Behavior & Function X X X X X X
SoC Hardware Gate- Level Circuit X X X X X X X
SoC Hardware Timing Constraints X X
SoC Hardware Power Structure X X X X
SoC Hardware Floor plan X X
SoC Hardware Place- and- Route Data X X
SoC Hardware Layout Data X X X
Functional Verification Test Bench X X X X X X
Functional Verification Property X X
Functional Verification Assertion X X
Functional Verification Functional Coverage X X
Functional Verification Transactor X X
Functional Verification Test Pattern X X X X
Functional Verification Random Verification X X
Intermediate Data between EDA tools Logic & Circuit Simulation Results X
Intermediate Data between EDA tools Parasitic Wire Capacitance X
Intermediate Data between EDA tools Parasitic Wire Resistance X
Intermediate Data between EDA tools Wire End Point Coordination X
Intermediate Data between EDA tools LVS Netlist
Intermediate Data between EDA tools Delay Time X X
SoC Testing Boundary Scan Circuits
SoC Testing Test Data
SoC Testing Core Test
SoC Testing On- chip scan compression structure

TR 62856 © IEC:2013 – 19 –
WGL
STIL
OASIS
GDS II
OASIS
GDS II
CDL
SDF
Open Access
SPF
SPEF
DSPF
CPF
UPF
SDC
VHDL
Verilog
SystemVerilog
Design Process
BVDL
Design - Manufacturing Interface
Sign- off Verification
2. SoC Design Place- and- Route
Logic (Gate- level) Verification
Logic (Gate- level) Synthesis
RTL Design & Verification
High- Level Design & Verification
Design
Language
IEEE # 1800 1364 1076 1801 - 1481 1497 1450
Descript ion Object s
IEC # 62530 61691ー4 62248 - -
Object Group Object s
SoC Hardware Structure X X X
SoC Hardware Logical Behavior & Function X X X
SoC Hardware Gate- Level Circuit X X X
SoC Hardware Timing Constraints X
SoC Hardware Power Structure X X
SoC Hardware Floor plan X
SoC Hardware Place- and- Route Data X
SoC Hardware Layout Data X X X X X
Functional Verification Test Bench X X X
Functional Verification Property X
Functional Verification Assertion X
Functional Verification Functional Coverage X
Functional Verification Transactor X
Functional Verification Test Pattern X X X
Functional Verification Random Verification X
Intermediate Data between EDA tools Logic & Circuit Simulation Results
Intermediate Data between EDA tools Parasitic Wire Capacitance X X X X
Intermediate Data between EDA tools Parasitic Wire Resistance X X X
Intermediate Data between EDA tools Wire End Point Coordination X X
Intermediate Data between EDA tools LVS Netlist X
Intermediate Data between EDA tools Delay Time X X
SoC Testing Boundary Scan Circuits
SoC Testing Test Data X X
SoC Testing Core Test X X
SoC Testing On- chip scan compression structure X X

– 20 – TR 62856 © IEC:2013
VHDLーAMS
VerilogーAMS
CITI
TouchStone
SPF
DSPF
FSDB
SPICE
OASIS
GDS II
Open Access
CITI
TouchStone
FSDB
SPICE
VHDLーAMS
VerilogーAMS
VerilogーA
4.4 Mixed-signal verification and analog block design
Design Process
BVDL
Mixed- Signal Verification
3.2 Mixed- Signal Verificat ion Post- Layout Circuit Verification
3.1 Analog Block Design Layout Design
Transistor- Level Circuit Design
Analog Functional Design, Architecture Design
Design
Language
IEEE # - 076.1- 1999 - - - - -
Descript ion Object s
IEC # - - - - - -
Object Group Object s
SoC Hardware Structure X X X X
SoC Hardware Logical Behavior & Function X X X X
SoC Hardware Logical Behavior & Function - Extended for AMS X X X X
SoC Hardware Analog　Behavior & Function X X X X X
SoC Hardware Gate- Level Circuit X X X
SoC Hardware Transistor - Level Circuit X X X X X
SoC Hardware Timing Constraints
SoC Hardware Power Structure
SoC Hardware Floor plan
SoC Hardware Place- and- Route Data X
SoC Hardware Layout Data X X
Functional Verification Test Bench X X X X
Functional Verification Test Bench - Extended for AMS X X X
Functional Verification Property
Functional Verification Assertion
Functional Verification Functional Coverage
Functional Verification Transactor
Functional Verification Test Pattern X X
Functional Verification Random Verification
Intermediate Data between EDA tools Logic & Circuit Simulation Results X X
Intermediate Data between EDA tools Parasitic Wire Capacitance X X X
Intermediate Data between EDA tools Parasitic Wire Resistance X X
Intermediate Data between EDA tools Wire End Point Coordination X X
Intermediate Data between EDA tools LVS Netlist X X
Intermediate Data between EDA tools Delay Time X
Device Characteristics Device Characteristics（S- Parameter, etc ） X X X X

TR 62856 © IEC:2013 – 21 –
IPーXACT
CDL
Liberty
OASIS
GDS II
LEF
VHDL
Verilog
SystemVerilog
4.5 Characterization and IP preparation
BVDL Design Process
IP Model Preparation
4. Charact erizat ion
IP Preparat ion
Characterization
Design
Language
IEEE # 1800 1364 1076 1685
Descript ion Object s
IEC # 62530 61691ー4 62248
Object Group Object s
Library, Component- model Logic　Library Model X X X
Library, Component- model Library Model for Place- and- Route Tools X
Library, Component- model Layout Data X X
Library, Component- model Delay Calculation Model X
Library, Component- model LVS Netlist X
IP IP Metadata X
_____________
– 22 – TR 62856 © CEI:2013
SOMMAIRE
AVANT-PROPOS . 23
INTRODUCTION . 25
1 Domaine d’application . 26
2 Structure et contenu des langages BVDL . 29
2.1 Structure des langages BVDL . 29
2.2 Diagramme des processus de conception . 30
2.3 Tableau du processus de conception “Electronic system design” . 31
2.4 Tableau du processus de conception “SoC design” . 31
2.5 Tableau du processus de conception “Mixed-signal verification” and analog
block design” .
...