IEC TR 62856:2013
(Main)Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)
Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)
IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.
Documentation sur les sujets concernant l'automatisation de la conception - Langages BVDL (Bird's-eye View of Design Languages)
La CEI/TR 62856:2013 décrit des caractéristiques pour des langages de conception existants, ainsi que pour améliorer et renouveler des langages de conception qui appartiennent aux processus de conception définis du Système sur puce (SoC) allant de la conception au niveau système, de la mise en oeuvre et de la vérification SoC, de la création de bloc IP et de la conception de bloc analogique jusqu'à la préparation des données d'interface pour la fabrication. Trente-trois langages de conception sont choisis et la dernière version de chaque langage est reprise dans le présent rapport, à la date de mars 2011:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL et IP-XACT.
General Information
Standards Content (Sample)
IEC/TR 62856 ®
Edition 1.0 2013-08
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
Documentation on design automation subjects – The Bird’s-eye View of Design
Languages (BVDL)
Documentation sur les sujets concernant l'automatisation de la conception –
Langages BVDL (Bird’s-eye View of Design Languages)
IEC/TR 62856:2013
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IEC/TR 62856 ®
Edition 1.0 2013-08
TECHNICAL
REPORT
RAPPORT
TECHNIQUE
colour
inside
Documentation on design automation subjects – The Bird’s-eye View of Design
Languages (BVDL)
Documentation sur les sujets concernant l'automatisation de la conception –
Langages BVDL (Bird’s-eye View of Design Languages)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX S
ICS 25.040 ISBN 978-2-8322-1028-4
– 2 – TR 62856 © IEC:2013
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Structure and content of the Bird’s-eye View of Design Languages . 8
2.1 Structure of the Bird’s-eye View of Design Languages . 8
2.2 Chart of design processes. 9
2.3 Table of “Electronic system design” . 10
2.4 Table of “SoC design” . 10
2.5 Table of “Mixed-signal verification” and analog block design” . 11
2.6 Table of “Characterization and IP preparation” . 12
2.7 Reading the Bird’s-eye View of Design Languages . 13
2.7.1 General . 13
2.7.2 Case 1): Multiple marks in one design object . 13
2.7.3 Case 2): Multiple marks in the same design objects in the
different processes . 14
3 Use case of the Bird’s-eye View of Design Languages . 14
3.1 Case 1): Investigation of consistency of flow . 14
3.2 Case 2): Evolution of language and standardization . 15
3.3 Case 3): Emergence of new technology . 15
4 The Bird’s-eye View of Design Languages (BVDL), version 1.0 . 15
4.1 Design processes . 15
4.2 Electronic system design . 16
4.3 SoC design . 17
4.4 Mixed-signal verification and analog block design . 20
4.5 Characterization and IP preparation . 21
Figure 1 – Electronic design ecosystem . 7
Figure 2 – Chart and table of BVDL . 8
Figure 3 – Structure of the table. 9
Figure 4 – Chart of design processes . 9
Figure 5 – “Electronic system design” table . 10
Figure 6 – Part of “SoC design” table . 11
Figure 7 – Part of “Mixed-signal verification and analog block design” table . 12
Figure 8 – “Characterization and IP preparation” table . 13
Figure 9 – Multiple marks in one design object . 14
Figure 10 – Multiple marks in the same design objects in the different processes . 14
Figure 11 – Chart of design processes . 15
TR 62856 © IEC:2013 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DOCUMENTATION ON DESIGN AUTOMATION SUBJECTS –
THE BIRD’S-EYE VIEW OF DESIGN LANGUAGES (BVDL)
FOREWORD
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The main task of IEC technical committees is to prepare International Standards. However, a
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example "state of the art".
IEC 62856, which is a technical report, has been prepared by IEC technical committee 91:
Electronics assembly technology:
The text of this technical report is based on the following documents:
Enquiry draft Report on voting
91/1085/DTR 91/1101/RVC
Full information on the voting for the approval of this technical report can be found in the report
on voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until the
stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data related to
the specific publication. At this date, the publication will be
– 4 – TR 62856 © IEC:2013
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
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TR 62856 © IEC:2013 – 5 –
INTRODUCTION
The automation of design and manufacturing technologies in electronic industries has been
evolving world-wide for over three decade
...
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