IEC 62228-6:2022

Integrated circuit - EMC evaluation of transceivers - Part 6: PSI5 transceivers

IEC 62228-6:2022 specifies test and measurement methods for EMC evaluation of peripheral sensor interface 5 (PSI5) transceiver integrated circuits (ICs) under network condition. It defines test configurations, test conditions, test signals, failure criteria, test procedures, test setups and test boards. It is applicable for PSI5 satellite ICs (e.g. sensors) and ICs with embedded PSI5 transceivers (e.g. PSI5 electronic control unit IC). The document covers
the emission of RF disturbances,
the immunity against RF disturbances,
the immunity against impulses, and
the immunity against electrostatic discharges (ESD).

Circuits intégrés - Évaluation de la CEM des émetteurs-récepteurs - Partie 6: Émetteurs-récepteurs PSI5

L’IEC 62228-6:2022 spécifie les méthodes d’essai et de mesure pour l’évaluation de la compatibilité électromagnétique (CEM) des circuits intégrés (CI) émetteurs-récepteurs PSI5 (Peripheral Sensor Interface 5) placés en réseau. Elle définit les montages d’essai, les conditions d’essai, les signaux d’essai, les critères de défaillance, les modes opératoires d’essai, les montages d’essai et les cartes d’essai. Elle est applicable aux CI satellites PSI5 (par exemple capteurs) et aux CI avec émetteurs-récepteurs PSI5 intégrés (par exemple CI d’unité de commande électronique PSI5). Le présent document couvre
l’émission de perturbations radioélectriques,
l’immunité aux perturbations radioélectriques,
l’immunité aux impulsions, et
l’immunité aux décharges électrostatiques (DES).

General Information

• Status: Published
• Publication Date: 07-Nov-2022
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 9 - TC 47/SC 47A/WG 9
• Current Stage: PPUB - Publication issued
• Start Date: 02-Dec-2022
• Completion Date: 08-Nov-2022

Standards Content (Sample)

IEC 62228-6 ®
Edition 1.0 2022-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuit – EMC evaluation of transceivers –
Part 6: PSI5 transceivers
Circuits intégrés – Évaluation de la CEM des émetteurs-récepteurs –
Partie 6: Émetteurs-récepteurs PSI5

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IEC 62228-6 ®
Edition 1.0 2022-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuit – EMC evaluation of transceivers –

Part 6: PSI5 transceivers
Circuits intégrés – Évaluation de la CEM des émetteurs-récepteurs –

Partie 6: Émetteurs-récepteurs PSI5

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.200 ISBN 978-2-8322-6028-9

– 2 – IEC 62228-6:2022 © IEC 2022
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms, definitions and abbreviated terms . 8
3.1 Terms and definitions . 8
3.2 Abbreviated terms . 8
4 General . 8
5 Test and operating conditions . 11
5.1 Supply and ambient conditions. 11
5.2 Test operation modes . 11
5.3 Test configuration . 13
5.3.1 General test configuration for functional test . 13
5.3.2 General test configuration for unpowered ESD test . 14
5.3.3 Coupling ports for functional tests . 14
5.3.4 Coupling ports for unpowered ESD tests . 16
5.4 Test signals . 17
5.4.1 General . 17
5.4.2 Test signals for Asynchronous mode . 17
5.4.3 Test signal for Synchronous parallel bus mode . 20
5.5 Evaluation criteria . 21
5.5.1 General . 21
5.5.2 Evaluation criteria in functional operation modes during exposure to
disturbances . 22
5.5.3 Evaluation criteria in unpowered condition after exposure to
disturbances . 22
6 Test and measurement . 23
6.1 Emission of RF disturbances . 23
6.1.1 Test method . 23
6.1.2 Test setup . 23
6.1.3 Test procedure and parameters . 25
6.2 Immunity to RF disturbances . 25
6.2.1 Test method . 25
6.2.2 Test setup . 25
6.2.3 Test procedure and parameters . 27
6.3 Immunity to impulses . 29
6.3.1 Test method . 29
6.3.2 Test setup . 29
6.3.3 Test procedure and parameters . 30
6.4 Electrostatic discharge (ESD) . 32
6.4.1 Test method . 32
6.4.2 Test setup . 32
6.4.3 Test procedure and parameters . 34
7 Test report . 35
Annex A (normative) PSI5 test circuits . 36
A.1 General . 36
A.2 Test circuit for emission and immunity tests on a PSI5 ECU IC . 36
A.3 Test circuit for emission and immunity tests on a PSI5 satellite IC . 39

A.4 Test circuit for an unpowered ESD test on a PSI5 IC . 41
Annex B (normative) Test circuit boards. 43
B.1 Test circuit board for emission and immunity tests . 43
B.2 ESD test . 43
Annex C (informative) Examples of test limits for PSI5 transceiver in automotive
applications . 44
C.1 General . 44
C.2 Emission of RF disturbances . 44
C.3 Immunity to RF disturbances . 45
C.4 Immunity to Impulses . 48
C.5 ESD . 48
Bibliography . 49

Figure 1 – PSI5 system overview . 9
Figure 2 – Example PSI5 wiring diagram with a single sensor and equivalent model . 10
Figure 3 – PSI5-A configuration with a single sensor connection with two wires . 12
Figure 4 – PSI5-P configuration with two sensor connection . 12
Figure 5 – General test configuration for tests in functional operation modes . 13
Figure 6 – General test configuration for unpowered ESD test of an ECU IC . 14
Figure 7 – General test configuration for unpowered ESD test of a satellite IC . 14
Figure 8 – Coupling ports for transceiver emission and immunity tests . 15
Figure 9 – Coupling ports for unpowered ESD tests . 16
Figure 10 – Example drawing of the maximum deviation on an I-V characteristic . 23
Figure 11 – Test setup for measurement of RF disturbances. 24
Figure 12 – Test setup for DPI tests . 26
Figure 13 – Test setup for impulse immunity tests. 29
Figure 14 – Test setup for direct ESD tests . 33
Figure A.1 – General circuit diagram of the PSI5 test network for emission and
immunity tests on ECU IC . 38
Figure A.2 – General circuit diagram of the PSI5 test network for emission and
immunity tests on Satellite IC . 40
Figure A.3 – General circuit diagram of the PSI5 ECU IC for testing of direct ESD in
unpowered mode . 41
Figure A.4 – General circuit diagram of the PSI5 sensor IC for testing of direct ESD in
unpowered mode . 42
Figure C.1 – Example of limits for RF emission – PSI5 pins . 44
Figure C.2 – Example of limits for RF emission – Other global pins . 45
Figure C.3 – Example of limits for RF immunity for functional status class A –
IC
PSI5 pins . 46
Figure C.4 – Example of limits for RF immunity for functional status class A –
IC
Other global pins . 46
Figure C.5 – Example of limits for RF immunity for functional status class C or D –
IC IC
PSI5 pins . 47
Figure C.6 – Example of limits for RF immunity for functional status class C or D –
IC IC
Other global pins . 47

– 4 – IEC 62228-6:2022 © IEC 2022
Table 1 – PSI5 physical layer electrical characteristics . 9
Table 2 – Overview of required measurements and tests . 10
Table 3 – Supply and ambient conditions for functional operation . 11
Table 4 – Sensor sink current specification . 13
Table 5 – Definitions for component values of coupling ports for transceiver emission
and immunity tests . 15
Table 6 – Definitions of coupling ports for unpowered ESD tests . 17
Table 7 – Communication test signal TX1 for Asynchronous mode (125 kbps) . 18
Table 8 – Communication test signal TX2 for Asynchronous mode (189 kbps) . 19
Table 9 – Communication test signal TX3 for Asynchronous low-power mode . 20
Table 10 – Communication test signal TX4 for Synchronous parallel bus mode. 21
Table 11 – Communication test signal TX5 for Synchronous parallel bus mode. 21
Table 12 – Evaluation criteria for standalone and embedded PSI5 transceiver IC in

functional operation modes . 22
Table 13 – Parameters for emission measurements . 25
Table 14 – Settings of the RF measurement equipment . 25
Table 15 – Specifications for DPI tests . 27
Table 16 – Required DPI tests for functional status class A evaluation of Standard
IC
PSI5 transceiver ICs and embedded PSI5 transceiver ICs . 28
Table 17 – Required DPI tests for functional status class C or D evaluation of
IC IC
standard PSI5 transceiver ICs and ICs with embedded PSI5 transceiver . 28
Table 18 – Specifications for impulse immunity tests . 30
Table 19 – Parameters for impulse immunity test . 31
Table 20 – Required impulse immunity tests for functional status class A evaluation
IC
of standard and embedded PSI5 transceiver ICs . 31
Table 21 – Required impulse immunity tests for functional status class C or D
IC IC
evaluation of Standard PSI5 transceiver ICs and ICs with embedded PSI transceiver . 31
Table 22 – Specifications for direct ESD tests . 35
Table B.1 – Parameter ESD test circuit board . 43
Table C.1 – Example of limits for impulse immunity for functional status class
C or D . 48
IC IC
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUIT –
EMC EVALUATION OF TRANSCEIVERS –

Part 6: PSI5 transceivers
FOREWORD
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rights. IEC shall not be held responsible for identifying any or all such patent rights.
IEC 62228-6 has been prepared by subcommittee 47A: Integrated circuits, of IEC technical
committee 47: Semiconductor devices. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47A/1145/FDIS 47A/1147/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.

– 6 – IEC 62228-6:2022 © IEC 2022
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at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 62228 series, published under the general title Integrated circuit –
EMC evaluation of transceivers, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
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• reconfirmed,
• withdrawn,
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INTEGRATED CIRCUIT –
EMC EVALUATION OF TRANSCEIVERS –

Part 6: PSI5 transceivers
1 Scope
This part of IEC 62228 specifies test and measurement methods for EMC evaluation of
peripheral sensor interface 5 (PSI5) transceiver integrated circuits (ICs) under network
condition. It defines test configurations, test conditions, test signals, failure criteria, test
procedures, test setups and test boards. It is applicable for PSI5 satellite ICs (e.g. sensors) and
ICs with embedded PSI5 transceivers (e.g. PSI5 electronic control unit IC). The document
covers
• the emission of RF disturbances,
• the immunity against RF disturbances,
• the immunity against impulses, and
• the immunity against electrostatic discharges (ESD).
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 61967-1, Integrated circuits – Measurement of electromagnetic emissions – Part 1: General
conditions and definitions
IEC 61967-4, Integrated circuits – Measurement of electromagnetic emissions – Part 4:
Measurement of conducted emissions – 1 Ω / 150 Ω direct coupling method
IEC 62132-1, Integrated circuits – Measurement of electromagnetic immunity – Part 1: General
conditions and definitions
IEC 62132-4, Integrated circuits – Measurement of electromagnetic immunity 150 kHz to 1 GHz
– Part 4: Direct RF power injection method
IEC 62215-3, Integrated circuits – Measurement of impulse immunity – Part 3:
Non-synchronous transient injection method
IEC 62228-1, Integrated circuits – EMC evaluation of transceivers – Part 1: General conditions
and definitions
ISO 7637-2, Road vehicles – Electrical disturbances from conduction and coupling – Part 2:
Electrical transient conduction along supply lines only
ISO 10605, Road vehicles – Test methods for electrical disturbances from electrostatic
discharge
– 8 – IEC 62228-6:2022 © IEC 2022
3 Terms, definitions and abbreviated terms
For the purposes of this document, the terms and definitions given in IEC 61967-1, IEC 62132‑1,
IEC 62228-1, as well as the following apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
3.1 Terms and definitions
3.1.1
global pin
pin which carries a signal or power, which enters or leaves the application board without any
active component in between
3.1.2
mandatory components, pl
components needed for proper function and/or technical requirements of IC as specified by the
IC manufacturer
3.1.3
PSI5 satellite IC
PSI5 satellite or sensor transceiver with access to PSI5 signal
Note 1 to entry: A PSI5 satellite IC is a sensor device.
3.1.4
IC with embedded PSI5 transceiver
IC with integrated PSI5 transceiver cell and PSI5 protocol handler with access to PSI5 signal
Note 1 to entry: An IC with an embedded PSI5 is an ECU device.
3.2 Abbreviated terms
ASIC application specific integrated circuit
DPI direct RF power injection
DUT device under test
ECU electronic control unit
PCB printed circuit board
PSI5 peripheral sensor interface 5
TDMA time division multiple access

4 General
The intention of this document is to evaluate the EMC performance of PSI5 transceiver ICs
under application in minimal operating conditions (or in a minimal network). PSI5 transceiver
ICs are in general available in two types: PSI5 satellite IC and IC with embedded PSI5
transceiver.
PSI5 transceiver system overview is shown in Figure 1.

Key
1 electronic control unit (ECU) 6 PSI5 Sensor ICs
2 microcontroller (A) point-to-point topology
3 IC with embedded PSI5 (B) daisy-chain topology
4 digital interface (C) bus topology
5 two wire current interface (PSI5)

Figure 1 – PSI5 system overview
The sensors are connected to the ECU with two wires, using the same lines for power supply
and data transmission. The IC with embedded PSI5 (e.g. transceiver ASIC in the ECU) provides
a pre-regulated voltage to the sensors and reads in the transmitted sensor data.
The physical layer of PSI5 for EMC evaluation shall have the following characteristics, as shown
in Table 1.
Table 1 – PSI5 physical layer electrical characteristics
No. Parameter Variable Minimum Typical Maximum Unit
1 Supply voltage V , V 4 16,5 V
SSmax CEmax
2 Reverse polarity t < 80 ms –105  mA
protection (standard)
3 Reverse polarity t < 50 ms –130  mA
protection (extended)
4 Internal ECU R 9 10 Ω
E1
resistance
5 PSI5 ECU filter C 9 10 11 nF
E
a
capacitor
6 PSI5 ECU filter R 2 2,2 2,5 Ω
E2
resistor
7 PSI5 ECU filter C 9 10 11 nF
L
a
capacitor
a
Symmetrical values for C and C are proposed to have a balanced filter on PSI5.
E L
An example of the typical PSI5 network, with a single sensor and the equivalent model, is shown
in Figure 2. Most implementations will have a mandatory PSI5 ECU filter (PSI5 bus filter) used
on the ECU side as shown in Figure 2. Sensor side may also have additional filter components
as per the IC manufacturer specifications.

– 10 – IEC 62228-6:2022 © IEC 2022

Key
1 PSI5 ECU IC
2 PSI5 ECU filter (PSI5 bus filter)
3 two-wire PSI5 interface
4 PSI5 satellite IC/sensor
Figure 2 – Example PSI5 wiring diagram with a single sensor and equivalent model
The evaluation of the EMC characteristics of PSI5 transceivers shall be performed in functional
operation modes for RF emission, RF immunity and impulse immunity tests and on a single
unpowered transceiver IC for electrostatic discharge tests.
The approach of these tests is to determine the EMC performance on dedicated global pins of
the PSI5 transceiver which are considered as EMC relevant in the application. For a PSI5
satellite IC or for an embedded PSI5 transceiver IC, these pins are at least PSI+ (PSI_DATA),
PSI- (PSI_GND) and V , if available.
BAT
The test methods used for the EMC characterization are based on the international standards
for IC EMC tests and are described in Table 2.
Table 2 – Overview of required measurements and tests
Transceiver mode Required test Test method Evaluation Functional
operation mode
Asynchronous
150 Ω direct coupling
RF emission Spectrum
Synchronous
(IEC 61967-4)
parallel bus
Synchronous
a
parallel bus
DPI
RF immunity Function
Functional
(IEC 62132-4)
Asynchronous
(powered)
b
low‑power
Synchronous
Non-synchronous transient a
parallel bus
injection
Impulse immunity Function
Asynchronous
(IEC 62215-3)
b
low-power
Passive Contact discharge
ESD Damage Off
(unpowered) (ISO 10605)
a
If the PSI5 transceiver under test does not support Synchronous parallel bus mode, Asynchronous mode shall
be used.
b
The test with Asynchronous low-power mode is recommended with the motivation to evaluate the RF and
impulse immunity performance with lower power supply levels on the interface. If the PSI5 transceiver does not
support low-power mode, the test can be omitted.

The 150 Ω direct coupling, DPI and impulse immunity test methods are chosen for the evaluation
of the EMC characteristic of transceivers in functional modes. These three test methods are
based on the same approach using conductive coupling. Therefore, it is possible to use the
same test board for all tests in functional operation mode, which reduces the effort and
increases the reproducibility and comparability of test results.
The ESD test is performed on a passive transceiver IC on a separate test board.
It is recommended to perform all measurements and tests with soldered transceivers on special
test boards to ensure application like conditions and to avoid setup effects due to sockets. Test
circuits and board design requirements for emission, immunity and ESD tests are described in
Annex A and Annex B respectively.
Since PSI5 transceivers are mostly implemented with PSI5 ECU filter (PSI5 bus filter), the EMC
performance of the PSI5 transceiver is evaluated with a bus filter at the PSI+/PSI- pins. In
consequence, the frequency characteristics of these filter elements should be taken into
account for the interpretation of the test results. Annex C provides example test limits and levels
for PSI5 transceivers in automotive application.
5 Test and operating conditions
5.1 Supply and ambient conditions
For all tests and measurements under operating conditions the settings are based on systems
with 12 V power supply, which is the main application of PSI5 transceivers. If a transceiver is
designed or targeted for higher power supply voltages the test conditions and test targets shall
be adapted and documented accordingly. The defined supply and ambient conditions for
functional operation are given in Table 3.
Table 3 – Supply and ambient conditions for functional operation
Parameter Value Comment
Voltage supply V (14 ± 0,2) V (default) PSI5 ECU IC supply voltage
BAT ext
Test temperature (23 ± 5) °C
V (3,3 ± 0,1) V (transceiver Digital/analog supply voltage for embedded
DD ext
dependent) PSI5 transceiver. Does not connect to the PSI5
bus.
For RF emission measurements, the ambient noise floor shall be at least 6 dB below the applied
target limit and documented in the test report.
Unpowered ESD tests shall be carried out without any supply voltage and the requirements of
ISO 10605 climatic environmental conditions shall be applied.
5.2 Test operation modes
The PSI5 transceiver ICs shall be tested in powered functional operation modes and in
unpowered mode. Functional operation modes are Asynchronous mode (PSI5-A), Synchronous
parallel bus mode (PSI5-P) and Asynchronous low-power mode.
• Asynchronous mode (PSI5-A): point-to-point connection for unidirectional, asynchronous
data transmission between PSI5 ECU transceiver IC and a single PSI5 satellite IC (sensor).
Figure 3 illustrates an example of this topology.
• Synchronous parallel bus mode (PSI5-P): bus network connection for bidirectional
synchronous data transmission between PSI5 transceiver and one or more sensors,
according to the TDMA method. An example with two (2) sensors is shown in Figure 4.

– 12 – IEC 62228-6:2022 © IEC 2022
• Asynchronous low-power mode: mode with reduced sink current (I ) in PSI5-A mode.
Sink
Key
1 PSI5 ECU IC
2 PSI5 ECU filter (PSI5 bus filter)
3 two-wire PSI5 interface
4 PSI5 satellite IC/sensor
Figure 3 – PSI5-A configuration with a single sensor connection with two wires

Key
1 PSI5 ECU IC
2 PSI5 ECU filter (PSI5 bus filter)
3 two-wire PSI5 interface
4 PSI5 satellite IC/sensor 1
5 PSI5 satellite IC/sensor 2
Figure 4 – PSI5-P configuration with two sensor connection
Table 4 shows the sensor sink current specifications as a function of the operating mode.

Table 4 – Sensor sink current specification
Operation mode Sink current
mA
Minimum Typical Maximum
Asynchronous mode (PSI5-A) and 22 26 30
Synchronous parallel bus mode (PSI5-P)
Asynchronous low-power mode 11 13 15

5.3 Test configuration
5.3.1 General test configuration for functional test
The test configuration in general consists of PSI5 transceivers with mandatory external
components in a minimal test network, where filtered power supplies, signals, monitoring probes
and coupling ports are connected as shown in Figure 5.

Figure 5 – General test configuration for tests in functional operation modes
For evaluation of RF emission, RF immunity and impulse immunity characteristic of a PSI5
transceiver in functional operation mode, a minimal PSI5 test network, consisting of two nodes
shall be used for PSI5-A, PSI5-P and Asynchronous low-power modes. The PSI5 ECU filter
shall be implemented on the ECU node (node 1) as part of its mandatory components. The use
of a filter on the satellite node (node 2) is optional and shall be implemented only if mandated
by the IC manufacturer.
NOTE In specific cases or for analyses, a deviation from this setup can be agreed between the users of this
document and will be noted in the test report.

– 14 – IEC 62228-6:2022 © IEC 2022
5.3.2 General test configuration for unpowered ESD test
The general test configuration for unpowered ESD test of PSI5 transceiver ICs consists of a
single PSI5 ECU IC or satellite IC with mandatory external components on a test board with
discharge coupling ports as shown in Figure 6 (ECU IC) and Figure 7 (satellite IC).

Figure 6 – General test configuration for unpowered ESD test of an ECU IC

Figure 7 – General test configuration for unpowered ESD test of a satellite IC
5.3.3 Coupling ports for functional tests
The coupling ports are used to transfer disturbances to or from the test network with a defined
transfer characteristic. The schematic of the coupling ports is shown in Figure 8. The values of
the components are dependent on the test method and defined in Table 5. The tolerance of the
components should be ±1 % or less.

Key
1 coupling ports
2 coupling networks
3 pin networks, including all external mandatory components and decoupling networks for the respective pin or pins
4 RF connectors
Figure 8 – Coupling ports for transceiver emission and immunity tests
Table 5 – Definitions for component values of coupling ports
for transceiver emission and immunity tests
Port Type Purpose Component
R C R
CPx CPx CPt
R = 120 Ω C = 1,0 nF
CP1a CP1a
R = 51 Ω
EMI1 RF measurement on PSI+/-
CP1t
R = 120 Ω C = 1,0 nF
CP1b CP1b
R = 0 Ω C = 1,0 nF
CP1a CP1a
CP1 RF1 RF coupling on PSI+/- not used
R = 0 Ω C = 1,0 nF
CP1b CP1b
R = 0 Ω C = 1,0 nF
CP1a CP1a
IMP1 Impulse coupling on PSI+/- not used
R = 0 Ω C = 1,0 nF
CP1b CP1b
EMI2 RF measurement on V R = 120 Ω C = 6,8 nF R = 51 Ω
BAT CP2 CP2 CPt
RF2 RF coupling on V R = 0 Ω C = 6,8 nF
CP2 not used
BAT CP2 CP2
IMP2 Impulse coupling on V R = 0 Ω
shorted not used
BAT CP2
– 16 – IEC 62228-6:2022 © IEC 2022
The characterization of the coupling ports shall be carried out as follows.
The magnitude of insertion losses (S measurement) between the ports CP1, CP2 and the
respective transceiver signal pads on the test board shall be measured and documented in the
test report. For this characterization, the coupling port shall be configured for RF immunity test
and the PSI5 transceiver ICs shall be removed. All other components which are directly
connected to the coupling port (e.g. filter to power supply or loads) shall remain on the test
board.
5.3.4 Coupling ports for unpowered ESD tests
The coupling ports used for unpowered direct ESD tests connect the discharge points to the
PSI5 transceiver IC test circuitry. The schematic and definitions of the coupling ports are given
in Figure 9 and Table 6. Discharge point on PSI- will depend on implementation. The
applicability of the ESD test in PSI- terminal can be agreed between the users of this document
and the same can be noted in the test report.

Key
1 coupling ports
2 coupling networks
3 pin networks, including all external mandatory components for the respective pin or pins
4 discharge points
Figure 9 – Coupling ports for unpowered ESD tests

Table 6 – Definitions of coupling ports for unpowered ESD tests
Port Type Purpose Components
a
CP1a ESD1a ESD coupling on PSI+
Metal trace for galvanic connection
a
CP1b ESD1b ESD coupling on PSI- (if
Metal trace for galvanic connection
applicable)
a
CP2 ESD2 ESD coupling on V
Metal trace for galvanic connection
BAT
a
The optional resistors R , R and R with R ≥ 200 kΩ are used to avoid static pre-
1a 1b 2
charge of discharge point caused by the ESD generator. A spark over at these
resistors at high test levels shall be avoided. If a static pre-charge is prevented by
the ESD generator construction, these resistors are not needed. Alternatively, an
external resistor can be used to remove pre-charges of each discharge point
before each single test.
5.4 Test signals
5.4.1 General
Depending on the transceiver type, different test signals are defined for communication in
normal operation mode and low-power mode of the PSI5 transceiver ICs.
5.4.2 Test signals for Asynchronous mode
The communication test signals TX1 (125 kbps) and TX2 (189 kbps) shall be used for tests of
standalone PSI5 transceiver ICs and ICs with embedded PSI5 transceiver in normal mode if no
sensor data communication is applicable. The parameters of these periodical signals are
defined in Table 7 and Table 8.
For PSI5 satellite ICs (e.g. sensors), the data frame pattern may be variable depending on the
sensor data communication. For cases where TX1 or TX2 cannot be used, the acceptable data
frame shall be defined and can be agreed between the users of this document and shall be
noted in the test report.
The communication test signal TX3 for the Asynchronous low-power mode is defined in Table 9.

– 18 – IEC 62228-6:2022 © IEC 2022
Table 7 – Communication test signal TX1 for Asynchronous mode (125 kbps)
Test signal TX1
Frame format Sensor to ECU as per PSI5 specification [1]
Signal type
After switching on the power supply, the sensor starts transmitting data continuously. Each
frame consists of 13 bits.
Protocol
PSI5-A10P-ttt/1L as per PSI5 specification, where ttt is the cycle time [1]
125 kbps, T = 8,0 μs
Data-rate
BIT
T
Sensor dependent, e.g. 224 µs
ref
T
≥ 8,4 µs
Gap
Amplitude
26 mA
(I – I )
S,High S,Low
___________
Numbers in square brackets refer to the Bibliography.

Table 8 – Communication test signal TX2 for Asynchronous mode (189 kbps)
Test signal TX2
Frame format Sensor to ECU as per PSI5 specification [1]
Signal type
After switching on the power supply, the sensor starts transmitting data continuously. Each
frame consists of 13 bits.
Protocol PSI5-A10P-ttt/1H as per PSI5 specification, where ttt is the cycle time [1]
189 kbps, T = 5,3 μs
Data-rate
BIT
T
Sensor dependent, e.g. 224 µs
ref
T
≥ 5,6 µs
Gap
Amplitude
26 mA
(I – I )
S,High S,Low
– 20 – IEC 62228-6:2022 © IEC 2022
Table 9 – Communication test signal TX3 for Asynchronous low-power mode
Test signal TX3
Frame format Sensor to ECU as per PSI5 specification [1]
Signal type
After switching on the power supply, the sensor starts transmitting data continuously. Each
frame consists of 13 bits.
Protocol PSI5-A10P-ttt/1L as per PSI5 specification, wh
...