IEC 62530:2011

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

General Information

• Status: Published
• Publication Date: 18-May-2011
• ICS: 25.040.01 - Industrial automation systems in general
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 13 - TC 91/WG 13
• Current Stage: DELPUB - Deleted Publication
• Start Date: 26-Jul-2021
• Completion Date: 26-Oct-2025

Relations

• Revises: IEC 62530:2007 - Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
• Effective Date: 05-Sep-2023
• Revised: IEC 62530:2021 - SystemVerilog - Unified Hardware Design, Specification, and Verification Language
• Effective Date: 05-Sep-2023

Overview

IEC 62530:2011 (IEEE Std 1800-2009) - SystemVerilog - defines a unified hardware design, specification, and verification language. Published as a double-logo IEEE/IEC standard, it merges and updates IEEE Std 1364 (Verilog) and IEEE 1800 (SystemVerilog) LRMs, incorporates errata and enhancements, and strengthens interoperability with languages such as SystemC, VHDL, and Verilog-AMS. The standard targets modern digital design and verification flows by combining design constructs with advanced verification features.

Key technical topics and requirements

The standard covers both language semantics and verification methodology. Key topics include:

• Unified Language Reference Manual (LRM): merger of Verilog and SystemVerilog LRMs into a single authoritative specification.
• Design constructs: modules, interfaces, programs, packages, primitives, and configurations for hierarchical hardware modeling.
• Verification constructs: enhanced assertion language, checkers, event scheduling, and simulation semantics.
• Scheduling and simulation semantics: stratified event scheduler, deterministic/nondeterministic behavior, and reference simulation algorithm for consistent simulator behavior.
• Data types and aggregates: nets, variables, vectors, classes, structures, unions, packed/unpacked arrays, dynamic/associative arrays, queues, and array manipulation methods.
• Object-oriented features: classes, inheritance, methods, static members, constructors, and encapsulation for advanced testbench architecture.
• Interoperability: guidelines and mechanisms to ensure integration with Verilog-AMS, SystemC, VHDL and other co-simulation environments.
• Tooling implications: compilation/elaboration rules, name spaces, and PLI callback control points for simulator and EDA tool implementers.

Practical applications and who uses it

IEC 62530:2011 is essential for:

• Hardware designers implementing RTL using SystemVerilog modules and interfaces.
• Verification engineers building constrained-random testbenches, assertions, and coverage-driven verification environments.
• EDA tool vendors and simulator developers ensuring compliant simulation semantics, scheduling, and language support.
• SoC and IP integrators needing language interoperability (SystemC/VHDL/Verilog-AMS) for mixed-language simulation and analog/mixed-signal integration.
• Academic and training organizations teaching modern digital design and verification techniques.

Related standards

• IEEE Std 1364 (Verilog) - predecessor merged into this LRM.
• IEEE Std 1800 (SystemVerilog) - core basis of this publication.
• Verilog-AMS standards and SystemC/VHDL interoperability specifications - for mixed-signal and mixed-language integration.

By following IEC 62530:2011, teams ensure consistent SystemVerilog usage across design, verification, and EDA tooling, improving portability, interoperability, and verification quality.

Standards Content (Sample)

IEC 62530
Edition 2.0 2011-05
™
IEEE Std 1800
INTERNATIONAL
STANDARD
colour
inside
SystemVerilog –
Unified Hardware Design, Specification, and Verification Language

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IEC 62530
Edition 2.0 2011-05
™
IEEE Std 1800
INTERNATIONAL
STANDARD
colour
inside
SystemVerilog –
Unified Hardware Design, Specification, and Verification Language

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XX
ICS 25.040 ISBN 978-2-88912-450-3

- i - IEC 62530:2011(E)
IEEE Std 1800-2009
Contents
Part One:
Design and Verification Constructs
1. Overview. 2
1.1 Scope. 2
1.2 Purpose. 2
1.3 Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005. 3
1.4 Special terms. 3
1.5 Conventions used in this standard. 3
1.6 Syntactic description. 4
1.7 Use of color in this standard . 5
1.8 Contents of this standard. 5
1.9 Deprecated clauses. 8
1.10 Examples. 8
1.11 Prerequisites. 8
2. Normative references. 9
3. Design and verification building blocks . 11
3.1 General. 11
3.2 Design elements. 11
3.3 Modules. 11
3.4 Programs . 12
3.5 Interfaces. 13
3.6 Checkers. 14
3.7 Primitives . 14
3.8 Subroutines . 14
3.9 Packages. 14
3.10 Configurations. 15
3.11 Overview of hierarchy . 15
3.12 Compilation and elaboration. 16
3.13 Name spaces. 18
3.14 Simulation time units and precision. 19
4. Scheduling semantics. 23
4.1 General. 23
4.2 Execution of a hardware model and its verification environment . 23
4.3 Event simulation . 23
4.4 The stratified event scheduler . 24
4.5 The SystemVerilog simulation reference algorithm. 29
4.6 Determinism. 29
4.7 Nondeterminism. 30
4.8 Race conditions. 30
4.9 Scheduling implication of assignments . 30
4.10 The PLI callback control points. 32
5. Lexical conventions . 33
5.1 General. 33
5.2 Lexical tokens . 33
5.3 White space. 33
5.4 Comments . 33
5.5 Operators. 33
5.6 Identifiers, keywords, and system names .34
5.7 Numbers. 35
5.8 Time literals . 40
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEEE Std 1800-2009
5.9 String literals. 40
5.10 Structure literals. 42
5.11 Array literals . 43
5.12 Attributes. 43
5.13 Built-in methods . 45
6. Data types. 47
6.1 General. 47
6.2 Data types and data objects. 47
6.3 Value set. 47
6.4 Singular and aggregate types . 48
6.5 Nets and variables. 49
6.6 Net types . 50
6.7 Net declarations . 56
6.8 Variable declarations . 58
6.9 Vector declarations . 60
6.10 Implicit declarations. 61
6.11 Integer data types . 62
6.12 Real, shortreal and realtime data types . 63
6.13 Void data type. 63
6.14 Chandle data type. 63
6.15 Class. 64
6.16 String data type . 64
6.17 Event data type. 69
6.18 User-defined types . 70
6.19 Enumerations . 71
6.20 Constants. 77
6.21 Scope and lifetime. 84
6.22 Type compatibility. 86
6.23 Type operator. 89
6.24 Casting . 90
7. Aggregate data types. 97
7.1 General. 97
7.2 Structures . 97
7.3 Unions. 99
7.4 Packed and unpacked arrays . 102
7.5 Dynamic arrays . 106
7.6 Array assignments. 109
7.7 Arrays as arguments to subroutines . 110
7.8 Associative arrays . 111
7.9 Associative array methods . 114
7.10 Queues. 117
7.11 Array querying functions . 121
7.12 Array manipulation methods. 121
8. Classes. 127
8.1 General. 127
8.2 Overview. 127
8.3 Syntax . 128
8.4 Objects (class instance). 129
8.5 Object properties and object parameter data. 130
8.6 Object methods . 130
8.7 Constructors . 131
8.8 Static class properties. 132
8.9 Static methods. 133
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

- iii - IEC 62530:2011(E)
IEEE Std 1800-2009
8.10 This . 133
8.11 Assignment, renaming, and copying. 134
8.12 Inheritance and subclasses . 135
8.13 Overridden members. 136
8.14 Super . 137
8.15 Casting . 137
8.16 Chaining constructors . 138
8.17 Data hiding and encapsulation. 138
8.18 Constant class properties. 139
8.19 Virtual methods. 140
8.20 Abstract classes and pure virtual methods. 141
8.21 Polymorphism: dynamic method lookup. 141
8.22 Class scope resolution operator :: . 142
8.23 Out-of-block declarations . 144
8.24 Parameterized classes. 145
8.25 Typedef class . 148
8.26 Classes and structures . 149
8.27 Memory management . 149
9. Processes. 151
9.1 General. 151
9.2 Structured procedures . 151
9.3 Block statements . 155
9.4 Procedural timing controls. 161
9.5 Process execution threads . 170
9.6 Process control. 171
9.7 Fine-grain process control. 175
10. Assignment statements. 177
10.1 General. 177
10.2 Overview. 177
10.3 Continuous assignments . 178
10.4 Procedural assignments. 181
10.5 Variable declaration assignment (variable initialization) . 186
10.6 Procedural continuous assignments . 186
10.7 Assignment extension and truncation . 188
10.8 Assignment-like contexts. 189
10.9 Assignment patterns. 190
10.10 Unpacked array concatenation. 194
10.11 Net aliasing . 197
11. Operators and expressions . 199
11.1 General. 199
11.2 Overview. 199
11.3 Operators. 200
11.4 Operator descriptions. 204
11.5 Operands . 224
11.6 Expression bit lengths. 227
11.7 Signed expressions. 230
11.8 Expression evaluation rules . 231
11.9 Tagged union expressions and member access. 232
11.10 String literal expressions. 234
11.11 Operator overloading . 235
11.12 Minimum, typical, and maximum delay expressions . 237
11.13 Let construct. 238
12. Procedural programming statements. 245
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEEE Std 1800-2009
12.1 General. 245
12.2 Overview. 245
12.3 Syntax . 245
12.4 Conditional if–else statement. 246
12.5 Case statement . 251
12.6 Pattern matching conditional statements . 256
12.7 Loop statements . 260
12.8 Jump statements. 264
13. Tasks and functions (subroutines) . 267
13.1 General. 267
13.2 Overview. 267
13.3 Tasks . 267
13.4 Functions. 271
13.5 Subroutine calls and argument passing. 277
13.6 Import and export functions. 282
13.7 Task and function names . 282
14. Clocking blocks . 283
14.1 General. 283
14.2 Overview. 283
14.3 Clocking block declaration . 283
14.4 Input and output skews . 285
14.5 Hierarchical expressions . 286
14.6 Signals in multiple clocking blocks . 287
14.7 Clocking block scope and lifetime. 287
14.8 Multiple clocking blocks example. 287
14.9 Interfaces and clocking blocks. 288
14.10 Clocking block events. 289
14.11 Cycle delay: ## . 289
14.12 Default clocking. 290
14.13 Input sampling . 291
14.14 Global clocking. 292
14.15 Synchronous events . 293
14.16 Synchronous drives. 293
15. Interprocess synchronization and communication. 299
15.1 General. 299
15.2 Overview. 299
15.3 Semaphores. 299
15.4 Mailboxes. 301
15.5 Named events. 304
16. Assertions. 309
16.1 General. 309
16.2 Overview. 309
16.3 Immediate assertions. 309
16.4 Deferred assertions. 312
16.5 Concurrent assertions overview. 316
16.6 Boolean expressions. 318
16.7 Sequences. 320
16.8 Declaring sequences. 323
16.9 Sequence operations. 331
16.10 Local variables. 353
16.11 Calling subroutines on match of a sequence. 359
16.12 System functions. 360
16.13 Declaring properties. 360
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

- v - IEC 62530:2011(E)
IEEE Std 1800-2009
16.14 Multiclock support. 385
16.15 Concurrent assertions. 393
16.16 Disable iff resolution. 410
16.17 Clock resolution. 412
16.18 Expect statement . 417
16.19 Clocking blocks and concurrent assertions. 419
17. Checkers. 421
17.1 Overview. 421
17.2 Checker declaration . 421
17.3 Checker instantiation . 424
17.4 Context inference. 427
17.5 Checker procedures. 427
17.6 Covergroups in checkers. 428
17.7 Checker variables. 429
17.8 Functions in checkers. 435
17.9 Complex checker example. 435
18. Constrained random value generation . 437
18.1 General. 437
18.2 Overview. 437
18.3 Concepts and usage. 437
18.4 Random variables. 440
18.5 Constraint blocks . 442
18.6 Randomization methods. 457
18.7 In-line constraints—randomize() with. 459
18.8 Disabling random variables with rand_mode(). 461
18.9 Controlling constraints with constraint_mode() . 463
18.10 Dynamic constraint modification. 464
18.11 In-line random variable control . 464
18.12 Randomization of scope variables—std::randomize(). 465
18.13 Random number system functions and methods . 467
18.14 Random stability . 468
18.15 Manually seeding randomize . 471
18.16 Random weighted case—randcase . 471
18.17 Random sequence generation—randsequence. 472
19. Functional coverage. 483
19.1 General. 483
19.2 Overview. 483
19.3 Defining the coverage model: covergroup. 484
19.4 Using covergroup in classes. 486
19.5 Defining coverage points . 488
19.6 Defining cross coverage. 498
19.7 Specifying coverage options. 503
19.8 Predefined coverage methods . 507
19.9 Predefined coverage system tasks and system functions. 509
19.10 Organization of option and type_option members. 509
19.11 Coverage computation . 510
20. Utility system tasks and system functions . 515
20.1 General. 515
20.2 Simulation control system tasks . 516
20.3 Simulation time system functions. 516
20.4 Timescale system tasks. 518
20.5 Conversion functions . 521
20.6 Data query functions. 522
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEEE Std 1800-2009
20.7 Array querying functions . 524
20.8 Math functions . 526
20.9 Severity tasks . 528
20.10 Elaboration system tasks. 528
20.11 Assertion control system tasks. 530
20.12 Assertion action control system tasks. 531
20.13 Assertion system functions . 533
20.14 Coverage system functions . 534
20.15 Probabilistic distribution functions. 534
20.16 Stochastic analysis tasks and functions. 536
20.17 Programmable logic array (PLA) modeling system tasks . 538
20.18 Miscellaneous tasks and functions. 542
21. I/O system tasks and system functions . 543
21.1 General. 543
21.2 Display system tasks. 543
21.3 File input-output system tasks and system functions. 554
21.4 Loading memory array data from a file . 565
21.5 Writing memory array data to a file. 568
21.6 Command line input. 569
21.7 Value change dump (VCD) files.
...