IEC 62530:2011
(Main)SystemVerilog - Unified Hardware Design, Specification, and Verification Language
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.
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IEC 62530
Edition 2.0 2011-05
™
IEEE Std 1800
INTERNATIONAL
STANDARD
colour
inside
SystemVerilog –
Unified Hardware Design, Specification, and Verification Language
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IEC 62530
Edition 2.0 2011-05
™
IEEE Std 1800
INTERNATIONAL
STANDARD
colour
inside
SystemVerilog –
Unified Hardware Design, Specification, and Verification Language
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XX
ICS 25.040 ISBN 978-2-88912-450-3
- i - IEC 62530:2011(E)
IEEE Std 1800-2009
Contents
Part One:
Design and Verification Constructs
1. Overview. 2
1.1 Scope. 2
1.2 Purpose. 2
1.3 Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005. 3
1.4 Special terms. 3
1.5 Conventions used in this standard. 3
1.6 Syntactic description. 4
1.7 Use of color in this standard . 5
1.8 Contents of this standard. 5
1.9 Deprecated clauses. 8
1.10 Examples. 8
1.11 Prerequisites. 8
2. Normative references. 9
3. Design and verification building blocks . 11
3.1 General. 11
3.2 Design elements. 11
3.3 Modules. 11
3.4 Programs . 12
3.5 Interfaces. 13
3.6 Checkers. 14
3.7 Primitives . 14
3.8 Subroutines . 14
3.9 Packages. 14
3.10 Configurations. 15
3.11 Overview of hierarchy . 15
3.12 Compilation and elaboration. 16
3.13 Name spaces. 18
3.14 Simulation time units and precision. 19
4. Scheduling semantics. 23
4.1 General. 23
4.2 Execution of a hardware model and its verification environment . 23
4.3 Event simulation . 23
4.4 The stratified event scheduler . 24
4.5 The SystemVerilog simulation reference algorithm. 29
4.6 Determinism. 29
4.7 Nondeterminism. 30
4.8 Race conditions. 30
4.9 Scheduling implication of assignments . 30
4.10 The PLI callback control points. 32
5. Lexical conventions . 33
5.1 General. 33
5.2 Lexical tokens . 33
5.3 White space. 33
5.4 Comments . 33
5.5 Operators. 33
5.6 Identifiers, keywords, and system names .34
5.7 Numbers. 35
5.8 Time literals . 40
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
IEEE Std 1800-2009
5.9 String literals. 40
5.10 Structure literals. 42
5.11 Array literals . 43
5.12 Attributes. 43
5.13 Built-in methods . 45
6. Data types. 47
6.1 General. 47
6.2 Data types and data objects. 47
6.3 Value set. 47
6.4 Singular and aggregate types . 48
6.5 Nets and variables. 49
6.6 Net types . 50
6.7 Net declarations . 56
6.8 Variable declarations . 58
6.9 Vector declarations . 60
6.10 Implicit declarations. 61
6.11 Integer data types . 62
6.12 Real, shortreal and realtime data types . 63
6.13 Void data type. 63
6.14 Chandle data type. 63
6.15 Class. 64
6.16 String data type . 64
6.17 Event data type. 69
6.18 User-defined types . 70
6.19 Enumerations . 71
6.20 Constants. 77
6.21 Scope and lifetime. 84
6.22 Type compatibility. 86
6.23 Type operator. 89
6.24 Casting . 90
7. Ag
...
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