IEC 63011-3:2018

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC.
Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.

Circuits intégrés - Circuits intégrés tridimensionnels - Partie 3: Modèle et conditions de mesure des trous de liaison à travers le silicium

L'IEC 63011-3:2018 spécifie un modèle de référence des caractéristiques électriques des trous de liaison à travers le silicium (TSV: through-silicon via) exigées pour la conception d'une interface dans un circuit intégré tridimensionnel (3-D IC) pour transmettre et recevoir des données numériques, ainsi que les conditions de mesure de la résistance et de la capacité afin de spécifier les caractéristiques des TSV dans un circuit intégré tridimensionnel.
Les dispositifs de puissance, les dispositifs aux fréquences radioélectriques (RF) et les systèmes microélectromécaniques (MEMS) ne font pas partie du domaine d'application du présent document.

General Information

• Status: Published
• Publication Date: 27-Nov-2018
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 7 - TC 47/SC 47A/WG 7
• Current Stage: PPUB - Publication issued
• Start Date: 28-Nov-2018
• Completion Date: 30-Nov-2018

Standards Content (Sample)

IEC 63011-3 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –
Part 3: Model and measurement conditions of through-silicon via

Circuits intégrés – Circuits intégrés tridimensionnels –
Partie 3: Modèle et conditions de mesure des trous de liaison à travers le
silicium
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IEC 63011-3 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –

Part 3: Model and measurement conditions of through-silicon via

Circuits intégrés – Circuits intégrés tridimensionnels –

Partie 3: Modèle et conditions de mesure des trous de liaison à travers le

silicium
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.200 ISBN 978-2-8322-6276-4

– 2 – IEC 63011-3:2018 © IEC 2018
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms, definitions and abbreviated terms . 7
3.1 Terms and definitions . 7
3.2 Abbreviated terms . 7
4 Measurement conditions to specify TSV characteristics . 7
4.1 Supply chain and TSV circuit model . 7
4.2 Reference model of TSV electrical characteristics . 8
4.3 Measurement conditions to specify TSV electrical characteristics . 9
4.3.1 General . 9
4.3.2 Resistance measurement . 9
4.3.3 Capacitance measurement . 10
Annex A (informative) Explanatory note . 12
A.1 Purpose of establishment . 12
A.2 Reference dimension of the TSV model . 12
A.3 Other considerations for implementation . 13
A.3.1 General . 13
A.3.2 Keep out zone . 13

Figure 1 – Reference of a multi-chip interconnect system . 6
Figure 2 – 3-D IC Supply chain model . 7
Figure 3 – TSV electrical characteristic model . 8
Figure 4 – Resistance measurement method . 10
Figure 5 – Capacitance measurement method . 10
Figure 6 – Measurement conditions to specify TSV electrical characteristics when
substrate is not connected to power supply . 11
Figure A.1 – Structure of the TSV model . 13
Figure A.2 – KOZ definition . 14

Table 1 – Policy for model standardization . 9
Table A.1 – Parameters and reference values of the TSV model . 12
Table A.2 – Parameters affecting KOZ . 14

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 3: Model and measurement conditions
of through-silicon via
FOREWORD
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patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 63011-3 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47A/1057/FDIS 47A/1063/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – IEC 63011-3:2018 © IEC 2018
A list of all parts in the IEC 63011 series, under the general title Integrated circuits – Three
dimensional integrated circuits, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
INTRODUCTION
The embedded system implementation such as digital consumer and mobile devices is a
history of functional integration and power reduction for faster and smaller. At the beginning,
the embedded system was developed by various digital ASIC chips to implement required
functions. They were then integrated on one chip as a system on chip (SoC), which includes
application processor and peripheral I/F logic, such as PCIe, SATA, USB, and DDRx memory
controller. Because required performance and image resolution is growing, SoC has
embedded many functions through adopting advanced semiconductor technology.
Since advanced semiconductor technology is complicated and its development cost is higher,
the application is limited to use only for a few products. Those SoC's cost is not appropriate
for all embedded systems. Multi-chip implementation is a way to solve this issue. It
implements very large logic gate on the separated SoC and ASIC logic chips, connecting each
other. This multi-chip interconnection technique provides also implementation of
heterogeneous technology VLSI chips.
This document is focused to interconnect methodology to implement multi-chip VLSI for three-
dimensional integrated circuit. Thanks to through-silicon via (TSV) and micro bump
interconnect technology; the wire number between VLSI can be tremendously wider. It also
allows to connect chips with on-chip bus interconnection, which has several thousand signal
connections.
– 6 – IEC 63011-3:2018 © IEC 2018
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 3: Model and measurement conditions
of through-silicon via
1 Scope
This part of IEC 63011 specifies a reference model of through-silicon via (TSV) electrical
characteristics required for an interface design in three dimensional integrated circuit (3-D IC)
to transmit and receive digital data and measurement conditions for resistance and
capacitance to specify TSV characteristics in 3-D IC.
3-D IC specifications covered by this document are the following:
• application: digital consumer and mobile;
• operating voltage: 0,1 V to 5,0 V,
• operating frequency: less than 2,0 GHz.
This document does not describe the equipment for the measurement. Figure 1 describes a
typical case of multi-chip interconnect system discussed in this document.

Figure 1 – Reference of a multi-chip interconnect system
Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the
scope of this document.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
IEC 63011-1, Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology

3 Terms, definitions and abbreviated terms
3.1 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 63011-1 apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.2 Abbreviated terms
3-D IC three-dimensional integrated circuit
ASIC application specific integrated circuit
NMOS N-channel MOSFET
PMOS P-channel MOSFET
SoC system on chip
TSV through-silicon via
VLSI very large scale integration
4 Measurement conditions to specify TSV characteristics
4.1 Supply chain and TSV circuit model
3-D IC supply chain employing the TSV circuit model is shown in Figure 2. Foundry
manufacturers of logic chip and 3-D stacking provide the TSV model. The circuit model is
determined based on an actual experimental result.

Figure 2 – 3-D IC Supply chain model

– 8 – IEC 63011-3:2018 © IEC 2018
4.2 Reference model of TSV electrical characteristics
Reference model of TSV electrical characteristics shown in Figure 3 is composed of a
capacitance (C ) and a resistance (R ). C is the total capacitance and consists of capacitance
v v v
of oxide layer (C , capacitance by depletion layer (C ) and fringe capacitance (C ). C
ox) dep fr ox
and C are capacitances between the TSV and the semiconductor substrate and dependent
dep
on the voltage applied to the TSV since depletion layer exists. C is a fringe capacitance
fr
between a bump and the semiconductor substrate. The node of C is connected to the
dep
ground through the substrate. When the interval of TSV is very short, coupling model is
recommended. Table 1 shows a policy for model standardization. Circuit definition explains
the view of proposed model. The device structure is the structure which will be the requisite in
the case of using the proposed model. Measurement condition explains device structure and
operating conditions for measurement. The parameters of the TSV model are derived from
TSV and its surrounding structure. An example of a typical concept is shown in Annex A.

Figure 3 – TSV electrical characteristic model

Table 1 – Policy for model standardization
Item Subitem Policy
Circuit Parameter Resistance is defined with average value.
definition
Capacitance is defined by a waveform.
Fringe capacitance is removable
Inductance is not included because of little influence.
Model for every application No definition
Device Surrounding TSV No definition
structure
When the interval of TSV is very short, coupling model is
recommended.
Semiconductor substrate Substrate is connected to the ground.
power supply
The defined TSV circuit model is inapplicable when
substrate isn’t connected to power supply.
Semiconductor substrate P type
Measurement Structure TSV array
condition
There is difference from single TSV and array TSVs.
Frequency Frequency dependence of capacitance is measured.
Voltage Voltage dependence of capacitance is measured.

4.3 Measurement conditions to specify TSV electrical characteristics
4.3.1 General
The electrical characteristics of the TSV shall be measured with the defined conditions.
4.3.2 Resistance measurement
TSV resistance (R ), consisting of bulk resistances of LSI interconnect, TSV, bumps and their
v
contact resistances, is obtained by four point measurement. A constant current ( I) is supplied
via current supply wirings connecting to terminal 1A and terminal 1B, and the generated
voltage (V) between wirings connecting to the terminals is measured by voltmeter as shown in
Figure 4. According to Ohm’s law, a pair resistance for the first chip (R ) is defined as V/ I .
Based on the same setup, a resistance for the first chip and the second chip (R ) is obtained.
TSV resistance (R ) is defined as (R -R )/2. This method is only valid when the second chip is
v 2 1
essentially the same as the first chip. To minimize measurement error, the voltage
measurement wiring should be connected as close as possible.

– 10 – IEC 63011-3:2018 © IEC 2018

TSV resistance (R ) is defined as R = R – R /2, where R is the first chip, and R is the second chip.
v v 2 1 1 2
Figure 4 – Resistance measurement method
4.3.3 Capacitance measurement
TSV capacitance (C ) is obtained by electrical impedance measurement. Overall capacitance
v
(C ) between terminal 1A and terminal 1B is measured by an impedance meter as a function
of signal frequency ( f) and DC voltage (V ) as shown in Figure 5. This capacitance (C ) is
dc 1
composed of TSV capacitance (C ) and the parasitic capacitance (C ) caused by the
v 2
measurement wiring and experimental setup. Therefore, TSV capacitance (C ) is given by
v
C – C . Parasitic capacitance (C ) between terminal 2A and terminal 2B is obtained by
1 2 2
impedance measurement for a measurement structure having neither TSV nor bump. Using
TSV array is recommended to reduce parasitic capacitance.

TSV capacitance (C ) is given by C – C , where C is the capacitance, and C is the parasitic capacitance.
v 1 2 1 2
Figure 5 – Capacitance measurement method

As a TSV high frequency characteristic, S parameters of TSV are measured using a vector
network analyzer (VNA). Every two TSVs short-circuited on the back side form a pair of a
grand line and a signal line using four TSVs, as shown in Figure 6 a). Two ground-signals (GS)
contact microwave probes with the contact pin pitch corresponding to the TSV interval (200μm)
are used in the measurement. After calibration operation for open, short, and load using a
calibration substrate, S parameters measurement of TSV is carried out. Typical measurement
results of S , S are shown in Figure 6 b).
21 11
6a) S parameter measurement method 6b) S parameter evaluation result
Figure 6 – Measurement conditions to specify TSV electrical characteristics
when substrate is not connected to power supply

– 12 – IEC 63011-3:2018 © IEC 2018
Annex A
(informative)
Explanatory note
A.1 Purpose of establishment
The conventional multi-chip interconnect specifications were used for limited applications and
were not suitable for SoC and ASIC interconnection. The wider range of interconnect
technology realized by TSV and micro bump changes the methodology of interconnect. The
wide range of I/O enables to extract on-chip bus to outside connection, and small size of TSV
and micro bump enables low capacitance load interface. These two technology permits to use
on-chip signalling for multi-chip signal interface.
Annex A describes neither TSV and micro bump technology, nor how to implement multi-chip
modules as a level of packaging technology, nor interposer materials. Annex A only shows
them as a reference.
A.2 Reference dimension of the TSV model
The following Table A.1 shows the parameters and reference values of the TSV model. The
structure of the TSV model is illustrated in Figure A.1.
Table A.1 – Parameters and reference values of the TSV model
Parameter Reference value
C LSI interconnect Size 20 µm to 30 µm
Pre-metal dielectric Dielectric ≈ 4
Thickness ≈ 0,3 µm
C TSV Diameter 10 µm to 20 µm
Length 25 µm to 50 µm
TSV interconnect Dielectric 4,5
Thickness 0,5 µm
C Back bump Size 10 µm to 30 µm
Backside ILD Dielectric 4,5
Thickness TBD
R Front bump-LSI Contact resistance
interconnect
LSI interconnect-TSV Contact resistance
TSV Resistivity 2,0 µΩ·cm
Diameter 10 µm to 20 µm
Length 25 µm to 50 µm
TSV-Back bump Contact resistance
Front bump/Back bump Resistivity
Thickness 5 µm to 5 µm
Size 10 µm to 30 µm
LSI interconnect Resistivity
Structure
Key
C Fringe capacitance between LSI interconnect and semiconductor substrate;
C Capacitance between TSV and semiconductor substrate;
C Fringe capacitance between b
...