IEC 60749-34-1:2025

Semiconductor devices - Mechanical and climatic test methods - Part 34-1: Power cycling test for power semiconductor module

IEC 60749-34-1:2025 describes a test method that is used to determine the capability of power semiconductor modules to withstand thermal and mechanical stress resulting from cycling the power dissipation of the internal semiconductors and the internal connectors. It is based on IEC 60749-34, but is developed specifically for power semiconductor module products, including insulated-gate bipolar transistor (IGBT), metal-oxide-semiconductor field-effect transistor (MOSFET), diode and thyristor.
If there is a customer request for an individual use or an application specific guideline (for example ECPE Guideline AQG 324), details of the test method can be based on these requirements if they deviate from the content of this document.
This test caused wear-out and is considered destructive.

Dispositifs à semiconducteurs - Méthodes d’essais mécaniques et climatiques - Partie 34-1: Essai de cycles en puissance pour modules de puissance à semiconducteurs

L’IEC 60749-34-1:2025 décrit une méthode d’essai utilisée pour déterminer la capacité des modules de puissance à semiconducteurs à résister aux contraintes thermiques et mécaniques du fait du cyclage de la dissipation de puissance des semiconducteurs internes et des connecteurs internes. Elle est basée sur l’IEC 60749‑34, mais est développée spécifiquement pour les modules de puissance à semiconducteurs, y compris les transistors bipolaires à grille isolée (IGBT), les transistors à effet de champ à structure métal-oxyde-semiconducteur (MOSFET), les diodes et les thyristors.
En cas de demande d’un client pour une utilisation individuelle ou une ligne directrice spécifique à une application (par exemple la ligne directrice AQG 324 de l’ECPE), les détails de la méthode d’essai peuvent être basés sur ces exigences s’ils s’écartent du contenu du présent document.
Cet essai provoque une usure et est considéré comme destructif.

General Information

• Status: Published
• Publication Date: 19-Jun-2025
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 2 - TC 47/WG 2
• Current Stage: PPUB - Publication issued
• Start Date: 20-Jun-2025
• Completion Date: 04-Jul-2025

Overview

IEC 60749-34-1:2025 is an international standard developed by the International Electrotechnical Commission (IEC) that specifies a power cycling test method for power semiconductor modules. This standard focuses on evaluating the durability of power semiconductor devices such as Insulated-Gate Bipolar Transistors (IGBTs), Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), diodes, and thyristors under thermal and mechanical stress caused by repeated cycling of power dissipation.

The test simulates real-world operating conditions by inducing temperature fluctuations within the device through controlled power cycling, which stresses internal semiconductor dies and connectors. IEC 60749-34-1:2025 distinguishes between short-time and long-time power cycling tests-each targeting different failure mechanisms relevant to power electronics applications like motor control, robotics, and renewable energy systems.

Being a destructive test method, this standard helps manufacturers and designers evaluate the lifetime and reliability of power semiconductor modules by replicating wear-out phenomena resulting from thermal cycling.

---

Key Topics

• Test Methodology: Guidelines for applying thermal and mechanical stress through power cycling to measure the module’s endurance.
• Device Coverage: Applicable to power modules including IGBTs, MOSFETs, diodes, and thyristors.
• Thermal Stress Simulation: Includes control of virtual junction temperature (T_vj) for short-time tests and case temperature (T_c) for long-time tests.
• Failure Mechanisms: Focuses on joint deterioration between semiconductor die and wire, die attach degradation, and substrate joining layer failures.
• Test Modes:
  • Short-Time Test: Simulates quick temperature cycles found in devices with rapid acceleration and deceleration, stressing internal connections.
  • Long-Time Test: Mimics longer operational cycles, affecting base plates and insulating substrate layers.
• Data Analysis: Employs statistical methods such as Weibull regression and least squares regression to estimate power cycling capability and lifetime.
• Test Setup: Describes required test apparatus, temperature measurement protocols, and circuit configurations for various device types.
• Application-Specific Adaptations: Allows adjustment based on user requests or specific guidelines like ECPE Guideline AQG 324 if they differ from the standard.

---

Applications

IEC 60749-34-1:2025 power cycling testing is critical for industries relying heavily on power semiconductor modules and needing assurance of device reliability and longevity under operational stresses:

• Industrial Motor Drives: Ensures that semiconductor modules powering motors withstand frequent power cycling without premature failure.
• Renewable Energy Systems: Validates robustness of inverters and converters managing fluctuating power loads in solar and wind applications.
• Robotics and Automation: Confirms reliability of modules controlling robotic joints and automation equipment where rapid cycling occurs.
• Electric Vehicles: Supports design validation for power modules in EV drivetrains that experience periodic switching and power load changes.
• Power Electronics Design: Assists engineers in lifetime estimation for product development and quality certification.

Through rigorous and standardized testing, manufacturers can improve product quality, reduce unexpected downtime, and provide users with reliable power semiconductor modules for demanding environments.

---

Related Standards

• IEC 60749 Series: Covers various mechanical and climatic test methods for semiconductor devices, providing a broad framework for reliability and environmental assessments.
• IEC 60749-23: Specifies high-temperature operating life (HTOL) tests which differ from power cycling by simulating stable high temperature stress instead of temperature fluctuations.
• ECPE Guideline AQG 324: An example of a specialized guideline that may be referred to or integrated with IEC 60749-34-1 tests for application-specific requirements.
• ISO/IEC Directives: Provide foundational procedures for standard development which underpin IEC 60749-34-1 creation and maintenance.

---

IEC 60749-34-1:2025 is an essential reference for reliability engineers, semiconductor manufacturers, and product developers seeking to understand and mitigate failure modes in power semiconductor modules through standardized power cycling testing. Adopting this test method supports product certification and helps predict operation lifetime, ensuring safer and more durable power electronic systems.

Standards Content (Sample)

IEC 60749-34-1 ®
Edition 1.0 2025-06
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices - Mechanical and climatic test methods -
Part 34-1: Power cycling test for power semiconductor module

Dispositifs à semiconducteurs - Méthodes d’essais mécaniques et climatiques -
Partie 34-1: Essai de cycles en puissance pour modules de puissance à
semiconducteurs
ICS 31.080.01  ISBN 978-2-8327-0496-7

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CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Test apparatus and structure of DUT . 8
5 Procedure . 12
5.1 General . 12
5.2 Determination of T , T and R . 15
vj(min) vj(max) th(j-c)
5.2.1 General. 15
5.2.2 Real-time temperature measurement . 15
5.2.3 Temperature calculation method . 17
6 Test conditions . 17
6.1 General . 17
6.2 Power cycling test (short-time test) . 18
6.3 Power cycling test (long-time test) . 18
6.4 Test conditions and objectives . 19
6.4.1 Certification test . 19
6.4.2 Lifetime model validation test . 19
7 Measurements. 20
8 Failure criteria . 20
Annex A (informative) Estimation of the power cycling capability . 22
A.1 Simple Weibull regression method (the "mean of m method") . 22
A.1.1 General. 22
A.1.2 Improve estimation accuracy under small sample size conditions . 22
A.1.3 Lifetime estimation using the "mean of m method" . 22
A.1.4 Estimation of the power cycling capability . 23
A.2 Least square regression method . 24
Bibliography . 28

Figure 1 – Example of the basic structure of a power semiconductor module
(schematic diagram) (case type module for industrial use) . 9
Figure 2 – A basic test circuit for the power cycling test (for IGBT module) . 9
Figure 3 – A basic test circuit for power MOSFET module . 11
Figure 4 – A basic test circuit for diode module. 11
Figure 5 – A basic test circuit for thyristor module . 12
Figure 6 – A basic circuit of 6-in-1 IGBT module . 13
Figure 7 – Temperature change profile and on/off cycle of the power cycling test
(short-time) . 14
Figure 8 – Temperature change profile and on/off cycle of the power cycling test (long-
time) . 15
Figure A.1 – Lifetime estimation by the mean of m method . 23
Figure A.2 – Power cycling capability in the power cycling test (short-time) . 23
Figure A.3 – Power cycling capability in the power cycling test (long-time) . 24
Figure A.4 – Power cycling tests at a minimum of 2 ΔT conditions . 26
Figure A.5 – Curve fitting by the regression analysis and determination of the
parameter of the lifetime model . 26
Figure A.6 – Normalization of the number of cycles to one ΔT and T by the
norm norm
N = f(ΔT, T)-model . 26
f
Figure A.7 – Fit procedure for the Weibull graph for the normalized cycle numbers . 26
Figure A.8 – Deduction of the lifetime curve for the product that crosses the specified
failure rate percentage x . 27

Table 1 – Test conditions . 18
Table 2 – Failure criteria for long-time and short-time tests . 21
Table A.1 – The sample size N for power cycling tests . 22

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Semiconductor devices - Mechanical and climatic test methods -
Part 34-1: Power cycling test for power semiconductor module

FOREWORD
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
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IEC 60749-34-1 has been prepared by subcommittee IEC technical committee TC 47:
Semiconductor devices. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2902/FDIS 47/2924/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.

This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, and the
ISO/IEC Directives available at www.iec.ch/members_experts/refdocs. The main document
types developed by IEC are described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 60749 series, published under the general title Semiconductor
devices – Mechanical and climatic test methods, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
INTRODUCTION
A power semiconductor module is affected by thermal and mechanical stress due to the power
dissipation of the internal semiconductor dies and connectors. This occurs when low-voltage
operating bias for forward conduction is periodically applied and removed, causing rapid
changes in temperature. The power cycling test is intended to simulate the temperature swing
in typical power electronics applications, which is different from the stable temperatures
reached under the high temperature operating life (HTOL) test as shown in IEC 60749-23.
Exposure to the power cycling test would not induce the same failure mechanisms as exposure
to the thermal cycling test, or thermal shock test. The power cycling test is a destructive test
that will cause wear-out failure of the device under test (DUT) if it is driven above the
specification of the device.
The power cycling test is applied to general power semiconductor modules such as for example
those used for motor control, robots, and renewable energy generation. The power cycling test
has two modes: a short-time test (based on a short cycle time) that simulates rapid acceleration
and deceleration of the equipment, and a long-time test (based on a long cycle time) that
simulates repeated operation and stop of the equipment. The short-time test mainly verifies the
effect of the temperature change of virtual junction temperature (T ) and causes the
vj
deterioration of the joint between the semiconductor die and the wire, and that of the die attach
under the semiconductor die. The long-time test verifies the effect of the temperature change
of case temperature (T ) and causes the deterioration of the joining layer between the metallic
c
base plate and the insulating substrate, and the deterioration of the die attach under the
semiconductor die.
The power cycling test is performed in two cases: as a certification test for the products whose
power cycling lifetime model has already been confirmed, and as a lifetime model validation
test for the products whose lifetime model has not been confirmed. The purpose of the
certification test is to verify that the product has a longer life than the specified number of cycles.
Moreover, the purpose of the lifetime model validation test is to statistically estimate the power
cycling lifetime model from the test results and obtain the expected lifetime model of power
modules. This is essential when customers design the lifetime of their products.

1 Scope
This part of IEC 60749 describes a test method that is used to determine the capability of power
semiconductor modules to withstand thermal and mechanical stress resulting from cycling the
power dissipation of the internal semiconductors and the internal connectors. It is based on
IEC 60749-34, but is developed specifically for power semiconductor module products,
including insulated-gate bipolar transistor (IGBT), metal-oxide-semiconductor field-effect
transistor (MOSFET), diode and thyristor.
If there is a customer request for an individual use or an application specific guideline (for
example ECPE Guideline AQG 324), details of the test method can be based on these
requirements if they deviate from the content of this document.
This test causes wear-out and is considered destructive.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60191-4, Mechanical standardization of semiconductor devices – Part 4: Coding system
and classification into forms of package outlines for semiconductor device packages
IEC 60747-2:2016, Semiconductor devices – Part 2: Discrete devices – Rectifier diodes
IEC 60747-6:2016, Semiconductor devices – Part 6: Discrete devices – Thyristors
IEC 60747-8:2010, Semiconductor devices – Discrete devices – Part 8: Field-effect transistors
IEC 60747-8:2010/AMD1:2021
IEC 60747-9:2019, Semiconductor devices – Part 9: Discrete devices – Insulated-gate bipolar
transistors (IGBTs)
IEC 60749-34, Semiconductor devices – Mechanical and climatic test methods – Part 34: Power
cycling
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
NOTE Further terms and definitions pertaining to semiconductor devices can be found in the IEC 60747 series and
IEC 60749 series.
3.1
power semiconductor module
isolated or non-isolated semiconductor module with two or more semiconductor dies according
to the package outline style code "MP" specified in IEC 60191-4
Note 1 to entry: The predominantly used package body material is plastic (including epoxy) according to
IEC 60191-4 and both the frame based and resin based embodiment are possible.
3.2
device under test
DUT
device to be tested
3.3
case temperature
T
c
case surface temperature closely below the power semiconductor die under test
3.4
junction temperature excursion
ΔT
vj
difference between virtual maximum and minimum junction temperature of the DUT during one
power cycle
3.5
case temperature excursion
ΔT
c
difference between maximum and minimum case temperature during one power cycle
3.6
minimum virtual junction temperature
T
vj(min)
minimum virtual junction temperature of the DUT during one power cycle
3.7
maximum virtual junction temperature
T
vj(max)
maximum virtual junction temperature of the DUT during one power cycle
3.8
minimum case temperature
T
c(min)
minimum case surface temperature directly below the power semiconductor module under test
3.9
maximum case temperature
T
c(max)
maximum case surface temperature directly below the power semiconductor module under test
3.10
on-time
t
on
time interval during which the DUT under test is conducting load current
Note 1 to entry: t is already defined as the turn-on switching time for BJTs, FETs and IGBTs, but is defined
on
differently in this document.
3.11
off-time
t
off
time interval for cooling down
Note 1 to entry: t is already defined as the turn-off switching time for BJTs, FETs and IGBTs, but is defined
off
differently in this document.
3.12
cycle period
sum of on-time and off-time
3.13
power loss
P
power dissipation of the DUT as calculated from current waveforms and the on-state voltage
during on-time
3.14
collector-emitter saturation voltage
V
CEsat
collector-emitter voltage, under conditions of gate-emitter voltage at which the collector current
is essentially independent of the gate-emitter voltage
[SOURCE: IEC 60747-9: 2019, 3.2.5]
3.15
drain-source on-state voltage
V
DS(on)
drain-source voltage at a specified gate-source voltage, and a drain current in the range of the
linear part of the on-state drain current-voltage curve
3.16
forward voltage
V
F
voltage across the terminals of a diode which results from the flow of current in the forward
direction
[SOURCE: IEC 60747-2:2016, 3.2.1, modified – The words "of a diode" have been added.]
3.17
load current
I
L
current to which the devices are subjected to produce power loss
4 Test apparatus and structure of DUT
The power cycling test system is constructed with a constant current power supply for supplying
a load current to the DUT, a switch circuit for turning the load current on and off, and a device
for cooling the DUT. The switch circuit controls the load current. The DUTs are cooled by an
air-cooling or water-cooling system.
Figure 1 shows an example of the structure of a typical power semiconductor module used in
industrial applications. The structure of the power semiconductor module can consist of
semiconductor dies (IGBTs, MOSFETs, diodes or thyristors) mounted on an insulating substrate.
The substrate can be soldered to a copper base plate and assembled in a case. The electrode
terminals in the case are connected to the power semiconductor dies by wires.
Figure 1 – Example of the basic structure of a power semiconductor module
(schematic diagram) (case type module for industrial use)
Alternatively, a power semiconductor module can be designed without a base plate.
Alternatively, the die connection has a structure with Al, Cu wire, and other full-scale
connections. A generic description for isolated power semiconductor devices and the applicable
characteristics can be found in IEC 60747-15.
Figure 2 exemplarily illustrates a test circuit for an IGBT module. First, a constant current power
supply and a gate voltage power supply are connected to the phase (see 5.1) to be tested in
the DUT. Next, the specified load current is supplied to the phase by controlling the constant
current power supply. Then, a switch is controlled to turn the load current I of the IGBT on and
C
off to generate a temperature change.

Key
R Gate resistor
DUT Device under test
I Current source
CC
V Voltage source
GG
I Collector current
C
Figure 2 – A basic test circuit for the power cycling test (for IGBT module)
The additional measurement circuit, which is used with the V (T) method for determining
on-state
the junction temperature T , is omitted in Figure 2, Figure 3, Figure 4 and Figure 5, as different
vj
methods to determine T are in general possible. Details for the V (T) measurement circuit
vj on-state
can be found in the applicable IEC standard (see 5.2).
The bias application procedure for the short-time cycle test is as follows. First, the on/off time
and the load current of the switch circuit are adjusted to set the ΔT of the IGBT to a specified
vj
temperature difference, then the test is started. After a short run-in period for further test
adjustment, where the parameters are fixed, all control parameters (such as I , V and on/off
C GE
time in case of an IGBT module) shall be kept constant until the end of life. The end of the run-
in period is defined by the number of cycles, at which the control parameters are fixed. The
number of cycles until the end of the run-in period should be neglectable compared to the total
number of cycles during the power cycling test.
Also, the “run-in period” is the period of adjustment until the test reaches stable conditions at
the start of the test. During this period, test conditions and operating parameters are set and
adjusted to ensure stable testing.
At the start of the test, during the run-in period the test conditions (e.g., I , V , V , on/off
C GE CE
time) are first set, so that the product reaches the required ΔT in a stabilized manner at the
vj
end of the run-in period.
For those characteristics, for which failure criteria apply according to Table 2, the following
applies: the stabilized characteristics are set as "reference values" for the failure judgment. The
"reference value" is the characteristic after the run-in period and is not the value at the start of
the test (0 cycle). It differs from the rated characteristics described in the data sheet.
If the variation of the characteristics monitored during the test exceeds the failure criterion
relative to the reference value, the product is judged to be failed (as shown in Table 2).
The run-in period for fine-tuning the test conditions can be included in the total number of test
cycles, if it can be regarded as neglectable compared to the total test duration.
of the DUT is set to the specified temperature, then the
In the long-time cycle test, first the ΔT
c
test is started.
Figure 3 shows an example of a test circuit for a power MOSFET module. The test method is
the same as for the IGBT module above.
Key
R Gate resistor
DUT Device under test
I Current source
DD
V Voltage source
GG
I Drain current
D
NOTE For MOSFET, heating in forward mode according to Figure 3 is the preferred circuitry. If the body diode is
used for heating, the circuitry is described in Figure 4.
Figure 3 – A basic test circuit for power MOSFET module
Figure 4 shows an example of a test circuit for a diode module. The test method is the same as
for the IGBT module above.
Key
D Diode
DUT Device under test
I Current source
FF
I Diode forward current
F
Figure 4 – A basic test circuit for diode module
Figure 5 shows an example of a test circuit for a thyristor module. The test method is the same
as for the IGBT module above. The current source can be either an AC or a DC current.
Key
T Thyristor
R Gate resistor
S Gate-biasing source
DUT Device under test
I Current source
TT
I Anode current
T
Figure 5 – A basic test circuit for thyristor module
NOTE Alternative test circuits for diode, thyristor, MOSFET and IGBT are given in IEC 60747-2, IEC 60747-6,
IEC 60747-8 and IEC 60747-9 respectively.
5 Procedure
5.1 General
Clause 5 exemplarily describes the test procedure for a 6-in-1 IGBT module, which can be
applied also to other types of devices. Figure 6 shows an example of a basic internal circuit of
the module.
First, determine the phase from the six elements that, under the same conditions, has the lowest
power cycling capability, i.e. the weakest position. This phase is determined with reference to
the structural design, the thermal simulation analysis, and the temperature when load current
is applied. The test is performed in the weakest position. Figure 6 shows an example in which
the VN phase is assumed to be in the weakest position based on the structural design. For the
power cycle test (long-time) the current can be distributed across all switches to achieve a more
homogeneous heating of the baseplate.
Key
P Positive
N Negative
U U-phase
V V-phase
W W-phase
UP UP-phase
VP VP-phase
WP WP-phase
UN UN-phase
VN VN-phase
WN WN-phase
Figure 6 – A basic circuit of 6-in-1 IGBT module
Next, set the temperature swing profile. Figure 7 shows an example of the profile of the short-
time power cycling test, and Figure 8 shows an example of the long-time power cycling test.
Control on-time t and off-time t of the switch circuit and set ΔT or ΔT to the specified
on off vj c
temperature excursion. Each continuous t and t is defined as one power cycle.
on off
Then, apply load current to the DUT repeatedly under the fixed conditions. Continue the test
until the DUT characteristics exceed the failure judgment criteria, or until the specified total
number of power cycles is reached.
Key
t On-time
on
t Off-time
off
NOTE t is the time up until the T increases from T to T , t is the time up until the T decreases from
on vj vj(min) vj(max) off vj
T to T (the times in the figure are reference values).
vj(max) vj(min)
Figure 7 – Temperature change profile and on/off cycle
of the power cycling test (short-time)
Key
t On-time
on
t Off-time
off
NOTE t is the time up until T increases from T to T , t is the time up until T decreases from T to
on c c(min) c(max) off c c(max)
T (the times in the figure are reference values).
c(min)
Figure 8 – Temperature change profile and on/off cycle
of the power cycling test (long- time)
5.2 Determination of T , T and R
vj(min) vj(max) th(j-c)
5.2.1 General
and T and R . Either one
The following is an explanation of how to determine T
vj(min) vj(max) th(j-c)
of the following two methods can be applied, which are explained in 5.2.2 and 5.2.3.
When monitoring the T , it is recommended to monitor the T of all modules, but it can be
c c
reduced to a minimum of 1 module by agreement with the customer.
5.2.2 Real-time temperature measurement
5.2.2.1 General
A suitable method to monitor the virtual junction temperature T and T in real-time
vj(min) vj(max)
during the power cycling test, is to use the on-state voltage of the device at a defined measuring
current as a temperature sensitive electrical parameter. The relevant standards for the
components explain the details of the method in the subclauses about the measurement
principle for thermal resistance R and transient thermal impedance Z (t) (6.2.2 of
th(j-x) th(j-x)
IEC 60747-2:2016, 6.4.3.1 of IEC 60747-6:2016, 6.3.20 of IEC 60747-8:2010, 6.3.16 of
IEC 60747-9:2019 and 6.2.4 of IEC 60747-15:2024 apply for diodes, thyristors, MOSFETs,
IGBTs and isolated power semiconductor devices, respectively). When testing MOSFETs, the
T shall be determined by using the body diode (as applicable), due to the device design.
vj
In the following, this method is referred to as the V (T)-method. Because this method
on-state
enables a real-time monitoring of T and T , a real-time monitoring of
vj(max) vj(min)
ΔT = T – T is also possible.
vj vj(max) vj(min)
5.2.2.2 Real-time R measurement ("in test")
th
To enable a real-time monitoring of R during the stress test, the load current (I , I , I or
th(j-c) C D F
I according to Figure 2, Figure 3, Figure 4 and Figure 5) and the respective on-state voltage
T
(V , V , V or V ) shall be measured at the end of the heating pulse at the same cycles
CEsat DS(on) F T
for which T and T are also determined. If the T , T , load current and on-
vj(max) c(max) vj(max) c(max)
state voltage are known, the R can be determined by the following equation, which is
th(j-c)
displayed as an example for IGBTs:

R T –/T V× I
( ) ( )
th(j-c) vj(max) c(max) CEsat C

where
R is the thermal resistance junction to case.
th(j-c)
I is the collector current.
C
The data do not have to be captured for every cycle, but the frequency shall be high enough to
register the failure criterion for R according to Table 2.
th(j-c)
If information on R (case to heatsink) is given, for example in datasheet, R can also
th(c-s) th(j-c)
be determined by the following method.
The load current (I , I , I or I according to Figure 2, Figure 3, Figure 4 and Figure 5) and the
C D F T
respective on-state voltage (V , V , V or V ) shall be measured at the end of the
CEsat DS(on) F T
heating pulse at the same cycles for which T and T are also determined.
vj(max) c(max)
R = (T – T ) / (V × I )
th(j-s) vj(max) s(max) CEsat C
= R (measurement) – R
R
th(j-c) th(j-s) th(c-s)
where
R is the thermal resistance junction to heatsink;
th(j-s)
T is the maximum heatsink temperature;
s(max)
R is the thermal resistance junction to heatsink.
th(c-s)
5.2.2.3 R measurement by intermediate and final readout
th
Another option to assess if the pass/fail criterion for R is met after the stress test is to
th(j-c)
measure R before and after the power cycling test. The method for the determination of
th(j-c)
R is according to the list provided in 5.2.2.1.
th(j-c)
=
Intermediate readouts for R -measurement are needed, if the number of cycles where end-of-
th
life is reached shall be determined. In this case the R shall be checked in regular intervals
th(j-c)
by dismounting the device from the power cycling test bench and measuring R for each
th(j-c)
device on separate equipment. The frequency for those intervals shall be high enough to
according to Table 2.
register the failure criterion for R
th(j-c)
If there is a customer request, follow the statement in ECPE Guideline AQG 324: For the
duration of the test, the DUT shall not be removed for R measurement. If it is not possible to
th
measure without removing the DUT from the test setup, ΔT can be used as failure criteria
vj
instead of R , in agreement with the customer.
th
5.2.3 Temperature calculation method
An alternative method for the determination of the DUT temperature is accepted, if evidence for
the correlation to the V (T)-method is given.
on-sate
The calculation of the T by means of the measured power loss P (for example
vj(max)
× I in the case of IGBTs), the device-specific R and the measured T is
P = V
CEsat c th(j-c)i c(max)
one possible option. In this case R shall be measured prior to the power cycling test under
th(j-c)
comparable cooling conditions as in the power cycling test to obtain the R for each device.
th(j-c)i
To determine T , and T , it shall be ensured that T and T are in thermal equilibrium
vj(max) vj(min) c vj
at the end of both the heating period and cooling period. T is given by the equation:
vj(max)
T = T + R × P
vj(max) c(max) th(j-c)i
where
R is the initial thermal resistance junction to case.
th(j-c)i
Under those conditions, the following correlation applies:
T = T
vj(min) c(min)
If T is calculated in the way that is described above, the R cannot be monitored real-
vj(max) th(j-c)
time as described in 5.2.2.2. For the assessment of whether the pass/fail criterion for R is
th(j-c)
met, only the method described in 5.2.2.3 can be applied.
6 Test conditions
6.1 General
Select the test conditions from Table 1 for the type of test to be conducted.
Keep the on and off times constant during the test. Test the specified number of DUTs.
Table 1 – Test conditions
Type Temperature Cycle time Cycle period Expected failure mode
of Test extremes (examples)
ΔT ΔT On time Off time
vj c
(1) Wire lift-off from the power
semiconductor die connection
Short-
a b c c c
< 10 s < 20 s 1 s to 30 s
time
(2) Solder crack under the power
semiconductor die
(1) Solder crack between the Cu base
plate and the insulating substrate
1 min to
Long-
c c
a
－
≥ 1 min min 3 min
c
time
3 min
(2) Solder crack under the power
semiconductor die
a
Test DUTs under appropriate test-temperature difference conditions agreed on in advance.
b
It is recommended to set the fluctuation of ΔT of the DUT as low as possible.
c
c
On and off times and cycle periods are examples only. The set values can be selected according to the heat
capacity of the DUT.
6.2 Power cycling test (short-time test)
In the short-time cycle test, set ΔT of the IGBT to the specified temperature difference.
vj
If T can be set within the rated current range at V according to the specified conditions,
vj(max) GE
adjust the load current to achieve the specified T and ΔT . However, if T does not
vj(max) vj vj(max)
reach the specified value within the rated current range, lower the V from the specified value
GE
in order to increase the V to achieve the specified T and ΔT .
CE vj(max) vj
Set the load current I to greater than 80 % of the rated current of the device under operation
L
for at least one test conditions of the certification test or the lifetime model validation test (for
IGBT under saturation operation conditions, for MOSFETs under linear region conditions of the
V = f(I ) characteristic respectively). T , I (IGBT) or I (MOSFET) or I (diode) or I
DS(on) D vj C D F T
(thyristor) and V (IGBT) or V (MOSFET) should be tested within the product’s rating. It is
GE GS
recommended to set the fluctuation of ΔT of the DUT as low as possible.
c
If I > = 80 % of the rated current is not reached in the power cycling test, the load current I ,
L L
which was applied in the test, shall be specified in the applicable documentation of the product
qualification.
The same procedure applies for MOSFETs, diodes and thyristors with the exception that the
increase of forward voltage by means of a reduction of V cannot be realized for diodes.
GE
For certification testing, T should represent the specified maximum junction temperature
vj(max)
of the device.
6.3 Power cycling test (long-time test)
In the long-time cycle test, set the ΔT of the DUT to the specified temperature difference. T
c c(max)
and ΔT are set in the same way as T and ΔT in the short-time test.
c vj(max) vj
Set the T , I (IGBT) or I (MOSFET) or I (diode) or I (thyristor) and V (IGBT) or V
vj C D F T GE GS
(MOSFET) within the ratings as well.
For certification testing, T should represent the specified maximum case temperature of
c(max)
the device.
For long-time power cycling tests, it is recommended to test using T However, in the end,
c(max).
the test will be performed under the temperature conditions that have been agreed upon with
the customer or those listed in the applicable specification.
6.4 Test conditions and objectives
6.4.1 Certification test
Test using the specified number of DUTs under the appropriate test-temperature difference
conditions (ΔT or ΔT ) agreed in advance.
vj c
This test is applied to products whose power cycling lifetime model has already been
established.
If the products pass the cycle number that is required by the lifetime model at one test conditions
(ΔT or ΔT ), the certification test is passed. Its assessment is also based on the failure rate
vj c
calculated in the Weibull evaluation.
6.4.2 Lifetime model validation test
6.4.2.1 General
Test using the specified number of DUTs under the appropriate pre-agreed test-temperature
difference conditions (ΔT or ΔT ).
vj c
The lifetime model for the product is derived from the test results (exception see 6.4.2.4). The
methods for deriving the lifetime model include the simple Weibull regression method and the
least square regression method (see Annex A for details).
6.4.2.2 Power cycling test using the simple Weibull regression method
Set at least three conditions of ΔT or ΔT , and test at least five DUTs for all temperature
vj c
difference conditions (minimum 3 conditions × 5 DUTs). Next, the lifetime model is deduced by
the simple Weibull regression method using a minimum of 15 test data (see Clause A.1 for the
lifetime model deduction method).
6.4.2.3 Power cycling test using the least square regression method
Set at least two conditions for ΔT and test with at least five DUTs for all temperature difference
vj
conditions (minimum 2 conditions × 5 DUTs). Then, using a minimum of 10 test data, estimate
the lifetime model using the least square regression method (see Clause A.2 for the lifetime
model deduction method).
6.4.2.4 Lifetime model deduction and lifetime model validation of long-time power
cycling test
In the long-time power cycling test, it is possible to classify products into newly structured
products and products based on an existing structure, and to estimate and verify the lifetime
model by the following methods.
1) Newly structured products (with new designs, new materials and new processes)
Data is taken from the evaluation of simulation usin
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