IEC 61189-5-502:2021

Test methods for electrical materials, printed board and other interconnection structures and assemblies - Part 5-502: General test methods for materials and assemblies - Surface Insulation Resistance (SIR) testing of assemblies

IEC 61189-5-502:2021 is used for evaluating the changes to the surface insulation resistance of a pre-selected material set on a representative test coupon and quantifies the deleterious effects of improperly used materials and processes that can lead to decreases in electrical resistance.

Méthodes d’essai pour les matériaux électriques, les cartes imprimées et autres structures d’interconnexion et ensembles - Partie 5-502: Méthodes d'essai générales pour les matériaux et les ensembles - Essais de résistance d'isolement en surface (RIS) des ensembles

L’IEC 61189-5-502:2021 permet d’évaluer les variations de la résistance d’isolement en surface d’un ensemble de matériaux présélectionné sur une éprouvette représentative et quantifie les effets délétères d’une mauvaise utilisation des matériaux et des processus qui peuvent provoquer une diminution de la résistance électrique.

General Information

• Status: Published
• Publication Date: 02-Feb-2021
• ICS: 31.180 - Printed circuits and boards
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 3 - TC 91/WG 3
• Current Stage: PPUB - Publication issued
• Start Date: 03-Feb-2021
• Completion Date: 15-Feb-2021

Relations

• Replaces: IEC 61189-6:2006 - Test methods for electrical materials, interconnection structures and assemblies - Part 6: Test methods for materials used in manufacturing electronic assemblies
• Effective Date: 05-Sep-2023
• Replaces: IEC 61189-5:2006 - Test methods for electrical materials, interconnection structures and assemblies - Part 5: Test methods for printed board assemblies
• Effective Date: 05-Sep-2023

Overview

IEC 61189-5-502:2021 is an international standard developed by the International Electrotechnical Commission (IEC) offering general test methods for Surface Insulation Resistance (SIR) testing of assemblies. It focuses on evaluating the changes in surface insulation resistance of materials in printed boards and other interconnection structures after exposure to certain conditions. This standard plays a critical role in detecting deleterious effects caused by improper materials or manufacturing processes that can reduce electrical resistance and compromise the performance and reliability of electronic assemblies.

The primary goal of IEC 61189-5-502:2021 is to provide a reliable, replicable testing methodology that helps manufacturers and quality assurance professionals assess and monitor the insulation characteristics of their assemblies. This is essential for ensuring long-term electrical integrity, preventing failure due to surface leakage currents and enhancing product durability.

Key Topics

• Scope of SIR Testing
  Defines the procedure for testing surface insulation resistance using representative test coupons that simulate real assembly materials and processes.

• Test Coupon Specifications
  Details requirements for coupon artwork, laminate, surface finish, solder mask, component materials, and quality. It specifies the number and identification of coupons needed for valid testing.

• Test Equipment and Apparatus
  Includes soldering tools, damp heat chambers, measurement instruments, magnifiers, cameras, cleaning solvents, interconnecting cables, connectors, and flux necessary for accurate test replication.

• Test Procedure
  Covers preparation, cleaning, manufacturing process simulation, sample conditioning in controlled environments, measurement techniques, and coupon orientation for consistent results.

• Measurement and Evaluation
  Specifies how to verify high resistance measurements, conduct hard wiring of test setups, monitor coupon data during testing, and evaluate insulation resistance values to determine pass/fail criteria.

• Reporting Requirements
  Standardizes the format and essential content for test reports, ensuring comprehensive documentation and traceability.

• Guidance and Additional Information
  Provides informative annexes offering best practices on condensation control, flux volatilization, test frequency, inspection, shielding, wiring, and test voltage considerations.

Applications

IEC 61189-5-502:2021 is widely applicable in the electronics manufacturing and quality assurance sectors, particularly:

• Printed Circuit Board (PCB) Manufacturing
  To assess the impact of materials and processes on surface insulation resistance, guiding materials selection and process control.

• Automotive, Aerospace, and Industrial Electronics
  Where high reliability under harsh environments demands thorough insulation resistance verification.

• Failure Analysis and Reliability Testing
  To diagnose insulation failures related to surface leakage and implement corrective actions.

• New Material and Process Qualification
  For qualifying solder masks, laminates, conformal coatings, and assembly processes prior to production implementation.

• Standardized Quality Control Programs
  Enabling manufacturers to maintain consistent high-quality electrical assemblies and meet international compliance requirements.

Related Standards

IEC 61189-5-502:2021 is part of the wider IEC 61189 series on test methods for electrical materials and assemblies. Related documents include:

• IEC 61189-5 (General test methods for materials and assemblies)
  Provides overarching guidelines applicable to various test types.

• IPC standards such as IPC-B-52
  Frequently referenced for test coupon design and resistor verification within SIR testing.

• ISO/IEC Directives
  For procedural consistency in standards development and implementation.

• Other IEC test method parts
  Covering environmental stress testing, solder joint reliability, and mechanical tests corresponding to electrical assembly performance.

---

Keywords: IEC 61189-5-502, Surface Insulation Resistance, SIR testing, electrical materials testing, printed board reliability, interconnection assemblies, insulation resistance measurement, solder mask testing, IPC-B-52 coupon, electrical assembly standards, IEC test methods, electrical insulation durability.

Standards Content (Sample)

IEC 61189-5-502 ®
Edition 1.0 2021-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Test methods for electrical materials, printed board and other interconnection
structures and assemblies –
Part 5-502: General test methods for materials and assemblies – Surface
Insulation Resistance (SIR) testing of assemblies

Méthodes d’essai pour les matériaux électriques, les cartes imprimées et autres
structures d’interconnexion et ensembles –
Partie 5-502: Méthodes d’essai générales pour les matériaux et les ensembles –
Essais de résistance d’isolement en surface (RIS) des ensembles

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IEC 61189-5-502 ®
Edition 1.0 2021-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Test methods for electrical materials, printed board and other interconnection

structures and assemblies –
Part 5-502: General test methods for materials and assemblies – Surface

Insulation Resistance (SIR) testing of assemblies

Méthodes d’essai pour les matériaux électriques, les cartes imprimées et autres

structures d’interconnexion et ensembles –

Partie 5-502: Méthodes d’essai générales pour les matériaux et les ensembles –

Essais de résistance d’isolement en surface (RIS) des ensembles

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180 ISBN 978-2-8322-9290-7

– 2 – IEC 61189-5-502:2021 © IEC 2021
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 7
4 Equipment/Apparatus . 7
4.1 Soldering and other production process equipment . 7
4.2 Measurement instrument . 7
4.3 Resistor verification coupon . 8
4.4 Damp heat chamber . 8
4.5 Magnifiers (10x – 30x) . 9
4.6 Camera . 9
4.7 Cleaning solvent . 9
4.8 Interconnecting cable . 9
4.9 Connector rack . 9
4.10 Solder flux . 9
5 Test coupon. 9
5.1 Test coupon artwork . 9
5.1.1 General . 9
5.1.2 Test coupon . 10
5.1.3 Laminate . 10
5.1.4 Surface finish . 10
5.1.5 Solder mask . 10
5.1.6 Quality . 10
5.2 Components (bill of materials) . 10
5.3 Number of test coupons . 12
5.4 Test conditions . 12
5.5 Coupon identification . 13
6 Procedure . 13
6.1 Test coupon preparation . 13
6.2 Cleaning . 13
6.3 Manufacturing process replication . 13
6.4 Preparation of samples for chamber . 13
6.5 Connector system – High-resistance measurement verification . 13
6.6 Hard wiring . 14
6.7 Coupon orientation in the chamber . 14
6.8 Test coupon measurements . 14
6.9 Evaluation . 15
6.10 Test report . 15
6.11 Additional information . 16
Annex A (informative) Additional information . 17
A.1 Additional information . 17
A.1.1 General . 17
A.1.2 Advisory notes . 17
A.1.3 Use of coupon test pattern on production product . 17
A.2 Use of dummy components . 17
A.3 Frequency of monitoring . 17

A.4 Condensation . 18
A.5 Flux volatilisation . 18
A.5.1 General . 18
A.5.2 90 % RH or 93 % RH . 18
A.6 Drip shield . 18
A.7 Inspection . 19
A.8 Connector test racks . 19
A.8.1 Advantages . 19
A.8.2 Disadvantages . 19
A.9 Electromagnetic shielding . 19
A.10 Wiring to the IPC B-52 test coupons . 20
A.11 Connector test rack wiring. 21
A.12 Test voltage . 21
Bibliography . 22

Figure 1 – Resistor verification coupon using the IPC-B-52 coupon . 8
Figure 2 – IPC B-52 Rev B Top Side . 11
Figure 3 – IPC B-52 Rev B bottom side . 11
Figure 4 – Test specimen location with respect to chamber air flow . 14

Table 1 – IPC B-52 bill of materials (BOM) . 12
Table A.1 – IPC B-52 Rev B wiring diagram . 20

– 4 – IEC 61189-5-502:2021 © IEC 2021
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARD AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 5-502: General test methods for materials and assemblies –
Surface Insulation Resistance (SIR) testing of assemblies

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
IEC 61189-5-502 has been prepared by IEC technical committee 91: Electronics assembly
technology. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
91/1646/CDV 91/1673/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.

This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/standardsdev/publications.
A list of all parts in the IEC 61189 series, published under the general title Test methods for
electrical materials, printed board and other interconnection structures and assemblies, can be
found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

– 6 – IEC 61189-5-502:2021 © IEC 2021
TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARD AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 5-502: General test methods for materials and assemblies –
Surface Insulation Resistance (SIR) testing of assemblies

1 Scope
This part of IEC 61189 is used for evaluating the changes to the surface insulation resistance
of a pre-selected material set on a representative test coupon and quantifies the deleterious
effects of improperly used materials and processes that can lead to decreases in electrical
resistance.
An assembly process involves a number of different process materials including solder flux,
solder paste, solder wire, underfill materials, adhesives, staking compounds, temporary
masking materials, cleaning solvents, conformal coatings and more. The test employs two
different test conditions of 85 °C and 85 % relative humidity (RH), preferred for a process that
includes cleaning, or 40 °C and 90 % relative humidity (RH), preferred for processes where no
cleaning is involved.
NOTE 40 °C and 93 % RH can be used as an alternative to 40 °C and 90 % RH. Additional information is provided
in 5.4 and A.5.2.
Testing is material (set) and process / equipment specific. Qualifications are to be performed
using the production intent equipment, processes and materials.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60068-1, Environmental testing – Part 1: General and guidance
IEC 60068-2-20, Environmental testing – Part 2-20: Tests – Test T: Test methods for
solderability and resistance to soldering heat of devices with leads
IEC 60068-2-58, Environmental testing – Part 2-58: Tests – Test Td: Test methods for
solderability, resistance to dissolution of metallization and to soldering heat of surface mounting
devices (SMD)
IEC 60068-2-67, Environmental testing – Part 2-67: Tests – Test Cy: Damp heat, steady state,
accelerated test primarily intended for components
IEC 60068-2-78, Environmental testing – Part 2-78: Tests – Test Cab: Damp heat, steady state
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
IEC 61190-1-3, Attachment materials for electronic assembly – Part 1-3: Requirements for
electronic grade solder alloys and fluxed and non-fluxed solid solder for electronic soldering
applications
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60068-1, IEC 60068-
2-20:2008, IEC 60068-2-58, IEC 60194, and IEC 61190-1-3 and the following apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
test coupon
test specimen, test vehicle, test sample
4 Equipment/Apparatus
4.1 Soldering and other production process equipment
All the equipment shall represent the equipment to be used in production.
4.2 Measurement instrument
This shall consist of a measuring device capable of measuring insulation resistance in the range
6 12
of at least 10 Ω to 10 Ω.
It shall be capable of measuring and recording each individual test pattern of an IPC-B-52 test
board/assembly. The measurement circuit shall incorporate a 1 MΩ current limiting resistor in
each current pathway.
The tolerance of the total measurement system shall be:
• ±5 % up to 10 Ω at 5 V;
10 11
• ±10 % between 10 Ω to 10 Ω at 5 V;
• ±20 % above 10 Ω at 5 V.
If a different test voltage is to be used, the measurement circuit shall be assessed at that voltage
rather than the 5 V stipulated. See 6.8 and Clause A.12 for additional information on test
voltages.
The resistors used to confirm the "total measurement system tolerance" defined above, shall
have a purchased tolerance of:
• ±0,1 % up to and including 10 Ω;
6 8
• ±1 % above 10 Ω and up to and including 10 Ω;
8 10
• ±5 % above 10 Ω and up to and including 10 Ω;
• ±10 % above 10 Ω.
The instrument can be used with either an external or internal power supply but shall be capable
of delivering a variable voltage from (5 to 100) V DC ±1 % with a 1 MΩ load and a channel to
channel isolation resistance of 10 Ω.
The system shall be capable of taking measurements in the time interval required.

– 8 – IEC 61189-5-502:2021 © IEC 2021
Equipment shall have the measurement capability to repeat the resistance measurement on all
channels at least every 20 min.
4.3 Resistor verification coupon
The measurement system measurement performance shall be verified by substituting a resistor
verification coupon (see Figure 1) in place of the test coupons while in the chamber at both
ambient and elevated conditions.
This coupon should be fitted with at least 4 “known value” resistors. The tolerances for the
“known value” resistors shall be as per the purchased tolerances detailed in 4.2.

Figure 1 – Resistor verification coupon using the IPC-B-52 coupon
The resistor verification coupon should have a protective metal (stainless steel) cover attached
with stainless hardware to the grounded mounting holes on the coupon to protect the resistors
from contamination or damage during handling operations.
Other types of test coupon may be used in place of the IPC-B-52 RVC, as this coupon is used
only to verify continuity prior to the commencement of the test.
4.4 Damp heat chamber
° ° °
A damp heat chamber capable of being adjusted to a temperature of 20 C ± 2 C to 100 C
± 2 °C and of relative humidity between 80 % RH ±3 % RH and 90 % RH ± 3 % RH according
to IEC 60068-2-67 and IEC 60068-2-78 shall be used.
If the alternative conditions of 40 °C and 93 % RH are to be used, the damp heat chamber shall
be capable of the upper humidity level of 93 % RH ± 3 % RH rather than the 90 % RH ± 3 %
RH specified above; see 5.4 and A.5.1 for further information.
The chamber shall be constructed with stainless steel inner surfaces and be well-insulated.
The temperature and humidity measurement should be taken using sensors such as dry and
wet bulb thermometers or solid-state sensors. The temperature and humidity levels of the test
chamber shall be recorded at a minimum of 5 minute intervals throughout the test, preferably with
independent control sensors.
The location of the samples within the chamber should ensure that the airflow within is not
impeded.
Adequate mixing of water vapour and air is imperative to ensure condensation does not occur
anywhere in the chamber except on/around cooling or dehumidification coils. If any part of
interior of the chamber is below the dew point, possibly due to insulation or control issues,
condensation will occur. The samples should be kept above the dew point and be shielded from
dripping or flying condensate.
Prior to every test, the chamber interior shall be wiped down with a mixture of 50 % propan-2-
ol and 50 % deionized water. The chamber shall be free from any unwanted residues from
previous tests. The chamber should have been dedicated to heat and humidity testing only and
not used for tests such as salt fog, salt mist or salt spray.
4.5 Magnifiers (10x – 30x)
To assist in post-test inspection, it is recommended that the user has a magnifier of not less
than 10x to a maximum 30x magnification.
4.6 Camera
It is recommended the user has a suitable camera available to photograph test coupons that
exhibit electrochemical migration or intermetallic dendritic growth.
4.7 Cleaning solvent
Removal of flux residues by a cleaning solvent should replicate the processes intended for
production hardware.
4.8 Interconnecting cable
A PTFE insulated wire or ribbon cable should be used to connect the test coupon to the
measurement system. This cable should be shielded using a suitable metallised cable mesh to
minimise the risk of tribo-electrical interference and electrical noise.
4.9 Connector rack
The connector rack should employ a connector (edge card or hard solder connection) suitable
to withstand the test environment. For edge card connection, use of gold-plated mating parts is
recommended.
4.10 Solder flux
Preferably use a fluxless solder wire. Alternatively, a flux-cored solder wire that conforms to
IEC 61190-1-3.
5 Test coupon
5.1 Test coupon artwork
5.1.1 General
The test coupon shall be the IPC-B-52 as shown in Figure 2 and Figure 3. The necessary
manufacturing data and artwork for this test coupon can be acquired from the IPC online store
under the reference: IPC-A-52-English-D.
The test board shall be prepared by the preferred board supplier, using the same processes as
those intended for the user’s end-product.

– 10 – IEC 61189-5-502:2021 © IEC 2021
5.1.2 Test coupon
The IPC B-52 printed circuit assembly consists of several components having test patterns
adjacent to, and beneath, the components. Prior to being subjected to conditioning the
components are soldered onto the board, using methodologies replicating as closely as possible
the proposed production techniques. See A.1.3 for additional information.
5.1.3 Laminate
The test coupon laminate should represent the substrate to be used in production.
5.1.4 Surface finish
The test coupon shall be finished with the same surface finish intended for the end-product.
When multiple surface finishes are used on end-products, the manufacturer shall have objective
evidence that the worst-case (from a residue standpoint) surface finish was tested.
5.1.5 Solder mask
The test coupon shall be finished with the same solder mask intended for the end-product.
5.1.6 Quality
The test coupons should be manufactured by the preferred supplier(s) to avoid compromising
the validity of the test. Bought-in coupons from an independent source should not be used as
these may feature:
• inappropriate laminate;
• indeterminant age and condition;
• indeterminate solder mask;
• inappropriate surface finish.
5.2 Components (bill of materials)
Comb patterns: the test coupon IPC B-52, as shown in Figure 2 and Figure 3, comprises the
following bill of materials (BOM) as shown in Table 1.

A list of all the components shown in Figure 2 is provided in Table 1.
Figure 2 – IPC B-52 Rev B top side

A list of all the components shown in Figure 3 is provided in Table 1.
Figure 3 – IPC B-52 Rev B bottom side
Apart from the chip resistors or capacitors, all the components used in this test shall be true
"dummy" components designed specifically for SIR testing. Scrap devices or devices with any
form of internal die shall not be used as these will compromise test results.

– 12 – IEC 61189-5-502:2021 © IEC 2021
Table 1 – IPC B-52 bill of materials (BOM)
ID Component/Pattern Qty Component Details
1 TH connector 4 × 24 pins 2 AMP part 536501-3 or equivalent.
Capacitor, 1 pF to 10 pF, 0402 Surface mount ceramic capacitor, 0402 body, 1 pF to 10 pF,
2 8
package DC 50 V , 5 % tolerance. AVX part 04025A100JAT2A or
equivalent.
3 BGA, 256 IO, 1 mm pitch, 1 Dummy component, no internal die or wires BGA, 256 I/O, full
isolated 16 x 16 array, 1,0 mm pitch, 17 mm body size.
4 SM connector IEEE 1386, 2 x 1 Molex Waldom part 71436-2164 or equivalent.
16 pins
5 Capacitor, 1 pF to 10 pF, 0805 25 Surface mount ceramic capacitor, 0805 body, 1 pF to 10pF,
package DC 100 V , 5 % tolerance. AVX part 08051A100JAT9A or
equivalent.
6 QFP160 0,65 mm pitch, 1 Dummy component, no internal die or wires, quad flat pack,
isolated 160 I/O, 28 mm square body, 0,65 mm pitch.
7 QFP80 0,5 mm pitch, isolated 1 Dummy component, no internal die or wires, quad flat pack,
80 I/O, 12mm square body, 0,5 mm pitch, 2 mm lead footprint.
8 Capacitor, 1 pF to 10 pF, 0603 15 Surface mount ceramic capacitor, 0603 body, 1 pF to 10 pF,
DC 50 V , 5 % tolerance. AVX part 0603A100JAT2A or
package
equivalent.
9 SOIC16, 1,27 mm pitch, 4 Dummy component, no internal die or wires, small outline
isolated integrated circuit, 16 I/O, 1,27 mm pitch leads, 3,8 mm body.
10 Capacitor, 1 pF to 10 pF, 1206 15 Surface mount ceramic capacitor, 1206 body, 1 pF to 10 pF,
package DC 100 V, 5 % tolerance. AVX part 12062A100JAT92 or
equivalent.
The design of this test coupon and the components listed in Table 1, are representative of those
presenting challenges for material and process compatibility as occurs in the assembly
production process. However, QFNs might represent the greatest challenge for material residue
accumulation – B-52 has a representative cross-section of component shapes used in the
industry, but users should employ their own components if they have a different form factor,
like QFN.
5.3 Number of test coupons
A minimum of 3 B-52 test coupons shall be tested for each material/process combination.
When conducting a process qualification, a sample size of 10 shall be used.
With every test, additional unprocessed coupons should be included in the test as controls.
5.4 Test conditions
All specimens shall be tested at 40 °C ± 2 °C and 90 % RH ± 3 % RH (according to
IEC 60068-2-78) or 85 °C ± 2 °C and 85 % RH ± 3 % RH (according to IEC 60068-2-67).
No-clean processes are recommended to be tested using 40 °C in a 90 % RH environment.
As an alternative to 40 °C ± 2 °C and 90 % RH ± 3 % RH, it is acceptable to use 40 °C ± 2°C
and 93 % RH ± 3 %. If 93 % RH is desired to be used instead of 90 % RH (at 40 °C), this shall
be agreed between user and supplier prior to use. Using 93 % RH could lead to different results
when compared to using 90 % RH. See A.5.1 for additional information.
Refer to Clause A.1 for general information.

5.5 Coupon identification
Test coupons should be identified using the production process. Use of marking pens should
be avoided.
6 Procedure
6.1 Test coupon preparation
The test coupon shall represent the substrate materials, assembly material set and fabrication
processes used in production. The test coupon circuitry shall provide for SIR testing as shown
in Figure 2 and Figure 3. Components of the type to be soldered in production are representative
of the hardest to clean configurations (in terms of "shadowing" of the solder joints by component
bodies and component-to-substrate spacing) as shown in Table 1 BOM. As the test pattern is
used to monitor the effect of printed board assembly processing, they shall be exposed to all
printed board assembly processes (i.e., the test pattern shall not be covered by permanent
solder mask).
6.2 Cleaning
Fluxes that require cleaning should be cleaned as per the intended production process.
Details of the cleaning procedure used on the coupons should be included in the test report.
6.3 Manufacturing process replication
The coupon manufacturing process used in this method is assumed to replicate the process
intended for production hardware. In cases where the assembly process involves multiple solder
operations (for example, surface mount reflow, wave solder, rework, hand solder, or conformal
coating if used), all these processes shall be carried out on the assembled test coupon. This
would be necessary even in cases where only one of the soldering processes is being changed
since residues from one process can interact with residues from a prior or following process. It
is the total of all these processes which would be shipped, and thus it is their total that shall be
tested and qualified. Refer to IPC 9203 and IPC 9201 for additional information.
For those coupons involving a “no-clean” process, no cleaning prior to assembly shall be carried
out.
6.4 Preparation of samples for chamber
Test patterns should be tested for electrical shorts prior to testing. Excessive solder should be
removed from the test samples using approved manufacturing rework processes.
Assembled coupons should be connected by either a connector system or by hard wiring. See
Clause A.8 for additional information.
It is recommended that the physical pre-test appearance be photographically documented, and
any physical anomalies recorded.
6.5 Connector system – High-resistance measurement verification
Prior to connecting test coupons to the measurement system, each cable assembly shall be
connected to the resistor verification coupon inside the humidity chamber at ambient conditions
and a measurement taken, see 4.3. Any cable that does not read within the tolerance value of
the total measurement system defined in 4.2 shall be reworked, replaced, or not used.

– 14 – IEC 61189-5-502:2021 © IEC 2021
6.6 Hard wiring
For each specimen, first cover the patterns to be tested with aluminium foil to protect them from
contamination during interconnect attachment soldering. Solder a PTFE-insulated wire to the
appropriate coupon tab using a soldering iron and, ideally, a fluxless solder wire according to
4.10. Use extreme care to minimise the amount of solder and flux to make each joint and do
not allow solder or flux to contaminate the test pattern. Each wire shall be properly identified
so that it can be recognised from outside of the damp heat chamber.
Inspect the coupon after the wires have been attached, checking that there is no solder bridging
or contamination between the connector tabs that could influence the SIR results of that test
coupon.
6.7 Coupon orientation in the chamber
Test coupons shall be placed in the centre of the chamber, if possible. The fixtures shall allow
the position of the coupons to be uniformly spaced (minimum of 15 mm) and parallel to air flow
with the connector (if present), as shown in Figure 4.

Figure 4 – Test specimen location with respect to chamber air flow
6.8 Test coupon measurements
Select environmental conditions a) or b), as appropriate; (refer to 5.3).
a) 40 °C with 90 % RH (according to IEC 60068-2-78);
• 40 °C with 93 % RH may be used if previously agreed between user and supplier
b) 85 °C with 85 % RH (according to IEC 60068-2-67).
Insert test coupons into the humidity chamber. Without the bias applied, stabilize the chamber
at 25 °C ± 2 °C with 50% RH ±3% RH for 2 h and take an initial SIR measurement. A review of
the initial ambient data can be used to identify shorts, and low values of SIR, possibly indicating
a compromised test sample.
Next, increase the temperature to 40 ºC ± 2 °C or 85 °C ± 2 °C, while maintaining the humidity
at 50 % RH ± 3 % RH and dwell at this temperature for 15 min. Then ramp chamber humidity
up to 90 % RH ± 3 % RH or 85 % RH ± 3 % RH. By increasing the temperature before the
humidity, it will help to prevent condensation forming on the test coupons. The total ramp-up
time from ambient to test conditions should not exceed 3 h for 85 °C / 85 % RH and 2 h for
40 °C / 90 % RH.
If the alternative conditions of 40 °C ± 2 °C and 93 % RH ± 3 % are being employed, the
chamber needs to be increased to 93 % RH ± 3 % RH rather than the 90% RH ± 3 % RH
referenced above. See 5.4 and A.5.1 for additional information.
The measurement voltage and stress voltage shall be the same value. If no voltage value has
been agreed between user and supplier, this voltage shall be 5 V.
The agreed upon voltage should then be applied and SIR measurements taken every 20 min
for the duration of the test, which shall not be less than 168 h.
Apply the stress voltage 1 h after chamber stabilisation at the test conditions. Remove the
stress voltage application and apply the appropriate test voltage and take SIR measurements
at the required frequency.
At the end of the exposure to test conditions, remove the electrical bias from all test coupons,
prior to temperature-humidity ramp-down initiation. After ramp-down, stabilize the chamber at
25 °C ± 2°C and 50 % RH ± 3 % RH for 2 h and take a final SIR measurement.
6.9 Evaluation
All specimens shall be visually inspected at between 10× to 30× magnification and the following
conditions recorded:
a) Presence of dendrites. If present, record, to ±25 %, the gap width of spacing between
bridged conductors.
b) No significant downward trend of SIR curve. No spikes going below 10 Ω. Reference shall
be one decade higher in SIR.
c) Presence of discoloration between conductors (discoloration on conductors-only is
acceptable). If present, discoloration shall be recorded as a colour image and included in
the test report.
d) Presence of water spots. If present, these conditions should be recorded as a colour image
and included in the test report.
e) Presence of subsurface metal migration. When examined with back-lighting, the presence
of subsurface metal migration is evidenced by a dark subsurface “shadow” growing from the
anode. If present, these conditions should be recorded as a colour image and included in
the test report.
f) Any reason for deleting values (scratches, condensation, solder-bridged conductors,
outlying points, etc.) shall be noted. Rejection of results for more than two test patterns for
a given condition shall require the test to be repeated.
6.10 Test report
The test report shall include, as a minimum, the following information:
a) details of any post-soldering cleaning procedures employed before coupon conditioning and
measurement;
b) individual charts or graphs showing the measured resistance in log Ω versus time for each
coupon and test pattern or box plots for the data set;
c) SIR results obtained for each pattern after
1) optional preconditioning, if applicable;
2) initial, at ambient;
3) final, at ambient.
– 16 – IEC 61189-5-502:2021 © IEC 2021
d) any unusual features noted during the test;
e) any visual observations (dendrites, water spots, metal migration);
f) details of any operation not included in this document or regarded as optional;
g) the environmental conditions used for the test, i.e., condition a) or b) above;
h) the stress and measurement voltage used, if not 5 V.
6.11 Additional information
The user is recommended to take into account the entire contents of Annex A. This provides
useful explanatory information.

Annex A
(informative)
Additional information
A.1 Additional information
A.1.1 General
This information provides guidance on which test conditions should be used and details on
specimen integrity during testing.
A.1.2 Advisory notes
The intent of this test is to show that a proposed manufacturing process or process change can
produce hardware with acceptable end-item performance.
For fluxes and other process materials that may leave undesirable residues and hence require
cleaning, the results obtained from the test will depend not only on the characteristics of the
residue but also on the effectiveness of the manufacturing/assembly cleaning operation. It
should be realised that the cleaning regime for populated boards may need to be more
aggressive than that indicated in the procedure for bare boards.
These process changes can involve a change in any one of the process steps. It can also
pertain to a change in bare-board supplier, solder mask or metallization. Test vehicle
construction will vary depending upon which of these changes is being evaluated.
A.1.3 Use of coupon test pattern on production product
A suitable test coupon may also be included in the preparation of the bare test coupon. If space
permits, a representative test pattern from the IPC-B-52 test board may also be used on a
production assembly, to allow for regular monitoring to be carried out.
A.2 Use of dummy c
...