IEC 63011-1:2018

Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology

IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.

Circuits intégrés - Circuits intégrés tridimensionnels - Partie 1 : Terminologie

L'IEC 63011-1:2018 donne des définitions relatives aux circuits intégrés multipuces constitués de puces empilées verticalement à l'aide de trous de liaison à travers le silicium ou de microbosses. Des termes et définitions relatifs à la fabrication et aux essais des circuits intégrés multipuces sont également fournis.

General Information

• Status: Published
• Publication Date: 27-Nov-2018
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: SC 47A - Integrated circuits
• Drafting Committee: WG 7 - TC 47/SC 47A/WG 7
• Current Stage: PPUB - Publication issued
• Start Date: 28-Nov-2018
• Completion Date: 14-Dec-2018

Overview

IEC 63011-1:2018 is an international standard developed by the International Electrotechnical Commission (IEC) that focuses on terminology related to three-dimensional (3D) integrated circuits (ICs). This Part 1 document provides clear definitions for key concepts associated with multichip integrated circuits, specifically those involving vertically stacked dies interconnected by through-silicon vias (TSVs) or micro bumps. It also covers terms related to the fabrication and testing of these advanced 3D multichip ICs, providing a foundational vocabulary essential for engineers, manufacturers, and researchers in semiconductor devices and 3D integration technology.

Key Topics

3D Integrated Circuits and Stacking Concepts

• 3-D Integrated Circuit (3D IC): Integration of multiple layers of active semiconductor devices stacked vertically, connected by local on-chip interconnects, facilitating compact and high-performance systems.
• 3-D Stacking: A bonding process that merges two or more dies or wafers, establishing electrical interconnections between layers.
• 3-D Bonding: Mechanical or electrical joining of multiple surfaces, such as die-to-die or wafer-to-wafer.

Multichip and Package Technologies

• Multichip Interconnect Technology: Techniques that enable vertical stacking of electronic components, such as transistors and capacitors, connected through specialized interconnect fabrics.
• System in Package (SiP): Integration of multiple dies and/or packages into a single package forming a complete system.
• Package-on-Package (PoP): A packaging method where multiple packages are stacked vertically.
• Multi-Chip Package (MCP): Packaging multiple dies either stacked vertically or placed side-by-side.

Interconnect Structures and Components

• Through-Silicon Via (TSV): Vertical interconnects passing completely through silicon wafers or dies, critical for 3D IC performance.
  • Power TSV: Specifically intended to deliver power across stacked layers.
  • Single Drop Signal TSV: Carries signals from one layer to another.
  • Multiple Drop Signal TSV: Carries signals from one layer to multiple layers.
• Micro Bumps: Tiny metal bumps on die surfaces providing electrical and physical contacts between stacked dies.
• Interposer: Electrical interface allowing connection redistribution, aiding integration by spreading or rerouting connections.

Testing and Fabrication Terms

• Die Stack: A chip composed of multiple vertically and horizontally integrated active components.
• Contacting Die Stack: A die stack where signals are transferred via physical and electrical contacts.
• Flip Chip: A die mounted face down to optimize electrical connectivity using bump connections.
• Redistribution Layer (RDL): An added metal layer on a chip to relocate input/output pads to other locations for easier integration.

Applications

IEC 63011-1:2018 terminology standard is vital for:

• Semiconductor Device Manufacturing: Defining and communicating precise terms during the design and production of 3D ICs with TSV technology.
• High-Performance Computing Systems: Facilitating stacking of processor and memory ICs to enhance data transfer rates and system performance.
• Advanced Packaging Technologies: Supporting development of new packaging methods like 3D wafer-level packaging, multi-chip packages, and PoP structures.
• Testing and Quality Assurance: Standardizing vocabulary for describing test techniques in 3D integration, essential for validation and reliability assessments.
• Research and Development: Offering a consistent terminology framework for engineers and scientists advancing 3D integration and multichip systems.

By standardizing terminology, this document improves communication across multidisciplinary teams, enabling innovation and reducing ambiguity in this rapidly evolving field.

Related Standards

For comprehensive understanding and further study, the following related IEC and ISO standards and resources are beneficial:

• IEC Electropedia: The official electronic dictionary of electrotechnical terms featuring more than 21,000 entries, including those related to integrated circuits.
• ISO/IEC Directives, Part 2: Framework for the preparation of International Standards ensuring consistency across technical documents.
• Other parts of the IEC 63011 series, which extend into fabrication, testing methodologies, and requirements for 3D integrated circuits.
• Relevant standards on semiconductor devices and electronic packaging, including those governing wafer-level packaging and chip-scale packaging technologies.

Keywords

3D integrated circuits, IEC 63011-1, through-silicon vias, TSV, micro bumps, multichip ICs, vertical stacking, semiconductor terminology, 3D bonding, package-on-package, multi-chip package, interposer, redistribution layer, flip chip, IC testing, system in package, electronics standards.

Standards Content (Sample)

IEC 63011-1 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –
Part 1: Terminology
Circuits intégrés – Circuits intégrés tridimensionnels –
Partie 1: Terminologie
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC
copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or
your local IEC member National Committee for further information.

Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduite
ni utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopie
et les microfilms, sans l'accord écrit de l'IEC ou du Comité national de l'IEC du pays du demandeur. Si vous avez des
questions sur le copyright de l'IEC ou si vous désirez obtenir des droits supplémentaires sur cette publication, utilisez
les coordonnées ci-après ou contactez le Comité national de l'IEC de votre pays de résidence.

IEC Central Office Tel.: [phone]
3, rue de Varembé [e-mail]
CH-1211 Geneva 20 www.iec.ch
Switzerland
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.

IEC Catalogue - webstore.iec.ch/catalogue Electropedia - www.electropedia.org
The stand-alone application for consulting the entire The world's leading online dictionary of electronic and
bibliographical information on IEC International Standards, electrical terms containing 21 000 terms and definitions in
Technical Specifications, Technical Reports and other English and French, with equivalent terms in 16 additional
documents. Available for PC, Mac OS, Android Tablets and languages. Also known as the International Electrotechnical
iPad. Vocabulary (IEV) online.

IEC publications search - webstore.iec.ch/advsearchform IEC Glossary - std.iec.ch/glossary
The advanced search enables to find IEC publications by a 67 000 electrotechnical terminology entries in English and
variety of criteria (reference number, text, technical French extracted from the Terms and Definitions clause of
committee,…). It also gives information on projects, replaced IEC publications issued since 2002. Some entries have been
and withdrawn publications. collected from earlier publications of IEC TC 37, 77, 86 and

CISPR.
IEC Just Published - webstore.iec.ch/justpublished

Stay up to date on all new IEC publications. Just Published IEC Customer Service Centre - webstore.iec.ch/csc
details all new publications released. Available online and If you wish to give us your feedback on this publication or
also once a month by email. need further assistance, please contact the Customer Service
Centre: [e-mail].
A propos de l'IEC
La Commission Electrotechnique Internationale (IEC) est la première organisation mondiale qui élabore et publie des
Normes internationales pour tout ce qui a trait à l'électricité, à l'électronique et aux technologies apparentées.

A propos des publications IEC
Le contenu technique des publications IEC est constamment revu. Veuillez vous assurer que vous possédez l’édition la
plus récente, un corrigendum ou amendement peut avoir été publié.

Catalogue IEC - webstore.iec.ch/catalogue Electropedia - www.electropedia.org
Application autonome pour consulter tous les renseignements
Le premier dictionnaire en ligne de termes électroniques et
bibliographiques sur les Normes internationales,
électriques. Il contient 21 000 termes et définitions en anglais
Spécifications techniques, Rapports techniques et autres
et en français, ainsi que les termes équivalents dans 16
documents de l'IEC. Disponible pour PC, Mac OS, tablettes
langues additionnelles. Egalement appelé Vocabulaire
Android et iPad.
Electrotechnique International (IEV) en ligne.

Recherche de publications IEC -
Glossaire IEC - std.iec.ch/glossary
webstore.iec.ch/advsearchform
67 000 entrées terminologiques électrotechniques, en anglais
La recherche avancée permet de trouver des publications IEC et en français, extraites des articles Termes et Définitions des
en utilisant différents critères (numéro de référence, texte, publications IEC parues depuis 2002. Plus certaines entrées
comité d’études,…). Elle donne aussi des informations sur les antérieures extraites des publications des CE 37, 77, 86 et
projets et les publications remplacées ou retirées. CISPR de l'IEC.

IEC Just Published - webstore.iec.ch/justpublished Service Clients - webstore.iec.ch/csc
Restez informé sur les nouvelles publications IEC. Just Si vous désirez nous donner des commentaires sur cette
Published détaille les nouvelles publications parues. publication ou si vous avez des questions contactez-nous:
Disponible en ligne et aussi une fois par mois par email. [e-mail].

IEC 63011-1 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –

Part 1: Terminology
Circuits intégrés – Circuits intégrés tridimensionnels –

Partie 1: Terminologie
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.200 ISBN 978-2-8322-6290-0

– 2 – IEC 63011-1:2018 © IEC 2018
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative reference . 6
3 Terms and definitions . 6
3.1 General . 6
3.2 Test method in 3D environment . 8
Bibliography . 12

Figure 1 – Examples of TSVs . 9

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 1: Terminology
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 63011-1 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47A/1060/FDIS 47A/1064/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – IEC 63011-1:2018 © IEC 2018
A list of all parts in the IEC 63011 series, published under the general title Integrated Circuits
– Three dimensional integrated circuits, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
INTRODUCTION
High performance electrical system requires a massive data exchange between processing
integrated circuit (IC) and storage IC. Stacked multiple ICs with a large number of vertical
interconnects among dies are an innovative way of providing higher data transfer rate among
dies. In addition to bumps, metal pillars, or metal pads which are traditional ways of
interconnection between dies, through-silicon vias enable to configure the integration of three
or more dies. The integration environment of multichip IC is significantly different from that of
the integration on a printed circuit board. This document describes definitions pertaining to
the multichip ICs.
– 6 – IEC 63011-1:2018 © IEC 2018
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 1: Terminology
1 Scope
This part of IEC 63011 provides definitions pertaining to multichip integrated circuits, as
vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and
definitions related to the fabrication and test of the multichip integrated circuits are also
provided.
2 Normative reference
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1 General
The general terms listed below relate to the secondary integration method in vertical direction
using integrated circuits fabricated on a horizontal surface of semiconductor.
3.1.1
interposer
electrical interface that connects one socket or connection to another
Note 1 to entry: The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection
to a different connection
3.1.2
multichip interconnect technology
technology that allows for the vertical stacking of layers of basic electronic components which
are connected using an interconnect fabric are as follows:
Note 1 to entry: "Basic electronic components” are elementary circuit devices such as transistors, diodes,
resistors, capacitors and inductors.
Note 2 to entry: A special case of multichip interconnect technology is the interposer structures that may only
contain interconnect layers, although in many cases other basic electronic components (in particular decoupling
capacitors) may be embedded into the interposer.

3.1.3
3-D bonding
process that joins two die or wafer surfaces together multiple surfaces mechanically or
electrically
EXAMPLE: Die-to-die, die-to-wafer, wafer-to-wafer
3.1.4
3-D stacking
3-D bonding operation that assumes electrical interconnects between the two devices
3.1.5
3-D packaging
3-D integration of multiple dies using wire bonding, package-on-package stacking, or
embedding in printed circuit boards
3.1.6
3-D wafer-level-packaging
3-D WLP
3-D integration using wafer level packaging technologies, performed after wafer fabrication,
which consists of flip-chip redistribution, redistribution interconnect, fan-in chip-size
packaging, and fan-out reconstructed wafer chip-scale packaging
Note 1 to entry: This note applies to the French language only.
3.1.7
redistribution layer
RDL
extra metal layer on a chip that makes the IO pads of an integrated circuit available in other
locations
Note 1 to entry: This note applies to the French language only.
3.1.8
system in package
SIP
integration of multiple dies, packages, or mixture of them as system in a package
Note 1 to entry: This note applies to the French language only.
3.1.9
3-D stacked integrated circuit
3-D approach using direct interconnects without wire bonding between integrated circuits of
multiple dies
Note 1 to entry: The 3-D stack uses a sequence of alternating front-end (devices) and back-end (interconnect)
layers.
3.1.10
3-D integrated circuit
3-D IC
3-D approach using direct stacking of active devices
Note 1 to entry: Interconnects are on the local on-chip interconnect levels. The 3-D stack is characterized by a
stack of front-end devices, combined with a common back-end interconnect stack.
Note 2 to entry: This note applies to the French language only.

– 8 – IEC 63011-1:2018 © IEC 2018
3.2 Test method in 3D environment
3.2.1
package stack
integrated circuit packaging method to combine vertically discrete logic and memory ball grid
array (BGA) packages
Note 1 to entry: Two or more packages are installed atop each other.
3.2.2
package-on-package
POP
package in which multiple packages are enclosed
Note 1 to entry: This note applies to the French language only.
3.2.3
multi-chip-package
MCP
package in which multiple dies are stacked vertically or placed side-by-side
Note 1 to entry: This note applies to the French language only.
3.2.4
die stack
chip in which two or more layers of active electronic components are integrated both vertically
and horizontally into a single circuit
3.2.5
contacting die stack
chip in which two or more layers of active electronic components are integrated and signals
between multiple layers are transferred via physical and electrical contacts
3.2.6
bump
stud of metal protruded on the surface of die to provide the physical and electrical contact
3.2.7
micro bump
small size bump to make an electrical contact between two dies
3.2.8
flip chip
die mounted with face down
3.2.9
through-silicon via
TSV
vertical interconnect access passing completely through a silicon wafer or die
Note 1 to entry: Examples of TSVs are shown in Figure 1.

Key
a power TSV;
b single drop signal TSV;
c multiple drop signal TSV;
d inter-die jumper;
e stacked inter-die jumper.
Figure 1 – Examples of TSVs
3.2.10
power TSV
TSV intended to deliver power from one layer to another layer of stacked silicon wafers or
dies
Note 1 to entry: Examples are shown in Figure 1.
3.2.11
single drop signal TSV
TSV intended to deliver electric signals from one layer to another layer of stacked silicon
wafers or dies
Note 1 to entry: An example is shown in Figure 1.
3.2.12
multiple drop signal TSV
TSV intended to deliver electric signals from one layer to multiple layers of stacked silicon
wafers or dies
Note 1 to entry: An example is shown in Figure 1.
3.2.13
inter-die jumper
TSV bridging circuits between adjacent two layers of stacked dies, that is not connected to
the output pin of the package
Note 1 to entry: An example is shown in Figure 1.

– 10 – IEC 63011-1:2018 © IEC 2018
3.2.14
single drop signal pin
TSV connecting the first die and to a pin of the package
3.2.15
multiple drop signal pin
TSV connecting delivering a signal from a pin of the package to multiple layers of dies
3.2.16
keep-out zone
KOZ
area around TSV in which it is recommended not to be occupied with active circuits because
the electrical properties are modified by the mechanical distortion by TSV
Note 1 to entry: This note applies to the French language only.
3.2.17
non-contacting die stack
chip in which two or more layers of active electronic components are integrated and signals
between the multiple layers are transferred without physical contacts
3.2.17.1
capacitive coupling
coupling between electric circuit elements, by which a voltage between the terminals of one of
them gives rise to an electric charge in another element
[SOURCE: IEC 60050-131:2002, 131-12-31]
3.2.17.2
inductive coupling
coupling between electric circuit elements, by which an electric current in one of them gives
rise to a linked flux between the terminals of another element
[SOURCE: IEC 60050-131:2002, 131-12-33]
3.2.18
cross-point
feature or device formed at the cross-section dimension of specific row and specific column
3.2.19
vertical transistor
transistor made to transport the charge in vertical direction
3.2.20
through-silicon via
vertical electrical connection passing completely through a silicon wafer or die
3.2.21
alignment key
apparatus to monitor or adjust the alignment of the overlaid dies
3.2.22
capacitive alignment
alignment method using differentiation of capacitance, where the maximum capacitance
appears when the top and bottom plates or chips perfectly overlap

3.2.23
inductive alignment
alignment method using differentiation of inductance, where the maximum capacitance
appears when the top and bottom plates or chips perfectly overlap
3.2.24
capacitance test
measurement of the capacitance incorporated with the t
...