ISO/IEC 11573:1994
(Main)Information technology — Telecommunications and information exchange between systems — Synchronization methods and technical requirements for Private Integrated Services Networks
Information technology — Telecommunications and information exchange between systems — Synchronization methods and technical requirements for Private Integrated Services Networks
Contains requirements necessary for the synchronization of PISNs. Establishes technical criteria necessary in the design of a synchronization plan for a PISN.
Technologies de l'information — Télécommunications et échange d'information entre systèmes — Méthodes de synchronisation et exigences techniques pour les réseaux privés avec intégration de services
General Information
Standards Content (Sample)
INTERNATIONAL ISO/IEC
11573
STANDARD
First edition
1994-12-15
Information technology -
Telecommunications and information
exchange between Systems -
Synchronization methods and technical
requirements for Private Integrated
Services Networks
Technologies de I’information - T6kommunications et behange
d ‘information en tre systemes - Methodes de Synchronisation et
exigences techniques pour /es r&eaux priv6s avec integration de Services
Reference number
ISO/IEC 11573:1994(E)
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ISO/IEC 11573: 1994(E)
Contents
Page
Section 1 : General
................................................
1.1 Scope
1.2 Definitions .
1.3 Abbreviations and acronyms .
1.4 Impact of Slips .
Section 2 : Technical requirements, Synchronization methods
5
2.1 Technical requirements .
2.1.1 Jitter and wander at the input . 5
5
2.1.1.1 CO and TO interfaces (144 kbits/s) .
2.1.1.2 Cl and Tl interfaces (1,544 Mbits/s) . 5
................... 6
2.1.1.3 C2 and T2 interfaces (2,048 Mbits/s)
2.1.2 Jitter and wander at the output . 6
2.1.2.1 CO and TO interfaces (144 kbits/s) . 6
................... 6
2.1.2.2 Cl and Tl interfaces (1,544 Mbits/s)
................... 7
2.1.2.3 C2 and T2 interfaces (2,048 Mbits/s)
2.1.3 Frequency deviation at the input . 7
............................................. 7
2.1.4Accuracy
7
2.1.5 Lack range .
2.1.6 Phase discontinuity of Slave clocks . 7
8
2.2 Synchronization methods for PISNs .
2.2.1 High level concepts . 8
2.2.2 Reference Glock Switching Criteria . 8
9
2.2.3 Reference Restoral .
2.2.4 Timing Reference Interfaces and Alarms . 9
2.2.5Buffers. . 9
9
2.2.6 Controls .
2.2.7 Slip Performance objectives . 9
2.2.8 Strategies . 10
Section 3 : Description of the synchronization methods
11
3.1 Plesiochronous Operation .
.......................... 11
3.2 Synchronization from one input
3.3 Automatic switch over with signalling . 12
12
3.4 Automatic switch over without signalling .
Annexes
A Choice of clock references
A.l Choice of reference from public nodes . 13
............... 14
A.2 Choice of references between private nodes
.............................. 15
A.3 Avoidance of Timing Loops
B Synchronization configuration
............. 16
B.l Master Slave configurations (synchronization)
................. 17
B.2 master-master configuration (Split timing)
0 ISO/IEC 1994
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Printed in Switzerland
ii
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ISO/IEC 11573:1994(E)
0 ISO/IEC
C Basis of strategies
18
C.lSliprate .
.......................... 18
C.2 Allocation of the controlled Slips
................................ 19
C.3 Unavailability of the links
20
........................................
C.4 Nodal solutions
............................ 21
C.5 Description of the five Options
D Synchronized Private Network Examples
22
.....................
D.l Example with a small private network
22
.......................
D.2 Example with a big private network
23
............
D.3 Example with two different public clock sources
.............................. 23
D.4 Example with a transit node
E Slave Glock Performance Measurement Guidelines
24
.............................
E.l Slave Clocks considerations
24
.......................................
E.l .l Ideal Operation
25
....................................
E. 1.2 Stressed Operation
25
...................................
E.1.3 Holdover Operation
............................ 25
E.2 Test Configuration Guidelines
...................................... 25
E.2.1 Reference Glock
26
............................
E.2.2 Digital Reference Simulation
26
.........................
E.2.3 Output Timing Signal Recovety
26
.........................................
E.3 Test categories
26
..........................................
E.3.1 Ideal Testing
26
........................................
E.3.2 Stress Testing
27
......................................
E.3.3 Holdover Testing
F Signalling for management of synchronization
28
............................................
F 1 Presentation
28
..............................
Fl .1 Configuration Parameters
28
..................................
Fl.2 Reactions of the node
................... 28
Fl .3 Reference clock switching and restoral
................................. 28
F.2 Description of the states
........................................... 28
F2.1 Initial states
29
...........................................
F.2.2 Slave states
29
.....................................
F2.3 Autonomous state
29
............................................
F2.4 Wait states
................................. 29
F.3 Description of the events
29
........................................
F.3.1 Failure of links
29
..................................
F3.2 Signalling information
29
.............................................
F3.3 Time out
29
...................
F4 SDL representation of the state machine
34
G Bibliography
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0 lSO/lEC
ISO/IEC 11573: 1994(E)
Foreword
ISO (the International Organization for Standardization) and IEC (the
International Electrotechnical Commission) form the specialized
System for worldwide standardization. National bodies that are
members of ISO or IEC participate in the development of International
Standards through technical committees established by the
respective organization to deal with particular fields of technical
activity. ISO and IEC technical committees collaborate in fields of
mutual interest. Other international organizations, governmental and
non-governmental, in liaison with ISO and IEC, also take part in the
work.
In the field of information technology, ISO and IEC have established a
lSO/IEC JTC 1.
joint technical committee, Draft International
Standards adopted by the joint technical committee are circulated to
national bodies for voting. Publication as an International Standard
requires approval by at least 75 % of the national bodies casting a
vote.
International Standard lSO/IEC 11573 was prepared by Joint Technical
Committee lSO/IEC JTC 1, Information technology, Subcommittee
SC 6, Telecommunications and information exchange between
Systems.
During the preparation of this International Standard, information was
gathered on Patents upon which application of the Standard might
depend. Relevant Patents were identified as belonging to ALCATEL
Business Systems. However, ISO and IEC cannot give authoritative or
comprehensive information about evidente, validity or scope of
patent and Iike rights. The patent-holder has stated that licences will
be granted under reasonable terms and conditions and com-
munications on this subject should be addressed to
ALCATEL Business Systems
Business Products Division
54, avenue Jean Jaures
92707 Colombes Cedex
France
Tel. : (1) 47.85.55.55
Telex: 615.531 F
Telefax: (1) 47.85.54.20
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0 ISO/IEC
ISO/IEC 11573:1994(E)
Introduction
When synchronous digital Signals are being transported over a
communications link, the receiving end must operate at the same average
frequency as the transmitting end to prevent loss of information. This is
referred to as link synchronization. When digital Signals traverse a network
of digital communications links, switching nodes, multiplexers, and
transmission interfaces, the task of keeping all the entities operating at the
same average frequency is referred to as network synchronization.
The design of a PISN requires specification of the timing sources and
receivers for the synchronization network. Proper design requires that
timing loops in the synchronization network be avoided. A timing loop
occurs when a clock is using as its reference frequency a Signal that is itself
traceable to the output of that clock. The formation of such a closed timing
loop leads to frequency instability and is not permitted. While it is relatively
straightforward to ensure against timing loops in the primary
synchronization reference network, care should be taken that timing loops
do not occur during failure or error conditions when various timing
references are rearranged.
When a PISN is not connected to the public digital network,
synchronization tan be achieved by having all PISN equipment derive
timing from a Single source.This Source should be the highest quality clock
available. Alternatively, if timing is derived from more than one class I clock,
or public clock traceable Source, the network is said to be operating
plesiochronously.
If a PISN is connected to the public network at one or more nodes, the
private network designer tan coordinate with the public network provider to
derive class I clock, or public clock traceable timing from the public digital
network. More information is available in Annex A.
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INTERNATIONAL STANDARD @ lSO/IEC ISO/IEC 11573: 1994(E)
Information technology - Telecommunications and
information exchange between Systems -
Synchronization methods and technical requirements
for Private Integrated Services Networks
Section 1 : General
1 .l Scope
This International Standard contains requirements necessaryforthesynchronization of PISNs. Timing within adigital private
network needs to becontrolled carefullyto ensure that the rateof occurrence of Slips between PINXs within the PISN,and the
public switched networks is sufficiently low not to affect unduly the Performance of voice transmissions, or the accuracy or
throughput (if errored data require re-transmission) of non-voice Services.
Requirements are also based upon the interconnection of digital private telecommunication networks via digital facilities in
the public (switched or not) telecommunication networks.
This International Standard is one of a series of technical Standards on telecommunications networks. This International
Standard with its companion Standards fills a recognized need in the telecommunications industry brought about by the
increasing use of digital equipment and facilities in private networks. lt is useful to anyone engaged in the manufacture of
digitalcustomerpremisesequipment(CPE)forprivatenetworkapplications,andtothosepurchasing,operatingorapplying
digital CPE to digital facilities for Private Integrated Services Networks (PISN).
This International Standard establishes technical criteria necessary in the design of a synchronization plan for a PISN.
Compliance with these requirements would be expected to result in a quality PISN synchronization design.
1.2 Definitions
For the purposes of this International Standard, the following definitions apply:
1.2.1 Accuracy
A measure of the maximum departure from the nominal clock rate over a 24 h period, made anytime in the lifetime of the
clock, during a defined period of time, within the declared environmental conditions. Frequency deviation may be
constrained to the specific accuracy by clock Operation in the free running or hold over modes, as defined below.
1.2.2 Asynchronous Signals
Signals having not the same nominal rate.
1.2.3 Glock free running mode
In such a mode, the PINX works with its own clock Source which is not locked to an external reference and is not using
storage techniques to maintain its accuracy.
1.2.4 Glock hold over mode
An operating condition of a clock in which it is not locked to an external reference clock, but uses storage techniques to
maintain during a limited period of time its accuracy with respects to the last known reference clock.
1.2.5 Controlled Slip
lt consists of the repetition or deletion of an integer number of octets caused by the elastic buffer mechanism used atthe
interface of a non -synchronous bit stream (a plesiochronous or asynchronous one). Slips and controlled Slips shall be
considered synonymous in this International Standard.
1.2.6 Jltter
Short-term non-cumulative variations of the significant instants of a digital Signal from their ideal positions in time.
1
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lSO/IEC 11573: 1994(E) o ISO/IEC
1.2.7 Lack range
Maximum frequency offset from the nominal, to which a given clock is able to synchronize.
1.2.8 Master
The term “master” refers to the clock Source providing the timing to the PINX.
1.2.9 Maximum time lnterval error (MTIE)
The maximum time interval error (TIE) for all possible measurement intervals within the measurement period. Figure 1
illustrates the definition of MTIE.
1.2.10 Phase Locked Loop (PLL)
A feedback-controlled System that locks a local clock to an incoming reference clock in both frequency and Phase.
1.2.11 Plesiochronous
The essential chracteristic of time-scales or Signals such as their corresponding significant instants occur at nominally the
same rate, any Variation in rate being constrained within specified limits.
1.2.12 Primary Reference Glock
Equipment that provides a timing Signal, with a long term accuracy equal or better than t 1 O-1'.
1.2.13 Pull in range
Maximum frequency offset from its own clock, to which a given clock is able to synchronize.
1.2.14 Reference Glock
Timing Signal used for synchronization, without any assumption on its accuracy.
1.2.15 Slave
The term “Slave” refers to the PINX receiving timing from another Source.
1.2.16 Slip
Refer to controlled Slip
1.2.17 Split Timing
An arrangement where equipment employsseparate transmit and receiveclockson atransmission link having no particular
relationship to one another.
1.2.18 Synchronous
Qualifies Signals with corresponding significant instants occuring at the same mean rate; the time differente betweenthese
homologous instants is generally limited.
1.2.19 Synchronization
The process of adjusting the corresponding significant instants of Signals so that a constant Phase relationship exists
between them.
1.2.20 Time-lnterval Error (TIE)
Thevariation in timedelayof agiven timing Signal with respectto an ideal timing Signal over aparticulartime period. Figure 1
illustrates the definition of TIE.
1.2.21 Timing loop
An unstable condition in which two or more equipment clocks transfer timing to each other, forming a loop without a
designated master timing Source.
1.2.22 Time to repair
The time by which, with a stated probability, the link is repaired.
1.2.23 Transparent
Alinkorgroupoflinksistransparentifthesignalcarriedisnotre-timedfromaclockassociatedwiththelink(s).Thetimingof
asignal passing across atransparent link may however be altered due to jitter, wander, filtering, orfault conditions. Figure 2
illustrates the definition of transparent and non transparent links.
1.2.24 Wander
The long-term variations of the significant instants of a digital Signal from their ideal positions intime. Long-term implies
that these variations are of low frequency.
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o ISO/IEC ISO/IEC 11573:1994( E)
1.3 Abbreviations and acronyms
Alarm Indication Signal
AIS:
BITS : Building Integrated Timing Supply
International Telegraph and Telephone Consultative Committee
CCITT :
CPE : Customer Premises Equipment
Basic Rate transparent or non transparent links
CO:
Cl : 1,544 Mbits/s transparent or non transparent links
2,048 Mbits/s transparent or non transparent links
c2 :
c3 : Non ISDN transparent or non transparent links
Digital Cross-connect System
DCS :
DSX : Digital Signal Cross - connect
Data Terminal Equipment
DTE :
ESF : Extended Super Frame
Frequency Modulation
FM:
Global Positioning System
GPS :
Maximum Time Interval Error (see figurel)
MTIE :
Multiplexer
MUX :
NCTE : Network Channel Terminating Equipment
Network Interface
NI :
PISN : Private Integrated Services Network.
Private Integrated Services Network Exchange (PABX, Key System, . .).
PINX :
Parts per million
PPm =
Public Switched Telecommunication Network
PSTN :
PLL : Phase Locked Loop
PRC : Primary Reference Glock
Phase Modulation
PM:
SES : Severely Errored Second
Synchronous Digital Hierarchy
SDH :
Basic Rate Access to public ISDN
’ TO:
Tl : 1,544 Mbits/s Access to public ISDN
2,048 Mbits/s Access to public ISDN
T2:
TIE : Time Interval Error (see figurel)
Unit Interval(488 ns for T2 and C2,648 ns for Tl and Cl, 5208 ns for TO and CO)
UI :
UTC : Universal Coordinated Time
AT
Slope representing long
A
te& freqüency departure
Time delay
with respect to
Public Switched Network
ideal reference
in seconds
/
TIME
t---s--+
Observation period
Time Interval Error (TIE) Figure 2 - Links definition
Figure 1 -
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o ISO/IEC
ISO/IEC 11573: 1994(E)
1.4 Impact of Slips
When synchronous digital Signals are being transported over a link, the receiving end must operate at the same average
frequency as the transmitting end to prevent loss of information.
When digitalsignalstraverseanetworkof digital links, switching nodes, multiplexersand transmission interfaces, thetaskof
keeping all the entities operating at the same average frequency is referred to as synchronization. If the distant transmitter
sends ata bit rate higher than the switching System clock, the receive buffer in the switching System eventuallywill overflow,
causing one frame to be lost. If the received bit stream is at a lower bit rate, the buffer will underflow, causing a frame to be
repeated. Ether occurrence is called a controlled Slip.
In adigital PISN, Slips tan be prevented byforcing all equipment to use acommon reference clock. In adigital PISN, when it
is not connected to the public digital network, network synchronization is achieved by having all equipments derive timing
from a Single Source that should be the highest quality clock available.
If a PISN is connected to the public network at one or more nodes, the private network shall derive timing from the public
digital network timing reference to ensure that the highest quality timing Source is used.
The design of a PISN requires specification of the timing sources and receivers to achieve synchronization. Proper design
requires that timing loops in the synchronization plan be eliminated.
The impact of Slips on Service carried on digital networks depends on the application and type of Service being provided.
Some examples of the effects of which are summarized in the following table.
Table 1 - Impacts sf a Slip
_--------~
Service Potential impact
Encrypted text Encryption key must be retransmitted
Video
Digital data
Facsimile Connection establishment may be not successful
Deletion of 4-8 scan lines or lost of throughput,
Voice Band Data
Voice Possible “Click”
Inadditiontoslips,synchronization-relatedimpairmentscaused bytransmissioneffectsonequipmentsuchaserrorbursts
and Phase discontinuity, tan also have an impact on customer Service. These degradations tan propagate and multiply
through the network.
All of the degradations described above tan be controlled by appropriate synchronization strategies and clock designs, as
described in later clauses.
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o ISO/IEC ISO/IEC 11573:1994(E)
Section 2 : Technical requirements, Synchronization methods
2.1 Technical requirements
The Phase stability of a Slave clock tan be described by:
-its lang-term Phase variations (wander and integrated frequency departure);
-its short-term Phase variations (jitter);
-Phase discontinuities due to transient disturbances.
NOTES
1 - The values given in 2.1.1,2.1.2 and 2.1.3 are taken from ETS 300 012 [3] for CO and TO, from ETS 300 Oll [2] for T2 and C2 and from
EIA/TIA-594 [8] for Cl and Tl.
2 -It has been found necessary to limit the wander value for the TO and CO interfaces. The need for the additional Parameters for accuracy
and leck range derives from the strategies in 2.2.8.
3 -Requirements for Phase discontinuity are taken from CCITT Recommendation G.812.
2.1.1 Jitter and wander at the input
2.1.1.1 CO and TO intetfaces (144 kbits/s)
The CO and TO inputs shall tolerate at least a sinusoidal input jitter within the mask shown in figure 3 without producing bit
errors:
Peak to peak jitter and
I Wander amplitude
0,5 Ul
0,05 Ul
I
1 I
I
I I
I
I I
I . 1
) Jitter frequency [Hz]
5 50 2k
Figure 3 - Tolerable jitter and wander at PINX input for Basic Access
In Order to save power, when both B channels are idle, carriers may disable TO interfaces. Under these conditions, timing
information is not available. Synchronization shall be derived from interfaces which are continuously available.
NOTE : The maximum relative wander between two OP more interfaces is limited to 4 Ul (except for plesiochronous Operation).
2.1 .1.2 Cl and Tl interfaces (1,544 Mbits/s)
The equipment shall operate with jitter of the received Signal which does not exceed the following limits, in both bands
simultaneously :
5,0 Ul, peak-to peak, and
(1) Band 1 [IOHz-40kHz]:
[8 kHz - 40 kHz] : 0,l Ul, peak-to-peak.
(2) Band 2
For Tl and non transparent Cl interfaces, the equipment shall operate with wander of the received Signal of up to 28 Ul (18
ps) peak-to-peak over any 24h period and up to 23 Ul (15 ps) peak-to-peak in any 1 h interval.
Wander requirements for transparent Cl interfaces are for further study.
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o ISO/IEC
ISO/IEC 11573:1994(E)
2.1.1.3 C2 and T2 interfaces (2,048 Mbits/s)
The input shall tolerate a sinusoidal input jitter / wander within the mask shown in figure 1 without producing bit errors or
losing frame alignment:
Peak to peak
jitter and wander
amplitude
36,9 Ul
18
13
12.10-6 t 1 0,Ol 1 1,667 1 20 1 2,4k 1 18k 1 1OOk 1 & frequency
4,88.10-3
NOTE : The value of 36,9 Unit Interval (Ul) is the maximum relative wander between two or more intetfaces, except for plesiochronous
Operation.
Figure 4 - Tolerable jltter and wander at PINX Input for 2Mbits/s access
2.1.2 Jitter and wander at the output
Wander accumulation within a private network needs to be controlled. Output jitter requirements of this subclause apply
when the input jitter meets the requirements of 2.1 .l .
2.1.2.1 CO and TO interfaces (144 kbits/s)
For further study.
2.1.2.2 Cl and Tl interfaces (1,544 Mbits/s)
Transmit Signal Jitter for Tl and non transparent Cl interfaces
The jitter of the transmitted Signal at the equipment output interface shall not exceed the following limits, in both bands
simultaneously :
Band 1 0,5 Ul peak-to peak, and
(1)
Band 2 0,07 Ul peak-to-peak.
(2)
Transmit Signal Wander for Tl and non transparent Cl intetfaces
The wander in the transmitted Signal of the equipment shall not exceed the wander of its received Signal by more than 2,5 Ul.
The wander of the transmitted Signal shall not exceed 28 Ul (18 f@ peak-to- peak in any 24h period, nor exceed 23 Ul (15
ps) peak-to- peak in any 1 h intetval under operating conditions defined as having class I clock, or public clock traceability
over facilities with typical short-term impairments that do not include events that result in Phase transients.
It is recognized that currently, the wander in the transmitted Signal may be as large as 7700 Ul (5 ms) peak-to- peak in any
24h period and may be as large as 4600 Ul (3 ms) peak-to-peak in any 1 h interval under normal operating conditions.
However, it must be recognized that such wander will result in frame Slips within the network.
NOTE: Transparent Cl jitter and wander requirements are for further study.
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o ISO/IEC ISO/IEC 11573:1994(E)
2.1.2.3 C2 and T2 intetfaces (2,048 Mbits/s)
T2, one interface
band 1 f E [ 20Hz - IOOkHz] < 1,l Ul
band 2 f E [400Hz - IOOkHz] < 0,ll Ul
T2, multiple interfaces and non transparent C2 interfaces
band 1 f E [ 4Hz - IOOkHz] < 1,l Ul
band 2 f E [40Hz - IOOkHz] < 0,ll Ul
transparent C2 interfaces
f E [ 4Hz - IOOkHz] < 1,6 Ul
band 1
band 2 f E [40Hz - IOOkHz] < 0,l Ul
2.1.3 Frequency deviation at the input
The interfaces shall tolerate input clock rates within the following ranges around the nominal value:
TO t100 ppm
Tl k32 ppm
250 ppm
T2
These values are only relevant for the interfaces, during maintenance and failure conditions, not for the
of the clock
unit.
2.1.4 Accuracy
Accuracy is defined in 1.3
Since class I clocks are intended to be used as master in plesiochronous networks, they only operate
running mode.
In Order to conform with the strategies defined Iater (2.2.8), clocks shall comply with the following classes :
class I <17,1 o--l0
<-Cl ,IO-6
class II
class Ill <+50,1 o-6
NOTES:
1 In certain network configurations, clocks with higher accuracy are necessary (see Annex D).
2 Class Ill free running clocks are typically not used as timing sources.
2.1.5 Lack range
Slave clocks within accuracy of class II and Ill shall comply with one of the following leck range classes :
class a >tl ppm
class b > 250 ppm
The following combinations of Slave clocks are allowed : Ila, Ilb, Illb.
2.1.6 Phase discontinuity of Slave clocks
Phase transients are changes in Phase relationships. Transients are specified in terms of the maximum transient Phase
deviation and the maximum equivalent frequency offset during the transient. The MTIE and Phase-slope requirements
shall also be met under all timing reference degradations, independent of whether a switch of reference has occurred.
(1) In case of internal testing or rearrangement operations within the Slave clock, the following conditions shall be met:
-the Phase Variation over any period of up to 2 l1 Ul must not exceed 1/8 of a Ul;
l1 Ul thephasevariationforeachintervalof211 Ul mustnotexceed 1/8UIuptoatotalamountofl ps,
-for periods greaterthan 2 ,
Where Ul corresponds to the reciprocal of the bit rate of the interface.
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lSO/IEC 11573:1994(E)
o ISO/IEC
(2) Equipment shall operate with transients in the Phase of received Signals of up to 1 j.~s with am aximu m rate of Change
equivalent to 61 ppm frequency offset. Such transients shall be isolated in time.
Additionally, accommodation needs to be made for SDH (SQNET) virtual tributary (VT) pointer adjustments with a
magnitude of 8 Ul (4,7 psfor VCI 1 and 357 ysforVC12). Phase slope characteristics of this transient have yet to be defined
but typicallyfall within a 1 second time frame and to be no greater than the equivalent of afrequency offset of 61 ppm. SDH
(SONET) quantizes input wander into8 Ul Steps. When the upper or lowerthreshold in aSDH (SONET) pointer processor is
reached, the SDH (SONET) pointer processor will generate an outgoing pointer adjustment to either the next downstream
pointer processor or far-end desynchronizer.
(3) When equipment receives a Phase transient conforming (l), its output shall not exceed (1)
2.2 Synchronization methods for PISNs
Operations include both the provisioning and maintenance of the digital synchronization network. Provisioning means
engineering an appropriate configuration for the network and installing any particular equipment necessary to implement
the configuration. Maintenance activities involve the detection of synchronization networkfailures and restoration of timing
distri bution.
2.2.1 High level concepts
(1) The public network is always to be taken as the reference clock Source when available and in operational mode, except
where a PINX contains a clock with characteristics in accordance with class 1, which needs not synchronize its clock
generators to any input.
(2) Synchronization Plans need to be hierarchical; timing is passed from better performing sources to
clocks of lower or
equal performante.
(3) Timing loops need to be eliminated.
(4) Timing sources need to be diverse whenever possible.
(5) The leck range of any node is to be sufficient to cover the accuracy of any potential master.
(6) Cascading of timing references through CPE needs to be minimized.
treated like T type interfaces
(7) Non-transparent C type interfaces are from the synchronization Point of view. The
strategies described here concern only the cases where the private links are transparent.
2.2.2 Reference Glock Switching Criteria
To minimize excessiveswitching ofthe timing referenceand the accumulation of Phase movements, aclockshall not initiate
a switch of reference until the timing reference has become degraded. Reference switch over shall occur at or after, but not
before, any of the following reference line degradations or events:
TO, C
...
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