SIST EN IEC 63287-1:2021

Semiconductor devices - Generic semiconductor qualification guidelines - Part 1: Guidelines for IC reliability qualification (IEC 63287-1:2021)

IEC 63287-1:2021 gives guidelines for reliability qualification plans of semiconductor integrated circuit products. This document is not intended for military- and space-related applications.
NOTE 1 The manufacturer can use flexible sample sizes to reduce cost and maintain reasonable reliability by this guideline adaptation based on EDR-4708, AEC Q100, JESD47 or other relevant document can also be applicable if it is specified.
NOTE 2 The Weibull distribution method used in this document is one of several methods to calculate the appropriate sample size and test conditions of a given reliability project.
This first edition of IEC 63287-1 cancels and replaces the first edition of IEC 60749-43 published in 2017. This edition constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous edition:

   
1. the document has been renamed and renumbered to distinguish it from the IEC 60749 (all parts);

   
2. a new section concerning the concept of "family" has been added with appropriate renumbering of the existing text.

Halbleiterbauelemente - Allgemeine Leitlinien für die Qualifikation von Halbleitern - Teil 1: Leitlinien für die IC-Zuverlässigkeitsqualifikation (IEC 63287-1:2021)

Dispositifs à semiconducteurs - Lignes directrices génériques concernant la qualification des semiconducteurs - Partie 1: Lignes directrices concernant la qualification de la fiabilité des circuits intégrés (IEC 63287-1:2021)

L’IEC 63287-1:2021 fournit des lignes directrices concernant les plans de qualification de la fiabilité des produits de CI à semiconducteurs. Le présent document n’est pas destiné aux applications militaires et spatiales.
NOTE 1 Le fabricant peut utiliser des tailles d’échantillons flexibles afin de réduire les coûts tout en maintenant une fiabilité raisonnable par l’adaptation des présentes lignes directrices fondées sur l’EDR-4708. S’ils sont spécifiés, les documents AEC Q100, JESD47 ou tout autre document pertinent spécifié peuvent également être applicables.
NOTE 2 La méthode de la loi de Weibull utilisée dans le présent document n’est qu’une méthode parmi d’autres permettant de calculer la taille d’échantillon et les conditions d’essai appropriées pour un projet de fiabilité donné.
Cette première édition de l’IEC 63287-1 annule et remplace la première édition de l’IEC 60749‑43 parue en 2017. Cette édition constitue une révision technique.
Cette édition inclut les modifications techniques majeures suivantes par rapport à l'édition précédente:

   
1. le document a été renommé et renuméroté afin de le différencier de l’IEC 60749 (toutes les parties);

   
2. une nouvelle section portant sur le concept de famille a été ajoutée avec une renumérotation appropriée du texte existant.

Polprevodniški elementi - Splošne smernice za kvalifikacijo polprevodnikov - 1. del: Smernice za kvalifikacijo zanesljivosti IC (IEC 63287-1:2021)

General Information

• Status: Published
• Publication Date: 13-Oct-2021
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 07-Oct-2021
• Due Date: 12-Dec-2021
• Completion Date: 14-Oct-2021
• Ref Project: EN IEC 63287-1:2021 - Semiconductor devices - Generic semiconductor qualification guidelines - Part 1: Guidelines for IC reliability qualification

Relations

• Replaces: SIST EN 60749-43:2017 - Semiconductor devices - Mechanical and climatic test methods - Part 43: Guidelines for IC reliability qualification plans (IEC 60749-43:2017)
• Effective Date: 16-Nov-2021

Standards Content (Sample)

SLOVENSKI STANDARD
01-december-2021
Polprevodniški elementi - Splošne smernice za kvalifikacijo polprevodnikov - 1.
del: Smernice za kvalifikacijo zanesljivosti IC (IEC 63287-1:2021)
Semiconductor devices - Generic semiconductor qualification guidelines - Part 1:
Guidelines for IC reliability qualification (IEC 63287-1:2021)
Halbleiterbauelemente - Allgemeine Leitlinien für die Qualifikation von Halbleitern - Teil 1:
Leitlinien für die IC-Zuverlässigkeitsqualifikation (IEC 63287-1:2021)
Dispositifs à semiconducteurs - Lignes directrices génériques concernant la qualification
des semiconducteurs - Partie 1: Lignes directrices concernant la qualification de la
fiabilité des circuits intégrés (IEC 63287-1:2021)
Ta slovenski standard je istoveten z: EN IEC 63287-1:2021
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 63287-1

NORME EUROPÉENNE
EUROPÄISCHE NORM
October 2021
ICS 31.080.01
English Version
Semiconductor devices - Generic semiconductor qualification
guidelines - Part 1: Guidelines for IC reliability qualification
(IEC 63287-1:2021)
Dispositifs à semiconducteurs - Lignes directrices Halbleiterbauelemente - Allgemeine Leitlinien für die
génériques concernant la qualification des semiconducteurs Qualifikation von Halbleitern - Teil 1: Leitlinien für die IC-
- Partie 1: Lignes directrices concernant la qualification de Zuverlässigkeitsqualifikation
la fiabilité des circuits intégrés (IEC 63287-1:2021)
(IEC 63287-1:2021)
This European Standard was approved by CENELEC on 2021-09-29. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Turkey and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2021 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 63287-1:2021 E

European foreword
The text of document 47/2703/FDIS, future edition 1 of IEC 63287-1, prepared by IEC/TC 47
"Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and approved by
CENELEC as EN IEC 63287-1:2021.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2022-06-29
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2024-09-29
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 63287-1:2021 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standards
indicated:
IEC 60068-2-1 NOTE Harmonized as EN 60068-2-1
IEC 60068-2-30 NOTE Harmonized as EN 60068-2-30
IEC 60749-11 NOTE Harmonized as EN 60749-11

Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments)
applies.
NOTE 1  Where an International Publication has been modified by common modifications, indicated by (mod), the relevant
EN/HD applies.
NOTE 2  Up-to-date information on the latest versions of the European Standards listed in this annex is available here:
www.cenelec.eu.
Publication Year Title EN/HD Year
IEC 60749-5 -  Semiconductor devices - Mechanical and EN 60749-5 -
climatic test methods - Part 5: Steady-state
temperature humidity bias life test
IEC 60749-6 -  Semiconductor devices - Mechanical and EN 60749-6 -
climatic test methods - Part 6: Storage at
high temperature
IEC 60749-15 -  Semiconductor devices - Mechanical and EN IEC 60749-15 -
climatic test methods - Part 15: Resistance
to soldering temperature for through-hole
mounted devices
IEC 60749-20 -  Semiconductor devices - Mechanical and EN IEC 60749-20 -
climatic test methods - Part 20: Resistance
of plastic encapsulated SMDs to the
combined effect of moisture and soldering
heat
IEC 60749-21 -  Semiconductor devices - Mechanical and EN 60749-21 -
climatic test methods - Part 21:
Solderability
IEC 60749-23 -  Semiconductor devices - Mechanical and EN 60749-23 -
climatic test methods - Part 23: High
temperature operating life
IEC 60749-25 -  Semiconductor devices - Mechanical and EN 60749-25 -
climatic test methods - Part 25:
Temperature cycling
IEC 60749-26 -  Semiconductor devices - Mechanical and EN IEC 60749-26 -
climatic test methods - Part 26:
Electrostatic discharge (ESD) sensitivity
testing - Human body model (HBM)
IEC 60749-28 -  Semiconductor devices - Mechanical and EN 60749-28 -
climatic test methods - Part 28:
Electrostatic discharge (ESD) sensitivity
testing - Charged device model (CDM) -
device level
IEC 60749-29 -  Semiconductor devices - Mechanical and EN 60749-29 -
climatic test methods - Part 29: Latch-up
test
IEC 60749-42 -  Semiconductor devices - Mechanical and EN 60749-42 -
climatic test methods - Part 42:
Temperature and humidity storage

IEC 63287-1 ®
Edition 1.0 2021-08
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Generic semiconductor qualification guidelines –

Part 1: Guidelines for IC reliability qualification

Dispositifs à semiconducteurs – Lignes directrices génériques concernant la

qualification des semiconducteurs –

Partie 1: Lignes directrices concernant la qualification de la fiabilité des circuits

intégrés
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.01 ISBN 978-2-8322-1017-2

– 2 – IEC 63287-1:2021 © IEC 2021
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 8
4 Product categories and applications . 8
5 Failure . 9
5.1 Failure distribution . 9
5.2 Early failure . 10
5.2.1 Description . 10
5.2.2 Early failure rate . 11
5.2.3 Screening . 15
5.3 Random failure . 17
5.3.1 Description . 17
5.3.2 Mean failure rate . 18
5.4 Wear-out failure . 21
5.4.1 Description . 21
5.4.2 Wear-out failure rate . 21
6 Reliability test . 24
6.1 Reliability test description . 24
6.2 Reliability test plan . 24
6.2.1 Procedures for creating a reliability test plan . 24
6.2.2 Estimation of the test time required to confirm the TDDB from the
number of test samples . 27
6.2.3 Estimation of the number of samples required to confirm the TDDB from
the test time. 28
6.3 Reliability test methods . 29
6.4 Acceleration models for reliability tests . 33
6.4.1 Arrhenius model . 33
6.4.2 V-model . 33
6.4.3 Absolute water vapor pressure model . 33
6.4.4 Coffin-Manson model . 33
6.5 Concept of family . 34
6.5.1 General . 34
6.5.2 Conducting life test using family . 34
6.5.3 Verification of early failure rate using family . 37
7 Stress test methods . 39
8 Supplementary tests . 40
9 Summary table of assumptions . 40
10 Summary . 42
Bibliography . 43

Figure 1 – Bathtub curve . 10
Figure 2 – Failure process of IC manufacturing lots during the early failure period . 11
Figure 3 – Weibull conceptual diagram of the early failure rate . 12

IEC 63287-1:2021 © IEC 2021 – 3 –
Figure 4 – Example of a failure ratio: α (in hundreds) and the number of failures for CL
of 60 % . 14
Figure 5 – Screening and estimated early fail rate in Weibull diagram . 16
Figure 6 – Bathtub curve setting the point immediately after production as the origin . 17
Figure 7 – Bathtub curve setting the point after screening as the origin. 17
Figure 8 – Conceptual diagram of calculation method for the mean failure rate from the
exponential distribution . 18
Figure 9 – Conceptual diagram of calculation method for the mean failure rate as an
extension of early failure . 19
Figure 10 – Conceptual diagram of the wear-out failure . 21
Figure 11 – Conceptual diagram describing the concept of the acceleration test . 22
Figure 12 – Concept of the reliability test in a Weibull diagram (based on sample size) . 26
Figure 13 – Concept of the reliability test in a Weibull diagram (based on test time) . 29
Figure 14 – Difference in sampling sizes according to the m value (image) . 30
Figure 15 – How the screening defect rate is seen depending on the difference of chip
size (example) . 37

Table 1 – Examples of product categories . 9
–6
Table 2 – Cumulative failure probability 0,1 % over 10 years [×10 ] for the third, fifth
and seventh years . 26
Table 3 – Major reliability (life) test methods and purposes . 31
Table 4 – Examples of the number of test samples and the test time in typical reliability
(life) test methods . 32
Table 5 – Concept of family (example) . 34
Table 6 – Concept of difference/failure mechanism/corresponding test item (examples). 36
Table 7 – Factors for calculation examples of early failure rate using family data . 38
Table 8 – LTPD sampling table for acceptance number Ac = 0 . 39
Table 9 – Major reliability (strength) test methods and purposes . 39
Table 10 – Supplementary tests . 40
a
Table 11 – Accelerating factors, calculation formulae and numerical values . 41

– 4 – IEC 63287-1:2021 © IEC 2021
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
GENERIC SEMICONDUCTOR QUALIFICATION GUIDELINES –

Part 1: Guidelines for IC reliability qualification

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as "IEC
Publication(s)"). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 63287-1 has been prepared by IEC technical committee 47:
Semiconductor devices.
This first edition of IEC 63287-1 cancels and replaces the first edition of IEC 60749-43
published in 2017. This edition constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) the document has been renamed and renumbered to distinguish it from the IEC 60749
(all parts);
b) a new section concerning the concept of "family" has been added with appropriate
renumbering of the existing text.

IEC 63287-1:2021 © IEC 2021 – 5 –
The text of this International Standard is based on the following documents:
DRAFT Report on voting
47/2703/FDIS 47/2720/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement,
available at www.iec.ch/members_experts/refdocs. The main document types developed by
IEC are described in greater detail at www.iec.ch/standardsdev/publications.
A list of all parts in the IEC 63287 series, published under the general title Semiconductor,
devices – Generic semiconductor qualification guidelines, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates that it
contains colours which are considered to be useful for the correct understanding of its
contents. Users should therefore print this document using a colour printer.

– 6 – IEC 63287-1:2021 © IEC 2021
INTRODUCTION
This document provides guidelines for semiconductor IC vendors in the preparation of
detailed reliability test plans for device qualification. Such plans are intended to be prepared
before commencing qualification tests and after consultation with the user of their
semiconductor integrated circuit product.
The guideline gives some examples for creating reliability qualification test plans to determine
appropriate reliability test conditions based on the use conditions and requirements for each
application of semiconductor integrated circuits. Categories are set for automotive
applications and for general applications as a target of reliability. The grade for automotive
use is further classified into two grades according to applications. The guideline assumes
annual operating hours, useful life, etc. for each grade, and defines the verification methods
for early failure rate and wear-out failure to propose appropriate reliability tests, and at the
same time, presents concepts to properly ensure the quality of semiconductor integrated
circuits using screening techniques which are designed to reduce the early failure rate.
The test conditions and the values of acceleration factors presented in this guideline are
shown to provide examples of calculations for obtaining reliability test conditions in order to
verify the required quality standards and are not designed to define the standards to ensure
reliability of semiconductor integrated circuits.
NOTE Qualification tests are tests in which the semiconductor vendor takes account of the reliability required by
its product users.
IEC 63287-1:2021 © IEC 2021 – 7 –
SEMICONDUCTOR DEVICES –
GENERIC SEMICONDUCTOR QUALIFICATION GUIDELINES –

Part 1: Guidelines for IC reliability qualification

1 Scope
This part of IEC 63287 gives guidelines for reliability qualification plans of semiconductor
integrated circuit products. This document is not intended for military- and space-related
applications.
NOTE 1 The manufacturer can use flexible sample sizes to reduce cost and maintain reasonable reliability by this
guideline adaptation based on EDR-4708, AEC Q100, JESD47 or other relevant document can also be applicable if
it is specified.
NOTE 2 The Weibull distribution method used in this document is one of several methods to calculate the
appropriate sample size and test conditions of a given reliability project.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
IEC 60749-5, Semiconductor devices – Mechanical and climatic test methods – Part 5:
Steady-state temperature humidity bias life test
IEC 60749-6, Semiconductor devices – Mechanical and climatic test methods – Part 6:
Storage at high temperature
IEC 60749-15, Semiconductor devices – Mechanical and climatic test methods – Part 15:
Resistance to soldering temperature for through-hole mounted devices
IEC 60749-20, Semiconductor devices – Mechanical and climatic test methods – Part 20:
Resistance of plastic encapsulated SMDs to the combined effect of moisture and soldering
heat
IEC 60749-21, Semiconductor devices – Mechanical and climatic test methods – Part 21:
Solderability
IEC 60749-23, Semiconductor devices – Mechanical and climatic test methods – Part 23: High
temperature operating life
IEC 60749-25, Semiconductor devices – Mechanical and climatic test methods – Part 25:
Temperature cycling
IEC 60749-26, Semiconductor devices – Mechanical and climatic test methods – Part 26:
Electrostatic discharge (ESD) sensitivity testing – Human body model (HBM)
IEC 60749-28, Semiconductor devices – Mechanical and climatic test methods – Part 28:
Electrostatic discharge (ESD) sensitivity testing – Charged device model (CDM) – Device
level
– 8 – IEC 63287-1:2021 © IEC 2021
IEC 60749-29, Semiconductor devices – Mechanical and climatic test methods – Part 29:
Latch-up test
IEC 60749-42, Semiconductor devices – Mechanical and climatic test methods – Part 42:
Temperature and humidity storage
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
failure mode
classification of a fault phenomenon which causes product failure
Note 1 to entry: Disconnection, a short circuit, occasional loss, abrasion, characteristic deterioration, etc. are
typical items considered as failure modes.
3.2
failure mechanism
physical, chemical or other process that results in a product failure to meet functional
requirements (or failure modes)
3.3
integrated circuit
IC
microcircuit in which all or some of the circuit elements are inseparably associated and
electrically interconnected so that it is considered to be indivisible for the purpose of
construction and commerce
Note 1 to entry: IEV:521-10-03
4 Product categories and applications
Quality-related requirements, operating hours, and field operating condition of ICs depend on
the applications of products in which they are used. As an example of creating scientific test
plans, their applications are broadly classified into three product categories: Automotive Use
A; Automotive Use B; and Consumer Use. Table 1 shows a list of quality-related requirements
according to each product category and the definition of their use conditions.

IEC 63287-1:2021 © IEC 2021 – 9 –
Table 1 – Examples of product categories
Category Automotive Use A Automotive Use B Consumer Use
Criteria for Applications for automotive Applications for automotive Home or office electronics,
category use directly relating to safety. use not directly relating to toys, appliances and server
(Failures can cause
safety. applications.
accidents.)
Examples of Powertrains, brakes, driving Navigation systems, car air- Home electronics, toys,
applications support systems, airbags conditioners, audio systems appliances
Annual 500 h 500 h Up to 8 760 h
operating hours
Differs depending on whether Differs among applications.
or not to work with KEY
ON/OFF.
Useful life 15 years (cumulative failure 15 years (cumulative failure Up to 10 years (cumulative
probability: 0,1 %) probability: 0,1 %) failure probability: 0,1 %)
Differs among applications.
Assumed Example of engine compartment
operating
T = −40 °C/ T = 125 °C T = 0 °C / T = 70 °C
conditions a,min a,max a,min a,max
T = 100 °C/ T = 150 °C T = 70 °C/105 °C (max.)
(examples of j,typ j,max j
conditions which
RH = 10 (min.)/80 % (max.)
min. RH: 0 / max. RH: 100 %,
differ among
RH (during 20 % power on)
applications) RH (during 10 % driving) (during 70 % stop)
(during 60 % power off)
Example of interior environment
T = -40 °C (min.)/85 °C (max.)
a
T = 85 °C (typ.)/125 °C (max.)
j
RH = 0 (min.)/100 % (max.),
RH (during 10 % driving) (during 70 % stop)
−6 −6 −6
Early failure rate 1 × 10 or below per annum 50 × 10 or below per Up to 500 × 10 per annum
annum
Differs among applications.
Random failure 10 FIT or below 50 FIT or below >50 FIT (typical)
rate
Differs among applications.
NOTE These are examples of application conditions and requirements that do not have to all be met to be
relevant for each use case.
5 Failure
5.1 Failure distribution
Failure distribution of ICs can be broadly divided into three regions: early failure portion
(e.g., t = 1 year), random failure portion, and wear-out failure portion. Figure 1 shows the
ELF
relationship between the field use time and the instantaneous failure rate (bathtub curve).
Failure distributions for each region are described in detail in 5.2 to 5.4.
Most early failures are screened within manufacturing processes of IC vendors. However, ICs
not fully screened can expose problems in a relatively short period after their operation starts
in the field.
– 10 – IEC 63287-1:2021 © IEC 2021
Random failure has been considered to achieve a certain failure rate with respect to time, but
actually, it is appropriate to consider as an extension of the early failure region where the
failure rate continues to decline. Potentially induced failures outside of the supplier’s control,
such as ESD, EOS and soft errors, should not be included in the failure rate calculations
unless a total fail rate that includes these types of fail modes is intended.
Wear-out failure is a failure which occurs due to the end of life of IC components such as
transistors and interconnections, and indicates the life of the ICs themselves. Wear-out failure
is a failure which depends on the usage load profile (time windows may be different). The
number of failures increases with time, and every IC will eventually cause a failure beyond the
intended design life of the part. Wear-out failures are not considered in the same manner,
because they have a totally different mechanism and therefore also a different mathematical
description (failure distribution). Therefore, it is important to prevent this failure during the
durable period. For ICs, the time to reach the cumulative failure probability of 0,15 over the
design life of the part in the given application is generally defined as their design lifetime.

Figure 1 – Bathtub curve
5.2 Early failure
5.2.1 Description
Since ICs contain very small feature sizes and are dense and complex, they are susceptible
to defects generated in manufacturing processes. For this reason, good devices which satisfy
required characteristics and functions are sorted out at the final stage of manufacturing
processes. The ratio of good devices to the total amount produced and tested in this process
is called yield. When sorting good devices, they are measured for as many items as possible
including characteristics and functions required. However, some of these sorted good devices
can include those with built-in latent defects or weaknesses which does not influence
electrical characteristics, and they operate properly during sorting. When the yield is high,
devices with these potential defects are less likely to be included. In contrast, when the yield
is relatively low, there is a high possibility of mixture of these latent defect devices with good
ones. Devices with these potential defects can eventually fail during use due to the shortened
lifetime or the intensity of the user application.

IEC 63287-1:2021 © IEC 2021 – 11 –
A small amount of tested good devices which contain such defects is included in the
manufacturing lot and, as such, its failure rate decreases with time. This is because non-
defective ICs which are unlikely to cause a failure remain when defective ICs are removed
after they cause a failure. In such a case, the shape parameter of the Weibull distribution: m is
less than 1 (m < 1).
To be more specific, when a manufacturing lot has good devices with a potential defect as
shown in Figure 2, electronic products using such devices may cause a failure during use,
and faulty ICs are removed by application screening, repair (component replacement) or
disposition. This leaves reliable ICs.
NOTE It is much preferred to screen out these failures, latent or otherwise, at the IC manufacturer rather than
have them reach the user, where it is more expensive to correct.

Figure 2 – Failure process of IC manufacturing lots
during the early failure period
For this reason, reducing defects generated in manufacturing processes is the major
countermeasure against such failures. Another possible countermeasure is to change the
design to a structure not susceptible to defects if it is feasible.
There are also screening techniques such as burn-in, which operate ICs under relatively
harsh conditions of temperature and/or voltage to induce the defects to fail in advance and
remove them by sorting. This acts to consume the early failure period of ICs before shipment,
which can reduce impacts of the early failure after shipment. Screening can be optimized if
the effect of the above defect reduction is confirmed.
5.2.2 Early failure rate
5.2.2.1 Early failure rate definition
The early failure rate indicates the probability of degradation failures resulting from
manufacturing defects which occur within one year (defined early failure period) after
shipment by IC manufacturers and the operation starts in the field (within assembly
manufacturers’ processes and in end user applications).
The early failure rate is often expressed as "cumulative failure probability", where the failure
rate which occurs during the defined early failure period is numerically expressed in
−6
percentage (%) or parts per million (10 ).

– 12 – IEC 63287-1:2021 © IEC 2021
5.2.2.2 Cumulative fail probability
In general, the cumulative failure probability is expressed as follows.
When the Weibull distribution shape parameter is expressed as m, scale parameter η and time
t, the cumulative failure probability F(t): from 0 to t is defined by Formula (1).
m
 t 
F(t) =1−exp− 
(1)
m
 
η
 
Figure 3 shows the concept of the early failure rate using a Weibull distribution chart.

Key
t : Field use time;
b
t : Value converting the time between screening period to shipment into field use time;
s
P: Operating ratio (0 < P ≤ 1).
Figure 3 – Weibull conceptual diagram of the early failure rate
The following sections describe how to calculate the early failure rate from the confirmation
result of the cumulative failure convergence at screening test.
5.2.2.3 Calculation of the early failure rate
Suppose that the cumulative failure probability F(t ) with the field use time t was obtained as
b b
the confirmation result of the cumulative failure convergence at screening test. The Weibull
scale parameter η is obtained from the following formula:
t
b
η = (2)
m
[−ln(1− F(t ))]
b
Where m indicates the value obtained from the experiment result or an estimated value.
However, in the above formula, if there are zero failures, then F(t ) = 0, and the scale
b
parameter η is undefined, as the denominator goes to 0.
For this reason, the χ (chi-squared) distribution shall be used to define the cumulative failure
probability F (t ) taking account of the confidence level.
c b
IEC 63287-1:2021 © IEC 2021 – 13 –
However, this is based on the premise that the number of samples N is sufficiently large.
NOTE Typical confidence level used in failure rate calculations for semiconductor devices is 60 %.
The cumulative failure probability at the specified confidence level and at the field use time
F (t ) is given by Formula (3).
c b
F (t ) =χ (3)
c b d
g
g,
2×N
where
χ is Chi-square distribution;
g is the confidence level (CL in %);
d is the degree of freedom = (2 × f) + 2;
f is the number of failures;
N is the number of samples.
Substituting (3) into (2) yields the scale parameter taking account of the confidence level:
t
b
η =
(4)
c
[− ln(1− F (t ))]
m
c b
When the value converting the screening period until shipment into field use time t and the
s
calculated value η are used, the early failure rate taking account of the confidence level after
c
shipment: F (t ,t ) is given by the following.
c 1 s
η is used instead of η and the early failure
If failures are found during the early failure period,
c
rate takes no account of the confidence level after shipment. F(t ,t ) is given by the following:
1 s
m
 
(t − t )
1 s
F (t ,t ) = 1− exp− 
(5)
c 1 s
m
 
η
 c 
m
 
(t − t )
1 s
F(t ,t ) = 1− exp− 
(6)
1 s
m
 
η
 
For both Formulae (5) and (6), t = 365 × 24 × P
where
P is the operating ratio ranged from 0 (always off) to 1 (always on);
t is the time point of 1 year after operation start measured in hours (constant
on = 8 760 hours).
– 14 – IEC 63287-1:2021 © IEC 2021
5.2.2.4 Calculation of a failure rate ratio
The failure rate ratio: α between the early failure rate F taking account of a confidence level
c
with g (in %) and the early failure rate F taking no account of the confidence level is
expressed by the following formulae:
F =χ (7)
c
d
g,
2×N
f
F = (8)
N
where f = Number of failures in N = Number of samples.
χ
d
g,
2×N
F
c 2
α = = = (N/f)χ
(9)
d
F f
  g,
 
2×N
N
 
Figure 4 – Example of a failure ratio: α (in hundreds)
and the number of failures for CL of 60 %
F is determined by the number of failures, not by the number of test samples: N.
As the number of failures increases, the ratio between the rates taking account of and without
taking account of the confidence level comes closer to 1.
From Figure 4, when the cumulative number of failures is 50, the failure rate difference
between the early failure rate taking account of the confidence level: F and the early failure
c
rate taking no account of the confidence level: F is 5 % (α = 105 for
N = 50 versus α = 100 for large N).
Therefore, if the difference in the early failure rate depends on the number of failures and the
incorporation of the confidence level is allowable, the early failure rate can be used without
accounting for the confidence level.

IEC 63287-1:2021 © IEC 2021 – 15 –
EXAMPLE:
When a confirmation result of the cumulative failure convergence at screening test is obtained using:
m = 0,3; t = 70 298 hours; N = 2 000; and f = 69,
b
and the early failure rate F (t ,t ) using:
c 1 s
CL of 60 %; t = 70 298 hours; P = 1
s
The scale parameter with confidence level is calculated as η = 5,57 × 10 from Formula (4).
c
−6
The early failure rate with confidence level is calculated as F (t :t ) = 129 × 10 from Formula (5).
c 1 s
The scale parameter taking no account of the confidence level η = 2,15 × 10 from Formula (2).
−6
The early failure rate taking no account of the confidence level F(t :t ) = 124 × 10 from Formula (6).
1 s
Thus, in this example, the failure rate difference between the early failure rate taking account of the confidence
level F and the early failure rate without taking account of the confidence level F is (129 − 124)/124 = 4 %.
c
5.2.3 Screening
Since ICs contain very small feature sizes and are dense with complex geometry, they are
susceptible to defects generated in manufacturing processes. Therefore, some lots classified
as ‘good devices’ contain potential failures with a minor intrinsic defect which does not
influence measured electrical characteristics. This allows the device to operate to
specification during the sorting process. Removing potential failures before shipment and thus
reducing or eliminating the early field failure rate is called screening.
General screening methods to remove devices containing such minor intrinsic defects include
the application of stricter stresses such as voltage and temperature than those under actual
use conditions, combining a product test and burn-in, methods to remove initial defects in
packages using X-ray inspections and visual inspections and combining mounting stress and
stresses under a temperature cycle test, etc. Screening conditions need to be adjusted when
necessary depending on the target early failure rate. They should be examined in a manner
that the screening itself will not influence the useful life significantly, i.e. reduce the time to
wear out. By stabilizing the product manufacturing lines and manufacturing the product
carefully to reduce intrinsic manufacturing defects, the product early failure rate can also be
reduced.
Burn-in has generally been conducted after packaging, but recently, it is common to conduct it
to die on wafers. Both methods will produce the same effect in terms of the purpose of
removing manufacturing defects in device die. Figure 5 shows the relationship between the
screening and the early failure rate which can be statistically estimated.

– 16 – IEC 63287-1:2021 © IEC 2021

Figure 5 – Screening and estimated early fail rate in Weibull diagram
Figure 5 shows the verification method for the early failure rate after screening which can be
estimated statistically. In some cases, burn-in is repeated until no actual burn-in failure occurs
to confirm the convergence of the screening but, as shown in Figure 5, the early failure
always occurs even at a slight rate when it is statistically estimated in the Weibull distribution.
For this reason, the sampling becomes meaningless unless data is statistically analysed
taking account of the experimental parameter, acceleration factor, and fail
...