SIST HD 593.1 S1:1997
(Main)Microprocessor system BUS - 8-bit and 16-bit data (MULTIBUS I) -- Part 1: Functional description with electrical and timing specifications
Microprocessor system BUS - 8-bit and 16-bit data (MULTIBUS I) -- Part 1: Functional description with electrical and timing specifications
This first edition describes the elements of the system bus. Applies to interface system components intended for data processing, data storage, and peripheral control devices.
Mikroprozessor-Systembus I für 8 Bit- und 16 Bit-Datenübertragung (MULTIBUS I) -- Teil 1: Funktionsbeschreibung, elektrische Anforderungen und Zeitverhalten
BUS système à microprocesseurs - Données: 8 bits et 16 bits (MULTIBUS 1) -- Partie 1: Description fonctionnelle avec spécifications électriques et chronologiques
S'applique aux composants d'interface du système et doit être utilisée lors de l'interconnexion des sous-ensembles de traitement de l'information, de stockage et des contrôleurs périphériques dans une configuration étroitement couplée. Ce système d'interface comprend les signaux nécessaires pour permettre aux divers composants du système de dialoguer entre eux. Il permet le transfert de données d'entrée/sortie et de mémoire, les accès directs à la mémoire, la génération d'interruptions, etc. Fournit une description détaillée de tous les éléments et caractéristiques qui constituent le bus système.
Mikroprocesorski sistem BUS za 8- in 16-bitne podatke (MULTIBUS I) - 1. del: Funkcionalni opis z električnimi in časovnimi specifikacijami (IEC 60796-1:1990)
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
SIST HD 593.1 S1:1997
01-avgust-1997
0LNURSURFHVRUVNLVLVWHP%86]DLQELWQHSRGDWNH 08/7,%86, GHO
)XQNFLRQDOQLRSLV]HOHNWULþQLPLLQþDVRYQLPLVSHFLILNDFLMDPL ,(&
Microprocessor system BUS - 8-bit and 16-bit data (MULTIBUS I) -- Part 1: Functional
description with electrical and timing specifications
Mikroprozessor-Systembus I für 8 Bit- und 16 Bit-Datenübertragung (MULTIBUS I) -- Teil
1: Funktionsbeschreibung, elektrische Anforderungen und Zeitverhalten
BUS système à microprocesseurs - Données: 8 bits et 16 bits (MULTIBUS 1) -- Partie 1:
Description fonctionnelle avec spécifications électriques et chronologiques
Ta slovenski standard je istoveten z: HD 593.1 S1:1992
ICS:
35.160 Mikroprocesorski sistemi Microprocessor systems
SIST HD 593.1 S1:1997 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
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SIST HD 593.1 S1:1997
NORME
CEI
INTERNATIONALE IEC
60796-1
INTERNATIONAL
Première édition
STAN DARD
First edition
1990-09
Bus système à microprocesseurs –
Données: 8 bits et 16 bits (MULTIBUS I)
Première partie:
Description fonctionnelle avec spécifications
électriques et chronologiques
Microprocessor system bus –
8-bit and 16-bit data (MULTIBUS I)
Part 1:
Functional description with electrical
and timing specifications
IEC 1990 Droits de reproduction réservés
© — Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in
utilisée sous quelque forme que ce soit et par aucun any form or by any means, electronic or mechanical,
procédé, électronique ou mécanique, compris la photo- including photocopying and microfilm, without permission in
y
copie et les microfilms, sans l'accord écrit de l'éditeur: writing from the publisher.
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: +41 22 919 0300 e-mail: inmail@iec.ch IEC web site http: //www.iec.ch
CODE PRIX v /^
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PRICE CODE /^/`^
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IEC MeiHpyHapogHaa 3nenrporexHwiecKaa HonnHCCHR
Pour prix, voir catalogue en vigueur
• • For price, see current catalogue
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CONTENTS
Page
FOREWORD 9
PREFACE 13
INTRODUCTION 13
SECTION ONE - GENERAL
Clause
1.1 Scope 13
1.2 Object 15
1.3 Definitions 15
1.3.1
General System Terms 15
1.3.1.1
Compatibility (IEC Publication 625-1) 15
1.3.1.2
Bus Cycle 17
1.3.1.3
Interface (IEC Publication 625-1) 17
1.3.1.4 Interface System (IEC Publication 625-1) 17
1.3.1.5 Override 17
1.3.1.6 System 17
1.3.2 Signals and Paths (IEC Publication 625-1) 17
1.3.2.1
Bus (IEC Publication 625-1) 17
1.3.2.2
Byte 17
1.3.2.3 Word 17
1.3.2.4
Signal (IEC Publication 625-1) 17
1.3.2.5
Signal Parameter (IEC Publication 625-1) 19
1.3.2.6
Signal Level (IEC Publication 625-1) 19
1.3.2.7 High State (IEC Publication 625-1) 19
1.3.2.8
Low State (IEC Publication 625-1) 19
1.3.2.9
Signal Line (IEC Publication 625-1) 19
1.3.2.10 Master 19
1.3.2.11 Slave 19
SECTION TWO - FUNCTIONAL SPECIFICATIONS
2.1 Bus Elements 21
2.1.1 Masters 21
2.1.2 Slaves 23
2.1.3 Bus Signals 23
2.1.3.1
Control Lines 25
2.1.3.1.1
Clock Lines 25
2.1.3.1.2
Command Lines (MWTC*, MRDC*, IOWC*, IORC*) 25
2.1.3.1.3
Transfer Acknowledge Line (XACK*) 27
2.1.3.1.4
Initialize (INIT*) 27
2.1.3.1.5
Lock (LOCK*) 27
2.1.3.2 Address and Inhibit Lines 27
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Clause Page
2.1.3.2.1 Address Lines (24 lines) 27
2.1.3.2.2 Byte High Enable Line (BHEN*) 27
2.1.3.2.3 Inhibit Lines (INH1* and INH2*) 29
29
2.1.3.3 Data Lines (D0*-D15*)
29
2.1.3.4 Interrupt Lines
2.1.3.4.1 Interrupt Request Lines (INTO*-INT7*) 29
2.1.3.4.2 - Interrupt Acknowledge (INTA*) 29
2.1.3.5 Bus Exchange Lines 31
2.1.3.5.1 Bus Request (BREQ*) 31
2.1.3.5.2 Bus Priority (BPRN* and BPRO*) 31
31
2.1.3.5.3 Bus Busy (BUSY*)
2.1.3.5.4 Common Bus Request (CBRQ*) 31
2.2 Data Transfer Operation 31
33
2.2.1 Data Transfer Overview
2.2.2 Signal Descriptions 35
2.2.2.1 Initialize (INIT*) 35
2.2.2.2 Constant Clock (CCLK*) 37
2.2.2.3 Address Lines (A0*-A23*) 37
2.2.2.4 Data Lines (D0*-D15*) 37
41
2.2.2.5 Bus Commands
43
2.2.2.5.1 Read Operation
2.2.2.5.2 Write Operation 45
45
2.2.2.5.3 Transfer Acknowledge (XACK*)
47
2.2.2.5.4 Inhibit (INH1* and INH2*)
53
2.2.2.6 Lock (LOCK*)
53
2.3 Interrupt Operations
2.3.1 Interrupt Signal Lines 53
Interrupt Request Lines (INTO*-INT7*) 53
2.3.1.1
2.3.1.2 Interrupt Acknowledge (INTA*) 55
2.3.2 Classes of Interrupt Implementation 55
Non-Bus Vectored Interrupts 55
2.3.2.1
2.3.2.2 Bus Vectored Interrupts 57
2.4 Bus Exchange 59
2.4.1 Bus Exchange Signals 59
2.4.1.1 Bus Clock (BCLK*) 59
2.4.1.2 Bus Busy (BUSY*) 61
Bus Priority IN (BPRN*) 61
2.4.1.3
Bus Priority OUT (BPRO*) 63
2.4.1.4
2.4.1.5 Bus Request (BREQ*) 63
2.4.1.6 Common Bus Request (CBRQ*) (Optional) 63
Bus Exchange Priority Techniques 65
2.4.2
65
2.4.2.1 Serial Priority Technique
65
2.4.2.2 Parallel Arbitration Technique
SECTION THREE - ELECTRICAL SPECIFICATIONS
69
3.1 General Bus Considerations
69
3.1.1 Logical and Electrical State Relationships
3.1.2 Signal Line Characteristics 71
71
3.1.2.1 In-Use Signal Line Requirements
73
3.1.2.2 Backplane Signal Trace Characteristics
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Clause Page
3.1.3 Power Supply Specification 73
3.1.4 Temperature and Humidity 79
3.2 Timing 79
3.2.1 Read Operations (I/O and Memory) 85
3.2.2 Write Operations (I/O and Memory) 85
3.2.3 Inhibit Operations 87
3.2.4 Interrupt Implementations 87
3.2.4.1 NBV Interrupts 89
3.2.4.2 BV Interrupts 89
3.2.5 Bus Control Exchanges 91
3.2.5.1 Serial Priority 93
3.2.5.2 Parallel Priority 95
3.2.6 Miscellaneous Timing 95
3.3 Receivers, Drivers and Terminations 97
SECTION FOUR - LEVELS OF COMPLIANCE
4.1 Variable Elements of Capability 105
4.1.1 Data Path 105
4.1.2 Memory Address Path 105
4.1.3 I/O Address Path 105
4.1.4 Interrupt Attributes 105
4.2 Masters and Slaves 107
4.3 Compliance Level Notation 109
4.3.1 Data Path 109
4.3.2 Memory Address Path 109
4.3.3 I/O Address Path 109
4.3.4 Interrupt Attributes 109
4.3.5 Example 109
4.3.6 Compliance Marking 111
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INTERNATIONAL ELECTROTECHNICAL COMMISSION
MICROPROCESSOR SYSTEM BUS - 8-BIT AND 16-BIT DATA
(MULTIBUS I)
Part 1: Functional description with electrical
and timing specifications
FOREWORD
1) The formal decisions or agreements of the IEC on technical matters,
prepared by Technical Committees on which all the National Committees
having a special interest therein are represented, express, as nearly
as possible, an international consensus of opinion on the subjects
dealt with.
2) They have the form of recommendations for international use and they
are accepted by the National Committees in that sense.
In order to promote international unification, the IEC expresses the
3)
wish that all National Committees should adopt the text of the IEC
recommendation for their national rules in so far as national con-
ditions will permit. Any divergence between the IEC recommendation and
the corresponding national rules should, as far as possible, be clearly
indicated in the latter.
The IEC has not laid down any procedure concerning marking as an
4)
indication of approval and has no responsibility when an item of
equipment is declared to comply with one of its recommendations.
PREFACE
This standard has been prepared by Sub-Committee 47B*: Microprocessor
Systems, of IEC Technical Committee No. 47: Semiconductor Devices.
This standard forms Part 1 of a series of publications, the other parts
being:
- Publication 796-2 (1990): Microprocessor system bus - 8-bit and
16-bit data (MULTIBUS I) - Part 2: Mech-
anical and pin descriptions for the system
bus configuration, with edge connectors
(direct).
- Publication 796-3 (1990) : Part 3: Mechanical and pin descriptions for
the Eurocard configuration with pin and
socket (indirect) connectors.
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The text of this standard is based upon the following documents:
Six Months' Rule Report on Voting
47B(C0)8
47B(C0)14
Full information on the voting for the approval of this standard can be
found in the Voting Report indicated in the above table.
The following IEC publication is quoted in this standard:
Publication No. 625-1 (1979): An interface system for programmable
measuring instruments (byte serial, bit
parallel), Part 1: Functional specifica-
tions, electrical specifications, mechan-
ical specifications, system applications
and requirements for the designer and
user.
IEC Sub-Committee 47B has now been transferred to ISO/IEC JTC 1.
This standard was approved according to IEC procedures and is therefore
published as an IEC standard.
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MICROPROCESSOR SYSTEM BUS - 8-BIT AND 16-BIT DATA
(MULTIBUS I)
Part 1: Functional description with electrical
and timing specifications
INTRODUCTION
This standard is one of a series which deals with the electrical and
mechanical interfaces to allow various microprocessor system components to
interact with each other. The interface bus serves as a parallel transfer
and utility signal interconnect for closely coupled system components. The
series consists of one functional description and two alternative mechanical
standards.
SECTION ONE - GENERAL
1.1 Scope
This standard is applicable to interface system components, for use
in interconnecting data processing, data storage, and peripheral
control devices in a closely coupled configuration. This interface
system contains the necessary signals to allow the various system
components to interact with each other. It allows memory and Input/
Output (I/O) data transfers, direct memory accesses, generation of
interrupts, etc. This standard provides a detailed description of all
the elements and features that make up the system bus.
The bus supports two independent address spaces: memory and I/O.
During memory cycles the bus allows direct addressability of up to 16
megabytes using 24-bit addressing. During I/O bus cycles, the bus
allows addressing of up to 64K I/O ports using 16-bit addressing.
Both memory and I/O cycles can support 8-bit data transfers.
The bus structure is built upon the master-slave concept where the
master device in the system takes control of the bus and the slave
device, upon decoding its address, acts upon the command provided
by the master. This handshake (master-slave relationship) between the
master and slave devices allows modules of different speeds to be
interfaced via the bus. It also allows data rates up to five million
transfers per second (bytes or words) to take place across the bus.
Another important feature of the bus is the ability to connect
multiple master modules for multiprocessing configurations. The bus
provides control signals for connecting multiple masters in either a
serial or parallel priority fashion. With either of these two arrange-
ments, more than one master may share bus resources.
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This standard has been prepared for those . users who intend to
evaluate or design products that will be compatible with the system
bus structure. To this end, the necessary signal definitions and timing
and electrical specifications have been covered in detail.
This standard deals only with the interface characteristics of
microcomputer devices and not with design specifications, performance
requirements, and safety requirements of modules.
Throughout this standard, the term "system" denotes the byte or
word interface system that, in general, includes all the circuits,
connectors, and control protocol to effect unambiguous data transfer
between devices. The term "device" or "module" denotes any product
connected to the interface system that communicates information via the
bus, and that conforms to the interface system definition.
1.2 Object
This standard is intended to:
1)
define a general purpose microcomputer system bus;
2) specify the device-independent electrical and functional interface
requirements that a module shall meet in order to interconnect and
communicate unambiguously via the bus system;
3) specify the terminology and definitions related to the system;
4) enable the interconnection of independently manufactured devices
into a single functional system;
5) permit products with a wide range of capabilities to be inter-
connected to the system simultaneously;
6) define a system with a minimum of restrictions on the performance
characteristics of devices connected to the system.
1.3
Definitions
The following general definitions apply for the purpose of this
standard. More detailed definitions can be found in the relevant
sub-clause.
1.3.1 General System Terms
1 .3.1 .1
Compatibility (IEC Publication 625-1)
The degree to which devices may be interconnected and used, with-
out modification, when designed as defined throughout this
standard
(e.g. mechanical, electrical, functional).
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1.3.1.2 Bus Cycle
The process whereby digital signals effect the transfer of data bytes
or words across the interface by means of an interlocked sequence of
control signals. ".Interlocked" denotes a fixed sequence of events in
which one event shall occur before the next event can occur.
1.3.1.3 Interface (IEC Publication 625-1)
A common boundary between a considered system and another
system, or between parts of a system, through which information is
conveyed.
1.3.1.4 Interface System (IEC Publication
625-1)
The set of device-independent mechanical, electrical and functional
elements of an interface necessary to effect communication among a set
of devices. Cables, connectors, driver and receiver circuits, signal
line descriptions, timing and control conventions and functional logic
circuits are typical system elements.
1.3.1.5 Override
A bus master overrides the bus control logic when it is necessary to
guarantee itself back-to-back bus cycles. This is called "overriding"
or "locking" the bus, temporarily preventing other masters from using
the bus.
1.3.1.6 System
A set of interconnected elements which achieve a given objective
through the performance of a specified function.
1.3.2 Signals and Paths (IEC Publication 625-1)
1.3.2.1 Bus (IEC Publication 625-1)
A signal line or a set of signal lines used by an interface system to
which a number of devices are connected and over which messages are
carried.
1.3.2.2 Byte
A group of eight concurrent binary digits operated on as a unit.
1.3.2.3 Word
Two bytes or sixteen bits operated on as a unit.
1.3.2.4 Signal (IEC Publication 625-1)
The physical representation of information.
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Note.- For the purpose of this standard, this is a restricted defi-
nition of what is often called "signal" in the general sense,
and hereinafter refers to digital electrical signals only.
1.3.2.5 Signal Parameter (IEC Publication 625-1)
That parameter of an electrical quantity whose value or sequence of
values conveys information.
1.3.2.6
Signal Level (IEC Publication 625-1)
The magnitude of a signal compared to an arbitrary reference
magnitude (voltage in the case of this standard) .
1.3.2.7 High State
(IEC Publication 625-1)
The more positive voltage level used to represent one of two logical
binary states.
1.3.2.8 Low State
(IEC Publication 625-1)
The more negative voltage level used to represent one of two logical
binary states.
1.3.2.9
Signal Line (IEC Publication 625-1)
One of a set of signal conductors in an interface system used to
transfer messages among interconnected devices.
1.3.2.10 Master
A functional module capable of initiating data bus transfer.
1.3.2.11
Slave
A functional module capable of responding to data transfer operations
generated by a master.
SECTION TWO - FUNCTIONAL SPECIFICATIONS
This section provides an overall understanding of how the bus functions
and describes the elements that connect to the bus, the signals that
provide the interface to the bus and the different types of operations
performed on the bus.
In this section, as well as throughout the standard, a clear and
consistent notation for signals has been used. The Memory Write Command
(MWTC) will be used to explain this notation. The terms one: zero and
true: false can be ambiguous, so their use will be avoided. In their place,
we will use the terms electrical High (H) and Low (L). A nathan ("*", a
non-superscript asterisk) following the signal name (MWTC*) indicates that
the signal is active low as shown below:
MWTC* = asserted at 0 V
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The signal (MWTC*) driven by a three state driver will be pulled up
to VCC when not asserted. The following is used to further explain
the notation used in this standard.
Definition
Electrical State
Function
logic
1 True Active, asserted
H
MWTC
L 0 False
L 1 True Active, asserted
MWTC*
H 0 False
2.1 Bus Elements
This clause describes the elements (masters and slaves) that inter-
face to the bus and the bus signal lines that comprise this interface.
2 1 1 Masters
A master is any module having the ability to control the bus. The
master exercises this control by acquiring the bus through bus
exchange logic and then generating command signals, address signals,
and memory or I/O addresses. To perform these tasks, the master is
equipped with either a central processing unit or logic dedicated to
transferring data over to the bus, to and from other destinations.
Figure 1, page 23, depicts a system that includes a master and two
slave modules.
The system bus architecture can support more than one master in
the same system, but in order to do this, there shall be a means for
each master to gain control of the bus. This is accomplished through
the bus exchange logic (see Clause 2.4) .
Masters may operate in one of two modes of operation. Modes 1 and 2
are defined as follows:
Mode 1: Masters are limited to single bus transfers per bus connect.
If all masters are in Mode 1, system timing is rendered
deterministic by conformance with a maximum bus busy
period. That period is limited by the parameter t max.
BYSO
(see Sub-clause 3.2.5) .
Mode 2: Masters are unlimited in the bus control. They may invoke
bus override. Bus timeouts are allowed. Conformance with
the maximum busy period is not required.
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The last classification is included to allow for. a very broad class of
operations, giving users maximum flexibility in meeting the needs of
their applications. The first mode of operation is defined to allow
system designers to predict the overall performance of their systems
without concern .for uncontrolled timing parameters such as bus
timeout. For masters which can only operate in Mode 2, their specifi-
cation shall state "Mode 2 master only".
2.1.2 Slaves
Another type of module that can interface to the bus is the slave.
Slave modules decode the address lines and act upon the command
signals from the masters. The slaves are not capable of controlling the
bus. Some examples of bus slaves are shown in Figure 1.
2.1.3
Bus Signals
Signals transferred over the bus can be grouped into several classes
based on the functions they perform. The classes are:
1) Control lines
2) Address and inhibit lines
3) Data lines
4) Interrupt lines
5) Bus exchange lines
TO USER I/O
-I [–MASTER
CPU
I/O
^
I SLAVE ESLAVE
PARALLEL
BUS
I/O
I/O
GLOBAL (SYSTEM)
EXCHANGE
MEMORY
MEMORY
GLOBAL (SYSTEM) I/O I (
L,
--- — — —W L — --- — _WJ
BUFFERS
C7
0
o W
oW
J
L---- ---t
J a W
â
cc
O
a Qo
0 0
z
a
^
TQ T Q
i
•
SYSTEM BUS
452/90
Fig. 1. - Bus master and slave example.
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IEC -
The following sub-clauses explain the different classes of bus
signals.
2.1.3.1 Control Lines
The following signals are classified as control lines:
Signal
Class Function
Clocks Constant clock CCLK*
Bus clock BCLK*
Memory write MWTC*
Commands
Memory read MRDC*
I/O write IOWC*
I/O read IORC*
Transfer acknowledge XACK*
Acknowledge
Initialize INIT*
LOCK*
Lock
2.1.3.1.1 Clock Lines
1) Bus Clock (BCLK*)
A periodic signal used to synchronize the bus contention logic; it
may be slowed, stopped, or single stepped. The Bus Clock shall
be generated by one and only one source within the system. This
means that each standalone bus master shall have the capability of
generating an acceptable clock that can optionally be connected to,
or disconnected from, the bus. In a multimaster system, only one
of the masters shall have its clock connected to the bus.
2) Constant Clock (CCLK*)
A periodic signal of constant frequency, which may be used by
masters or slaves as a master clock. The Constant Clock shall be
generated by only one source within the system. This means that
each bus master shall have the capability of generating an accept-
able clock that can optionally be connected to, or disconnected
from, the bus. In a multimaster system, only one of the masters
shall have its clock connected to the bus.
2.1.3.1.2 Command Lines (MWTC*, MRDC*, IOWC*, IORC*)
The command lines are elements of a communication link between the
masters and slaves. There are two command lines for memory and two
command lines for I/O. An active command line indicates to the slave
that the address lines are carrying a valid address, and that the slave
is to perform the specified operation. In a data write cycle, the active
command line (MWTC* or IOWC*) additionally indicates that the data is
valid on the bus. In a data read cycle, the transition of the command
(MRDC* or IORC*) from active to inactive indicates that the master
has received the data from the slave.
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2.1.3.1.3 Transfer Acknowledge Line
(XACK*)
This line is used by the slaves to acknowledge commands from the
master. XACK* indicates to the master that the requested action is
complete, and that data has been placed on, or accepted from, the
data lines.
2.1.3.1.4
Initialize (INIT*)
The INIT* signal is generated to reset the entire system to a known
internal state. This signal is usually generated prior to starting any
operation on the system. INIT* may be generated by any or all of
the bus masters or by an external source such as a buffered and
debounced front panel switch.
2.1.3.1.5
Lock (LOCK*)
The LOCK* signal is generated by the master in control of the bus
to indicate that the bus is locked. LOCK* is used to extend mutual
exclusion to multiple port RAM designs.
2.1.3.2 Address and Inhibit Lines
The address and inhibit lines are used for the following signals:
Function Signal
Address Lines A0*-A23*
Byte High Enable BHEN*
Inhibit Lines INH1* and INH2*
2.1.3.2.1 Address Lines (24 lines)
These lines, which specify the address of the referenced memory
location or I/O device, allow a maximum of 16 megabytes (16 777 216
bytes) of memory to be accessed. When addressing an I/O device, a
maximum of 16 address lines (A0*-A15*) are used, thus allowing the
addressing of a maximum of 64K devices. An I/O module shall also be
able to be configured to decode only eight address lines (A0*-A7*) and
ignore the upper eight lines (see Sub-clause 2.2.2.3) .
2.1 .3.2.2 Byte High Enable Line '(BHEN*)
This byte control line is used to enable the upper byte (bits 8-F) of
a 16-bit word to drive the bus. The signal is used only on systems
that incorporate 16-bit data transfers.
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2.1.3.2.3 Inhibit Lines (INH1* and INH2*)
The inhibit lines can be invoked for any memory read or memory
write operation (MRDC* or MWTC*) . An inhibit line is asserted by a
slave to inhibit another slave's bus activity during a memory read or
write operation. The inhibit signal generated by the inhibiting slave is
derived from decoding the memory address lines. The inhibiting slave
can decode a single address, a block of addresses, or any combination
of single and block addresses.
When it detects the specific address during an actual command
(MRDC* or MWTC*), the inhibiting slave generates an inhibit signal,
which is sensed by the inhibited slave. When so inhibited, this slave
module disables its drivers from all data, address, and acknowledge
bus lines, although it may actually perform internal operations. (All
modules that may be inhibited shall have completed internal operations
within 1.5 ps from the start of the command line. This interval
(1.5 ps) is also the minimum acknowledge timing from modules issuing
inhibits. This guarantees that inhibited modules have enough time to
return to their normal state before the current bus command is
completed.)
2.1.3.3 Data Lines (D0*-D15*)
These 16 bidirectional data lines transmit and receive information to
and from a memory location or an I/O port. (D15* is the most signifi-
cant bit and DO* is the least significant bit.) In 8-bit systems, only
lines D0*-D7* are valid.
2.1.3.4 Interrupt Lines
The interrupt lines consist of the following signals:
Function Signal
Interrupt Requests INTO*-INT7*
Interrupt Acknowledge INTA*
2.1 .3.4.1 Interrupt Request Lines (I NT0*-I NT7*)
Interrupts are requested by activating one of the eight interrupt
request lines. INTO* has the highest priority and INT7* has the lowest
priority.
2.1 .3.4.2
Interrupt Acknowledge (I NTA*)
In response to an Interrupt Request signal, an Interrupt Acknowl-
edge signal can be generated by a bus master with bus vectored
interrupt capability. The Interrupt Acknowledge signal is used to
freeze the interrupt status and request the placement of the interrupt
vector address on the bus data lines.
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2.1.3.5
Bus Exchange Lines
The bus exchange lines are used by the following signals:
Function Signal
Bus Clock BCLK*
Bus Request BREQ*
Bus Priority BPRN*, BPRO*
Bus Busy BUSY*
Common Bus Request CBRQ*
A master gains control of the bus through the manipulation of these
signals.
2.1 .3.5.1 Bus Request (B R EQ*)
A signal used by the bus masters in a priority resolution circuit to
indicate a request for control of the bus.
2.1.3.5.2
Bus Priority (BPRN* and BPRO*)
The priority functions allow masters to break deadlocks that occur
when more than one master concurrently requests the bus. The Bus
Priority IN (BPRN*) signal indicates to a particular master that no
higher priority master is requesting use of the bus. The Bus Priority
OUT (BPRO*) signal is used in serial (daisy chain) bus priority
resolution schemes. In such a scheme, BPRO* is passed by one master
to the BPRN* input of the master with the next lower bus priority;
when active, the BPRO* signal indicates that the higher priority
master does not require control of the bus.
2.1.3.5.3 Bus Busy (BUSY*)
A signal activated by the master in control of the bus to indicate
that the bus is in use. This prevents other masters from gaining
control of the bus.
2.1.3.5.4 Common Bus Request (CBRQ*)
A signal that maximizes a master's data transfer rate to the bus by
sensing the absence of other bus requests. The CBRQ* signal does
this by serving two functions. It indicates to the master controlling
the bus whether or not another master needs to gain control of the
bus. For the other masters, it is a means of notifying the controlling
bus master that it shall relinquish control of the bus if it is not using
the bus.
2.2 Data
Transfer Operation
The primary function of the system bus architecture is to provide a
path for the transfer of data between modules on the bus. The follow-
ing sub-clauses describe the different types of data transfers and the
means by which they are implemented using the signals previously
described. Figure 2, page 33, can be referenced during the following
discussion.
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The discussion of the data transfer operation of the bus is covered
in three parts:
1) An overview of the operation.
2) A detailed description of the signals used in the transfer.
3) A discussion of the specifics pertaining to the different transfers.
It is assumed in this discussion that there is only one master on the
bus, and therefore no bus contention exists. (The bus exchange logic
is discussed in Clause 2.4.)
I/O SLAVE
IOWC* AND IORC*
COMMAND
•
Do*-D15*
• DATA
AO*-A15*
• ADDRESS
BUS MASTER
BHEN*
INTERRUPTS
I/O COMMANDS
TRANSFER ACKNOWLEDGE
DATA
• CLOCK
ADDRESS --4,
BHEN* INTA*
INIT*
4
INTERRUPTS
XACK*
TRANSFER ACKNOWLEDGE ^
C
...
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