SIST EN IEC 62433-6:2021

EMC IC modelling - Part 6: Models of integrated circuits for pulse immunity behavioural simulation - Conducted pulse immunity modelling (ICIM-CPI) (IEC 62433-6:2020)

The objective of this part of IEC 62433 is to describe the extraction flow for deriving an
immunity macro-model of an Integrated Circuit (IC) against conducted Electrostatic Discharge
(ESD) according to IEC 61000-4-2 and Electrical Fast Transients (EFT) according to
IEC 61000-4-4.
The model addresses physical damages due to overvoltage, thermal damage and other failure
modes. Functional failures can also be addressed.
This model allows the immunity simulation of the IC in an application. This model is commonly
called "Integrated Circuit Immunity Model Conducted Pulse Immunity", ICIM-CPI.
The described approach is suitable for modelling analogue, digital and mixed-signal ICs.
Several terminals of an IC can be part of a single model (e.g. input, output and supply pins).
The implementation of the model is capable of representing the non-linear behaviour of
overvoltage protection circuits.
The model can be implemented for the use in different software tools for circuit simulation in
time-domain. The described modelling approach allows simulating device failure due to ESD
or EFT at component and system level considering all components necessary for the immunity
simulation of an IC, such as a PCB or external protection elements.
This document demonstrates, in detail, the construction of models in a defined XML-based
format which is suitable for the exchange of models without any deeper knowledge of the
semiconductor circuit. However, the model functionality can be implemented in different
formats including, but not limited to, tables, SPICE[1] 1 netlists, hardware description
languages such as VHDL-AMS [2] and Verilog-AMS [3].
This document provides:
• the description of ICIM-CPI macro-model elements representing electrical, thermal or
logical behaviour of the IC.
• a universal data exchange format based on XML.

EMV-IC-Modellierung - Teil 6: Modelle integrierter Schaltungen für die Simulation des Verhaltens bei Störfestigkeit gegen Impulse - Modellierung der Störfestigkeit gegen leitungsgeführte Impulse (ICIM-CPI) (IEC 62433-6:2020)

Modèles de circuits intégrés pour la CEM - Partie 6: Modèles de circuits intégrés pour la simulation du comportement d'immunité aux impulsions - Modélisation de l'immunité aux impulsions conduite (ICIM-CPI) (IEC 62433-6:2020)

L'IEC 62433-6:2020 a pour objet de décrire la méthode d'extraction d’un macromodèle d'immunité d'un circuit intégré aux décharges électrostatiques (DES) conduites selon l'IEC 61000-4-2 et aux transitoires électriques rapides (TER) selon l'IEC 61000‑4‑4.
Le modèle couvre les dommages physiques dus à la surtension, les dommages thermiques et d’autres modes de défaillance. Les défaillances fonctionnelles peuvent également être traitées par ce modèle. Ce modèle permet de simuler l'immunité du circuit intégré dans une application. Ce modèle est communément appelé "modèle d'immunité des circuits intégrés – immunité aux impulsions conduites" (ICIM-CPI – integrated circuit immunity model conducted pulse immunity).
Le présent document fournit:
- la description des éléments de macromodèle ICIM-CPI représentant le comportement électrique, thermique ou logique du circuit intégré;
- un format universel d'échange de données fondé sur le langage XML.

Modeliranje integriranih vezij (IC) za elektromagnetno združljivost (EMC) - 6. del: Modeli integriranih vezij za simulacijo impulzno odpornega obnašanja - Modeliranje impulzne odpornosti (ICIM-CPI) (IEC 62433-6:2020)

General Information

• Status: Published
• Publication Date: 17-Nov-2020
• ICS: 31.200 - Integrated circuits. Microelectronics
• ICS: 33.100.20 - Immunity
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 13-Nov-2020
• Due Date: 18-Jan-2021
• Completion Date: 18-Nov-2020
• Ref Project: EN IEC 62433-6:2020 - EMC IC modelling - Part 6: Models of integrated circuits for pulse immunity behavioural simulation - Conducted pulse immunity modelling (ICIM-CPI)

Standards Content (Sample)

SLOVENSKI STANDARD
SIST EN IEC 62433-6:2021
01-januar-2021
Modeliranje integriranih vezij (IC) za elektromagnetno združljivost (EMC) - 6. del:
Modeli integriranih vezij za simulacijo impulzno odpornega obnašanja -
Modeliranje impulzne odpornosti (ICIM-CPI) (IEC 62433-6:2020)
EMC IC modelling - Part 6: Models of integrated circuits for pulse immunity behavioural
simulation - Conducted pulse immunity modelling (ICIM-CPI) (IEC 62433-6:2020)
EMV-IC-Modellierung - Teil 6: Modelle integrierter Schaltungen für die Simulation des
Verhaltens bei Störfestigkeit gegen Impulse - Modellierung der Störfestigkeit gegen
leitungsgeführte Impulse (ICIM-CPI) (IEC 62433-6:2020)
Modèles de circuits intégrés pour la CEM - Partie 6: Modèles de circuits intégrés pour la
simulation du comportement d'immunité aux impulsions - Modélisation de l'immunité aux
impulsions conduite (ICIM-CPI) (IEC 62433-6:2020)
Ta slovenski standard je istoveten z: EN IEC 62433-6:2020
ICS:
31.200 Integrirana vezja, Integrated circuits.
mikroelektronika Microelectronics
33.100.20 Imunost Immunity
SIST EN IEC 62433-6:2021 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN IEC 62433-6:2021

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SIST EN IEC 62433-6:2021


EUROPEAN STANDARD EN IEC 62433-6

NORME EUROPÉENNE

EUROPÄISCHE NORM
November 2020
ICS 31.200

English Version
EMC IC modelling - Part 6: Models of integrated circuits for
Pulse immunity behavioural simulation - Conducted Pulse
Immunity (ICIM-CPI)
(IEC 62433-6:2020)
Modèles de circuits intégrés pour la CEM - Partie 6: EMV-IC-Modellierung - Teil 6: Modelle integrierter
Modèles de circuits intégrés pour la simulation du Schaltungen für die Simulation des Verhaltens bei
comportement d'immunité aux impulsions - Modélisation de Störfestigkeit gegen Impulse - Modellierung der
l'immunité aux impulsions conduites (ICIM-CPI) Störfestigkeit gegen leitungsgeführte Impulse (ICIM-CPI)
(IEC 62433-6:2020) (IEC 62433-6:2020)
This European Standard was approved by CENELEC on 2020-10-27. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Turkey and the United Kingdom.


European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2020 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
 Ref. No. EN IEC 62433-6:2020 E

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SIST EN IEC 62433-6:2021
EN IEC 62433-6:2020 (E)
European foreword
The text of document 47A/1090/CDV, future edition 1 of IEC 62433-6, prepared by SC 47A "Integrated
circuits" of IEC/TC 47 "Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and
approved by CENELEC as EN IEC 62433-6:2020.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2021-07-27
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2023-10-27
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Endorsement notice
The text of the International Standard IEC 62433-6:2020 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standards
indicated:
IEC 62433-2:2017 NOTE Harmonized as EN 62433-2:2017 (not modified)
CISPR 16-1-4:2019 NOTE Harmonized as EN IEC 55016-1-4:2019 (not modified)
CISPR 17 NOTE Harmonized as EN 55017
2

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SIST EN IEC 62433-6:2021
EN IEC 62433-6:2020 (E)
Annex ZA
(normative)

Normative references to international publications
with their corresponding European publications
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments)
applies.
NOTE 1 Where an International Publication has been modified by common modifications, indicated by (mod), the
relevant EN/HD applies.
NOTE 2 Up-to-date information on the latest versions of the European Standards listed in this annex is available
here: www.cenelec.eu.
Publication Year Title EN/HD Year
IEC 61000-4-2 - Electromagnetic compatibility (EMC) - EN 61000-4-2 -
Part 4-2: Testing and measurement
techniques - Electrostatic discharge
immunity test
IEC 61000-4-4 - Electromagnetic compatibility (EMC) - EN 61000-4-4 -
Part 4-4: Testing and measurement
techniques - Electrical fast transient/burst
immunity test
IEC 62215-3 - Integrated circuits - Measurement of EN 62215-3 -
impulse immunity - Part 3: Non-
synchronous transient injection method
IEC 62433-1 - EMC IC modelling - Part 1: General EN IEC 62433-1 -
modelling framework
IEC 62433-4 - EMC IC modelling - Part 4: Models of EN 62433-4 -
integrated circuits for RF immunity
behavioural simulation - Conducted
immunity modelling (ICIM-CI)
IEC 62615 - Electrostatic discharge sensitivity testing - - -
Transmission line pulse (TLP) -
Component level

3

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SIST EN IEC 62433-6:2021

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SIST EN IEC 62433-6:2021




IEC 62433-6

®


Edition 1.0 2020-09




INTERNATIONAL



STANDARD




NORME


INTERNATIONALE
colour

inside










EMC IC modelling –

Part 6: Models of integrated circuits for pulse immunity behavioural simulation –

Conducted pulse immunity modelling (ICIM-CPI)



Modèles de circuits intégrés pour la CEM –

Partie 6: Modèles de circuits intégrés pour la simulation du comportement


d'immunité aux impulsions – Modélisation de l'immunité aux impulsions

conduites (ICIM-CPI)












INTERNATIONAL

ELECTROTECHNICAL

COMMISSION


COMMISSION

ELECTROTECHNIQUE


INTERNATIONALE




ICS 31.200 ISBN 978-2-8322-8813-9




Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

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SIST EN IEC 62433-6:2021
– 2 – IEC 62433-6:2020 © IEC 2020
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms, definitions, abbreviated terms and conventions . 8
3.1 Terms and definitions . 8
3.2 Abbreviated terms . 11
3.3 Conventions . 11
4 Philosophy . 11
5 ICIM-CPI model structure . 12
5.1 General . 12
5.2 PPN . 14
5.2.1 Typical structure of a PPN . 14
5.2.2 PDN description . 15
5.2.3 NLB description . 16
5.3 FB description . 16
6 CPIML format . 18
6.1 General . 18
6.2 CPIML structure . 19
6.3 Global elements . 20
6.4 Header section . 20
6.5 Lead_definitions section . 20
6.6 Macromodels section . 21
6.7 Validity section . 22
6.8 PDN . 22
6.9 NLB . 22
6.9.1 General . 22
6.9.2 Attribute definitions . 23
6.9.3 Data description . 24
6.10 FB . 25
6.10.1 General . 25
6.10.2 Attribute definitions . 26
6.10.3 Data description . 30
Annex A (informative) Extraction of model components . 34
A.1 General . 34
A.2 PPN description . 34
A.3 PDN Extraction . 34
A.3.1 General . 34
A.3.2 S/Z/Y-parameter measurement . 34
A.3.3 Conventional one-port method . 35
A.3.4 Two-port method for low impedance measurement . 35
A.3.5 Two-port method for high impedance measurement . 36
A.4 NLB extraction . 36
A.4.1 General . 36
A.4.2 TLP test method . 37
A.5 FB extraction . 39
A.5.1 General . 39

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SIST EN IEC 62433-6:2021
IEC 62433-6:2020 © IEC 2020 – 3 –
A.5.2 Example of FB data in case of test criteria type = Class E_IC . 39
A.5.3 Example of FB data in case of test criteria type = Class C_IC . 41
Annex B (informative)  NLB implementation techniques in a circuit simulator . 42
B.1 General . 42
B.2 NLB modelling based on a R/I table . 42
B.3 NLB modelling based on a switch based model . 42
B.4 NLB modelling based on physical device model . 43
Annex C (informative)  Example of ICIM-CPI model . 45
C.1 General . 45
C.2 Example of Power switch ICIM-CPI model. 45
C.2.1 General . 45
C.2.2 CPImodel. 45
C.2.3 ICIM-CPI model use . 48
C.3 Example of 32-bit microcontroller ICIM-CPI model . 50
C.3.1 General . 50
C.3.2 CPImodel. 51
Bibliography . 54

Figure 1 – Structure of the ICIM-CPI model. 13
Figure 2 – Example of an ICIM-CPI model of an electronic board . 14
Figure 3 – Structure of a typical PPN . 15
Figure 4 – Characteristics of a voltage pulse entering the DI during a TLP test . 17
Figure 5 – Example of defect monitored at the OO when a disturbance
is applied to the DI . 18
Figure 6 – CPIML inheritance hierarchy . 19
Figure 7 – Example of a NLB external file . 25
Figure 8 – Example of an external FB file . 33
Figure A.1 – Conventional one-port S-parameters measurement . 35
Figure A.2 – Two-port method for low impedance measurement . 35
Figure A.3 – Two-port method for high impedance measurement . 36
Figure A.4 – Example of I/V measurements to extract NLB . 37
Figure A.5 – TLP method set-up (not powered IC) . 38
Figure A.6 – Example of NLB extraction using standard TLP pulse . 38
Figure A.7 – Graphs for identification of IC failure mechanism for destruction prediction . 40
Figure B.1 – NLB model based on a R/I table. 42
Figure B.2 – Example of a generic model architecture based on switches for NLB
behavioural modelling . 43
Figure B.3 – Example of core MOS large signal model of the GGNMOS . 43
Figure C.1 – Use of the ICIM-CPI model for simulation . 45
Figure C.2 – Power switch V/I curve for 50 ns-pulse width . 46
Figure C.3 – Power switch ICIM-CPI model . 46
Figure C.4 – Power switch ICIM-CPI model use for ESD protection design . 49
Figure C.5 – Calculated voltage at Power switch pin for different ESD protection

capacitor values . 49
Figure C.6 – Voltage at Power switch pin for fog lamp left and right sides . 50
Figure C.7 – Example of 32-bit microcontroller protection devices . 50

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SIST EN IEC 62433-6:2021
– 4 – IEC 62433-6:2020 © IEC 2020

Table 1 – Attributes of Lead tag in the Lead_definitions section . 20
Table 2 – Compatibility between the Mode and Type fields for correct CPIML
annotation . 21
Table 3 – Definition of the Lead tag for Nlb section . 22
Table 4 – Default values of Unit_voltage and Unit_current . 24
Table 5 – Allowed file extensions for Data_files . 24
Table 6 – Definition of the Lead tag in Fb section . 26
Table 7 – Table sub-attributes definition . 27
Table 8 – Pulse_characteristics parameters definition . 27
Table 9 – Test_criteria parameters definition . 28
Table A.1 – Example of FB data corresponding to Class E failure . 41
IC
Table A.2 – Example of FB data corresponding to Class C failure . 41
IC
Table C.1 – Synthesis Peak voltage and Energy for different pulse widths . 46

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SIST EN IEC 62433-6:2021
IEC 62433-6:2020 © IEC 2020 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

EMC IC MODELLING –

Part 6: Models of integrated circuits for pulse immunity behavioural
simulation – Conducted pulse immunity modelling (ICIM-CPI)

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
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4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
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5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62433-6 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this International Standard is based on the following documents:
CDV Report on voting
47A/1090/CDV 47A/1098/RVC

Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

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SIST EN IEC 62433-6:2021
– 6 – IEC 62433-6:2020 © IEC 2020
A list of all parts in the IEC 62433 series, published under the general title EMC IC modelling,
can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.

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SIST EN IEC 62433-6:2021
IEC 62433-6:2020 © IEC 2020 – 7 –
EMC IC MODELLING –

Part 6: Models of integrated circuits for pulse immunity behavioural
simulation – Conducted pulse immunity modelling (ICIM-CPI)



1 Scope
The objective of this part of IEC 62433 is to describe the extraction flow for deriving an
immunity macro-model of an Integrated Circuit (IC) against conducted Electrostatic Discharge
(ESD) according to IEC 61000-4-2 and Electrical Fast Transients (EFT) according to
IEC 61000-4-4.
The model addresses physical damages due to overvoltage, thermal damage and other failure
modes. Functional failures can also be addressed.
This model allows the immunity simulation of the IC in an application. This model is commonly
called "Integrated Circuit Immunity Model Conducted Pulse Immunity", ICIM-CPI.
The described approach is suitable for modelling analogue, digital and mixed-signal ICs.
Several terminals of an IC can be part of a single model (e.g. input, output and supply pins).
The implementation of the model is capable of representing the non-linear behaviour of
overvoltage protection circuits.
The model can be implemented for the use in different software tools for circuit simulation in
time-domain. The described modelling approach allows simulating device failure due to ESD
or EFT at component and system level considering all components necessary for the immunity
simulation of an IC, such as a PCB or external protection elements.
This document demonstrates, in detail, the construction of models in a defined XML-based
format which is suitable for the exchange of models without any deeper knowledge of the
semiconductor circuit. However, the model functionality can be implemented in different
1
formats including, but not limited to, tables, SPICE[1] netlists, hardware description
languages such as VHDL-AMS [2] and Verilog-AMS [3].
This document provides:
• the description of ICIM-CPI macro-model elements representing electrical, thermal or
logical behaviour of the IC.
• a universal data exchange format based on XML.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
IEC 61000-4-2, Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement
techniques – Electrostatic discharge immunity test
___________
1
 Numbers in square brackets refer to the bibliography.

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SIST EN IEC 62433-6:2021
– 8 – IEC 62433-6:2020 © IEC 2020
IEC 61000-4-4, Electromagnetic compatibility (EMC) – Part 4-4: Testing and measurement
techniques – Electrical fast transient/burst immunity test
IEC 62215-3, Integrated circuits – Measurement of impulse immunity – Part 3: Non-
synchronous transient injection method
IEC 62433-1, EMC IC modelling – Part 1: General modelling framework
IEC 62433-4:2016, EMC IC modelling – Part 4: Models of integrated circuits for RF immunity
behavioural simulation – Conducted immunity modelling (ICIM-CI)
IEC 62615, Electrostatic discharge sensitivity testing – Transmission line pulse (TLP) –
Component level
3 Terms, definitions, abbreviated terms and conventions
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• ISO Online browsing platform: available at http://www.iso.org/obp
• IEC Electropedia: available at http://www.electropedia.org/
3.1.1
pulse
abrupt variation of short duration of a physical quantity followed by a rapid return to the initial
value
Note 1 to entry: In this document, a pulse can be represented by a voltage or current quantity.
[SOURCE: IEC 60050-161:1990, 161-02-02, modified – Note 1 has been added.]
3.1.2
non-linear
qualifies a circuit (element) for which not all relations between the integral quantities are
linear
[SOURCE: IEC 60050-131:2002, 131-11-19]
3.1.3
network
set of ideal circuit elements and their interconnections, considered as a whole
[SOURCE: IEC 60050-131:2002, 131-13-03, modified – The words "in network topology" have
been removed at the beginning of the definition as well
...