SIST EN IEC 60191-1:2018
(Main)Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices (IEC 60191-1:2018)
Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices (IEC 60191-1:2018)
This part of IEC 60191 gives guidelines on the preparation of outline drawings of discrete
devices, including discrete surface-mounted semiconductor devices with lead count less than
8.
For the preparation of outline drawings of surface-mounted discrete devices with a lead count
higher or equal to 8, IEC 60191-6 should be referred to as well.
The primary object of these drawings is to indicate the space to be allowed for devices in
equipment, together with other dimensional characteristics required to ensure mechanical
interchangeability.
Complete interchangeability involves other considerations such as the electrical and thermal
characteristics of the semiconductor devices concerned.
The international standardization represented by these drawings therefore encourages the
manufacturers of devices to comply with the tolerances shown on the drawings in order to
extend their range of customers internationally. It also gives equipment designers an
assurance of mechanical interchangeability between the devices obtained from suppliers in
different countries, provided they allow the space in their equipment that is indicated by the
drawings and take note of the more precise information on bases, studs, etc.
NOTE Additional details of reference letter symbols used in this document are given in Annex A.
Mechanische Normung von Halbleiterbauelementen - Teil 1: Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von Einzelhalbleiterbauelementen (IEC 60191-1:2018)
Normalisation mécanique des dispositifs à semi-conducteurs - Partie 1: Règles générales pour la préparation des dessins d'encombrement des dispositifs discrets (IEC 60191-1:2018)
L’IEC 60191-1:2018 donne des lignes directrices pour la préparation des dessins d’encombrement des dispositifs discrets, comprenant les dispositifs discrets à semiconducteurs pour montage en surface dont le nombre de connexions est inférieur à 8.
Il convient également de se référer à l’IEC 60191-6 pour la préparation des dessins d’encombrement des dispositifs discrets pour montage en surface dont le nombre de connexions est supérieur ou égal à 8.
L’objectif principal de ces dessins consiste à indiquer l’espace à octroyer aux dispositifs dans un équipement, ainsi que d’autres caractéristiques dimensionnelles exigées pour assurer une interchangeabilité mécanique.
Cette édition inclut les modifications techniques majeures suivantes par rapport à l’édition précédente:
- le domaine d’application a été étendu pour couvrir les dispositifs à semiconducteurs pour montage en surface dont le nombre de connexions est inférieur à 8;
- une définition du terme "élévation" a été ajoutée;
- les méthodes de positionnement de la référence spécifiée ont été étendues pour englober les boîtiers des composants pour montage en surface (CMS);
- l’identification visuelle de la position de broche no 1, dans le cadre des procédures de manipulation automatique, a été clarifiée;
- les règles de représentation des broches ont été clarifiées;
- le Tableau A.1 a été complété avec des symboles spécifiquement destinés aux boîtiers CMS;
- l’Annexe B "Concept de normalisation" a été supprimée;
- une annexe normative avec des règles spécifiques aux boîtiers CMS a été ajoutée;
- les exemples de dessins de dispositifs à semiconducteurs ont été alignés sur l’état de l’art des boîtiers, en englobant les boîtiers CMS.
Standardizacija mehanskih lastnosti polprevodniških elementov - 1. del: Splošna pravila za pripravo tehničnih risb diskretnih elementov (IEC 60191-1:2018)
Ta del standarda IEC 60191 podaja smernice za pripravo tehničnih risb diskretnih elementov, vključno z diskretnimi površinsko nameščenimi polprevodniškimi elementi z manj kot 8 vodili.
Za pripravo tehničnih risb površinsko nameščenih diskretnih elementov z 8 ali več vodili se uporablja tudi standard IEC 60191-6.
Glavni cilj tehničnih risb je prikaz prostora, ki je namenjen elementom v opremi, ter drugih dimenzijskih lastnosti, ki so potrebne za zagotavljanje mehanske medsebojne zamenljivosti.
Za zagotavljanje popolne medsebojne zamenljivosti je treba upoštevati tudi druge dejavnike, kot so električne in toplotne lastnosti zadevnih polprevodniških elementov.
Mednarodna standardizacija, ki jo prikazujejo te risbe, spodbuja proizvajalce elementov k upoštevanju prikazanih toleranc na risbah, da lahko razširijo bazo svojih strank na mednarodni ravni. Prav tako pomeni zagotovilo razvijalcem opreme o mehanski medsebojni zamenljivosti elementov dobaviteljev iz različnih držav, če v svoji opremi namenijo prostor, kot je označeno na risbah, in upoštevajo podrobnejše informacije o podnožjih, stojnih vijakih itd.
OPOMBA: Dodatne podrobnosti glede referenčnih črkovnih oznak, ki se uporabljajo v tem dokumentu, so podane v dodatku A.
General Information
Relations
Standards Content (Sample)
SLOVENSKI STANDARD
SIST EN IEC 60191-1:2018
01-junij-2018
1DGRPHãþD
SIST EN 60191-1:2008
6WDQGDUGL]DFLMDPHKDQVNLKODVWQRVWLSROSUHYRGQLãNLKHOHPHQWRYGHO6SORãQD
SUDYLOD]DSULSUDYRWHKQLþQLKULVEGLVNUHWQLKHOHPHQWRY,(&
Mechanical standardization of semiconductor devices - Part 1: General rules for the
preparation of outline drawings of discrete devices (IEC 60191-1:2018)
Mechanische Normung von Halbleiterbauelementen - Teil 1: Allgemeine Regeln für die
Erstellung von Gehäusezeichnungen von Einzelhalbleiterbauelementen (IEC 60191-
1:2018)
Normalisation mécanique des dispositifs à semi-conducteurs - Partie 1: Règles
générales pour la préparation des dessins d'encombrement des dispositifs discrets (IEC
60191-1:2018)
Ta slovenski standard je istoveten z: EN IEC 60191-1:2018
ICS:
01.100.25 5LVEHVSRGURþMD Electrical and electronics
HOHNWURWHKQLNHLQHOHNWURQLNH engineering drawings
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
31.240 Mehanske konstrukcije za Mechanical structures for
elektronsko opremo electronic equipment
SIST EN IEC 60191-1:2018 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
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SIST EN IEC 60191-1:2018
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SIST EN IEC 60191-1:2018
EUROPEAN STANDARD EN IEC 60191-1
NORME EUROPÉENNE
EUROPÄISCHE NORM
March 2018
ICS 31.080.01 Supersedes EN 60191-1:2007
English Version
Mechanical standardization of semiconductor devices - Part 1:
General rules for the preparation of outline drawings of discrete
devices
(IEC 60191-1:2018)
Normalisation mécanique des dispositifs à semi- Mechanische Normung von Halbleiterbauelementen - Teil
conducteurs - Partie 1: Règles générales pour la 1: Allgemeine Regeln für die Erstellung von
préparation des dessins d'encombrement des dispositifs Gehäusezeichnungen von Einzelhalbleiterbauelementen
discrets (IEC 60191-1:2018)
(IEC 60191-1:2018)
This European Standard was approved by CENELEC on 2018-02-27. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden,
Switzerland, Turkey and the United Kingdom.
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2018 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 60191-1:2018 E
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SIST EN IEC 60191-1:2018
EN IEC 60191-1:2018 (E)
European foreword
The text of document 47D/886/CDV, future edition 3 of IEC 60191-1, prepared by IEC/SC 47D
"Semiconductor devices packaging, of IEC technical committee 47: Semiconductor devices" was
submitted to the IEC-CENELEC parallel vote and approved by CENELEC as EN IEC 60191-1:2018.
The following dates are fixed:
(dop) 2018-11-27
• latest date by which the document has to be
implemented at national level by
publication of an identical national
standard or by endorsement
• latest date by which the national (dow) 2021-02-27
standards conflicting with the
document have to be withdrawn
This document supersedes EN 60191-1:2007.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Endorsement notice
The text of the International Standard IEC 60191-1:2018 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standards indicated:
IEC 60191-6 (series) NOTE Harmonized as EN 60191-6 (series).
ISO 5459:2011 NOTE Harmonized as EN ISO 5459:2011 (not modified).
2
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SIST EN IEC 60191-1:2018
EN IEC 60191-1:2018 (E)
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments)
applies.
NOTE 1 Where an International Publication has been modified by common modifications, indicated by (mod), the relevant
EN/HD applies.
NOTE 2 Up-to-date information on the latest versions of the European Standards listed in this annex is available here:
www.cenelec.eu.
Publication Year Title EN/HD Year
IEC 60191-2 - Mechanical standardization of - -
semiconductor devices - Part 2:
Dimensions
IEC 60191-4 - Mechanical standardization of EN 60191-4 -
semiconductor devices - Part 4: Coding
system and classification into forms of
package outlines for semiconductor device
packages
IEC 60191-6-1 - Mechanical standardization of EN 60191-6-1 -
semiconductor devices - Part 6-1: General
rules for the preparation of outline
drawings of surface mounted
semiconductor device packages - Design
guide for gull-wing lead terminals
IEC 60191-6-3 - Mechanical standardization of EN 60191-6-3 -
semiconductor devices - Part 6-3: General
rules for the preparation of outline
drawings of surface mounted
semiconductor device packages -
Measuring methods for package
dimensions of quad flat packs (QFP)
IEC 60191-6-20 - Mechanical standardization of EN 60191-6-20 -
semiconductor devices - Part 6-20:
General rules for the preparation of outline
drawings of surface mounted
semiconductor device packages -
Measuring methods for package
dimensions of small outline J-lead
packages (SOJ)
IEC 60191-6-21 - Mechanical standardization of EN 60191-6-21 -
semiconductor devices - Part 6-21:
General rules for the preparation of outline
drawings of surface mounted
semiconductor device packages -
Measuring methods for package
dimensions of small outline packages
(SOP)
3
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SIST EN IEC 60191-1:2018
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SIST EN IEC 60191-1:2018
IEC 60191-1
®
Edition 3.0 2018-01
INTERNATIONAL
STANDARD
Mechanical standardization of semiconductor devices –
Part 1: General rules for the preparation of outline drawings of discrete devices
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.01 ISBN 978-2-8322-5266-6
Warning! Make sure that you obtained this publication from an authorized distributor.
® Registered trademark of the International Electrotechnical Commission
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– 2 – IEC 60191-1:2018 IEC 2018
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 7
4 General rules for all drawings . 8
4.1 Drawing layout . 8
4.2 Dimensions and tolerances . 9
4.3 Methods for locating the datum . 10
4.4 Numbering of terminals . 11
4.4.1 General . 11
4.4.2 Single-ended devices with terminals in a linear array . 11
4.4.3 Single-ended devices with terminals in a circular array . 11
4.4.4 Double-ended devices . 11
4.4.5 Devices with terminals disposed in a square or rectangular periphery . 11
4.4.6 Particular case of lozenge – shaped bases . 11
4.4.7 Other devices . 12
5 Additional rules . 12
5.1 Rules for device and case outline drawings . 12
5.2 Rules to specify the dimensions and positions of terminals . 13
5.2.1 General rules . 13
5.2.2 Rules to specify the dimensions and the positions of the terminals on a
base drawing . 13
5.3 Rules for gauge drawings . 13
6 Inter-conversion of inch and millimetre dimensions and rules for rounding off . 14
7 Rules for coding . 14
Annex A (informative) Reference letter symbols . 15
Annex B (informative) Rules to specify the dimensions and positions of terminals on a
base drawing . 18
B.1 Example of dimensioning for a circular base outline with no tab and having
four terminals located symmetrically on a pitch circle . 18
B.1.1 Interpretation of the principle of dimensioning . 18
B.1.2 Checking . 19
B.2 Example of dimensioning for a circular base outline with a tab and having
four terminals located symmetrically on a pitch circle . 19
B.2.1 Interpretation of the principle of dimensioning . 19
B.2.2 Checking . 20
Annex C (normative) General philosophy of flat base devices . 24
Annex D (normative) Special rules for SMD-packages . 26
D.1 General reference . 26
D.2 Lead terminals . 26
D.3 Measuring methods . 26
Annex E (informative) Examples of semiconductor device drawings . 27
Annex F (informative) Former rules for rounding off . 33
F.1 Toleranced dimensions . 33
F.1.1 Maximum and minimum values of toleranced dimensions . 33
F.1.2 Nominal value of toleranced dimensions . 33
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IEC 60191-1:2018 © IEC 2018 – 3 –
F.2 Untoleranced dimensions (maximum only or minimum only) . 33
F.3 Untoleranced nominal dimensions given for general information . 33
F.4 Untoleranced nominal dimensions given to specify true geometrical positions . 34
Annex G (informative) Former rules for coding . 35
G.1 General . 35
G.2 Device outlines . 35
G.3 Bases . 35
G.4 Case outlines . 35
G.5 Type variants and provisional drawings . 35
Bibliography . 36
Figure 1 – Numbering of terminals for the particular case of lozenge – shaped bases . 12
Figure 2 – System to indicate the dimensions of the terminals . 13
Figure B.1 – Circular base outline with no tab . 21
Figure B.2 – Tolerances of terminals. 21
Figure B.3 – Gauge for a circular base outline with no tab . 22
Figure B.4 – Circular base outline with tab . 22
Figure B.5 – Gauge for a circular base outline with tab . 23
Figure C.1 − Example of flat base outline . 25
Figure E.1 – Long form package . 27
Figure E.2 – Post/stud mount package . 27
Figure E.3 – Cylindric package . 28
Figure E.4 – Cylindric in-line package . 29
Figure E.5 – Flange-mounted in-line package . 29
Figure E.6 – Press package . 30
Figure E.7 – SMD-package with flat leads . 30
Figure E.8 – SMD-Package with gull-wing leads . 31
Figure E.9 – SMD-package with no leads . 32
Table A.1 – Dimensions of reference letter symbols . 15
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INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –
Part 1: General rules for the preparation of outline drawings
of discrete devices
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as "IEC
Publication(s)"). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-1 has been prepared by subcommittee 47D: Semiconductor
devices packaging, of IEC technical committee 47: Semiconductor devices.
This third edition cancels and replaces the second edition published in 2007. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) the Scope has been extended to include surface-mounted semiconductor devices with a
lead count less than 8;
b) a definition of the term "stand-off" has been added;
c) the methods for locating the datum have been extended to be suitable for SMD-packages;
d) the visual identification of terminal position one for automatic handling has been clarified;
e) the rules for the drawing of terminals have been clarified;
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SIST EN IEC 60191-1:2018
IEC 60191-1:2018 © IEC 2018 – 5 –
f) Table A.1 has been completed with symbols specifically for SMD-packages;
g) Annex B "Standardization philosophy" has been deleted;
h) a normative Annex with special rules for SMD-packages has been added;
i) the examples of semiconductor device drawings have been aligned to state-of-the-art
packages including SMD-packages.
The text of this standard is based on the following documents:
CDV Report on voting
47D/886/CDV 47D/896/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 60191 series, published under the general title Mechanical
standardization of semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.
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MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –
Part 1: General rules for the preparation of outline drawings
of discrete devices
1 Scope
This part of IEC 60191 gives guidelines on the preparation of outline drawings of discrete
devices, including discrete surface-mounted semiconductor devices with lead count less than
8.
For the preparation of outline drawings of surface-mounted discrete devices with a lead count
higher or equal to 8, IEC 60191-6 should be referred to as well.
The primary object of these drawings is to indicate the space to be allowed for devices in
equipment, together with other dimensional characteristics required to ensure mechanical
interchangeability.
Complete interchangeability involves other considerations such as the electrical and thermal
characteristics of the semiconductor devices concerned.
The international standardization represented by these drawings therefore encourages the
manufacturers of devices to comply with the tolerances shown on the drawings in order to
extend their range of customers internationally. It also gives equipment designers an
assurance of mechanical interchangeability between the devices obtained from suppliers in
different countries, provided they allow the space in their equipment that is indicated by the
drawings and take note of the more precise information on bases, studs, etc.
NOTE Additional details of reference letter symbols used in this document are given in Annex A.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
IEC 60191-2, Mechanical standardization of semiconductor devices – Part 2: Dimensions
IEC 60191-4, Mechanical standardization of semiconductor devices – Part 4: Coding system
and classification into forms of package outlines for semiconductor device packages
IEC 60191-6-1, Mechanical standardization of semiconductor devices – Part 6-1: General
rules for the preparation of outline drawings of surface mounted semiconductor device
packages – Design guide for gull-wing lead terminals
IEC 60191-6-3, Mechanical standardization of semiconductor devices – Part 6-3: General
rules for the preparation of outline drawings of surface mounted semiconductor device
packages – Measuring methods for package dimensions of quad flat packs (QFP)
IEC 60191-6-20, Mechanical standardization of semiconductor devices – Part 6-20: General
rules for the preparation of outline drawings of surface mounted semiconductor device
packages – Measuring methods for package dimensions of small outline J-lead packages
(SOJ)
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SIST EN IEC 60191-1:2018
IEC 60191-1:2018 © IEC 2018 – 7 –
IEC 60191-6-21, Mechanical standardization of semiconductor devices – Part 6-21: General
rules for the preparation of outline drawings of surface mounted semiconductor device
packages – Measuring methods for package dimensions of small outline packages (SOP)
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
device outline drawing
drawing that includes all dimensional characteristics required for the mechanical
interchangeability of the complete device
Note 1 to entry: The device outline drawing includes the case or body, all terminals and the locating tab if present.
3.2
terminal
part of the semiconductor device primarily used in making an electrical, mechanical or thermal
connection
EXAMPLE Flexible leads, rigid leads, pins, studs, etc.
3.3
case outline drawing
drawing that includes all dimensional characteristics required for the mechanical
interchangeability of the case or body
Note 1 to entry: The case outline drawing does not include the dimensions of the terminals or the locating tab if
present, but their positions are shown by dotted lines.
3.4
base drawing
drawing that includes all dimensional characteristics required for the mechanical
interchangeability of the terminals and mechanical index
Note 1 to entry: Examples of these characteristics are: lead length, lead diameters with controlled zones, lead
spacing, pitch circle diameter, thickness, width and length of a tab, etc.
Note 2 to entry: The diameter or major axis of the case outline should not be given on the base drawing.
Note 3 to entry: Many semiconductor devices have identical cases, but differ in the number or the length of
terminals. It is also possible to have the same type of base associated with cases that are not identical.
Consequently, there are advantages in having:
a) a single drawing including only the dimensional characteristics of the case outline and separate drawings for
the various bases which can be associated with this case outline,
or
b) a single drawing including only the dimensional characteristics of the base and separate drawings for the
various case outlines which can be associated with this base.
3.5
mechanical index
locating feature, or that portion of the device specifically designed to provide orientation
Note 1 to entry: Examples of a mechanical index are: key, keyway, locating tab, etc.
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3.6
visual index
any single terminal (or omission of) readily distinguished by the eye from others or any
distinctive boss, stippled pattern or colour mark adjacent to a terminal
3.7
datum
theoretically exact geometric reference (such as axes, planes, straight lines etc.) to which
toleranced features are related
Note 1 to entry: Datums may be based on one or more datum features of a part.
[SOURCE: ISO 5459:2011, 3.4]
3.8
seating plane
seating base
reference plane from which, in general, outline and base dimensions are given
3.9
seated height
mounted height
distance from the seating plane to the top of any exposed tip or rigid terminal present,
otherwise to the top of the outline
Note 1 to entry: Flexible terminals should not be included as part of the seated height, but the mounted height
should include a minimum allowance necessary for an axially mounted flexible lead to be bent at right angles.
3.10
controlled cylindrical zone
zone that defines a portion of the body of minimum length over which the diameter is
controlled to closer tolerances than is allowed over the full length of the body
3.11
stand-off
distance from the seating plane to the lowest point of a package
4 General rules for all drawings
4.1 Drawing layout
General rules for the drawing layout are as follows.
a) A drawing should show all dimensions required to ensure mechanical interchangeability.
b) The drawing using third angle projection, should include:
– a suitable side-view;
–
...
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