SIST EN 60749-29:2011
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
This part of IEC 60749 covers the I-test and the overvoltage latch-up testing of integrated circuits. This test is classified as destructive. The purpose of this test is to establish a method for determining integrated circuit (IC) latchup characteristics and to define latch-up failure criteria. Latch-up characteristics are used in determining product reliability and minimizing "no trouble found" (NTF) and "electrical overstress" (EOS) failures due to latch-up. This test method is primarily applicable to CMOS devices. Applicability to other technologies must be established. The classification of latch-up as a function of temperature is defined in 3.1 and the failure level criteria are defined in 3.2.
Halbleiterbauelemente - Mechanische und klimatische Prüfverfahren - Teil 29: Latch-up-Prüfung
Dispositifs à semiconducteurs - Méthodes d'essais mécaniques et climatiques - Partie 29: Essai de verrouillage
La CEI 60749-29:2011 couvre l'essai I et l'essai de verrouillage de surtension des circuits intégrés. L'objet de cet essai est d'établir une méthode pour déterminer les caractéristiques de verrouillage des circuits intégrés (CI) et pour définir les critères de défaillance de verrouillage. Les caractéristiques de verrouillage sont utilisées pour la détermination de la fiabilité de produit et la minimisation des défaillances en rapport avec 'l'absence d'observation de problèmes' (NTF, No Trouble Found) et la 'contrainte électrique excessive' (EOS, Electrical Overstress) dues au verrouillage. Cette deuxième édition annule et remplace la première édition publiée en 2003 et constitue une révision technique. Les modifications importantes apportées par rapport à l'édition antérieure concernent: - un certain nombre de modifications techniques mineures; - l'addition de deux nouvelles annexes traitant de l'essai des broches spéciales et des calculs de température.
Polprevodniški elementi - Mehanske in klimatske preskusne metode - 29. del: Preskus zapore
Ta del IEC 60749 zajema preskus I in prenapetostni preskus zapore integriranih vezij Ta preskus je klasificiran kot porušitveni. Namen tega preskusa je vzpostaviti metodo za določanje zapornih značilnosti integriranega vezja (IC) in opredeliti merila za neuspešnost zapore. Zaporne značilnosti se uporabljajo pri ugotavljanju zanesljivosti proizvoda in zmanjševanju napak zaradi zapore »Ne najdem težave« (NTF) in »Električna prenapetost« (EOS). Ta preskusna metoda se uporablja predvsem za elemente CMOS. Uporabnost za druge tehnologije je treba ugotoviti. Klasifikacija zapore kot funkcije temperature je opredeljena v 3.1, merila za stopnjo neuspešnosti pa v 3.2.
General Information
Relations
Standards Content (Sample)
SLOVENSKI STANDARD
SIST EN 60749-29:2011
01-oktober-2011
Polprevodniški elementi - Mehanske in klimatske preskusne metode - 29. del:
Preskus zapore
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
Dispositifs à semiconducteurs - Méthodes d'essais mécaniques et climatiques - Partie
29: Essai de verrouillage
Ta slovenski standard je istoveten z: EN 60749-29:2011
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
SIST EN 60749-29:2011 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
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SIST EN 60749-29:2011
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SIST EN 60749-29:2011
EUROPEAN STANDARD
EN 60749-29
NORME EUROPÉENNE
August 2011
EUROPÄISCHE NORM
ICS 31.080.01 Supersedes EN 60749-29:2003 + corr. Mar.2004
English version
Semiconductor devices -
Mechanical and climatic test methods -
Part 29: Latch-up test
(IEC 60749-29:2011)
Dispositifs à semiconducteurs - Halbleiterbauelemente -
Méthodes d'essai mécaniques et Mechanische und klimatische
climatiques - Prüfverfahren -
Partie 29: Essai de verrouillage Teil 29: Latch-up-Prüfung
(CEI 60749-29:2011) (IEC 60749-29:2011)
This European Standard was approved by CENELEC on 2011-05-12. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,
the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia,
Spain, Sweden, Switzerland and the United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Management Centre: Avenue Marnix 17, B - 1000 Brussels
© 2011 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60749-29:2011 E
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SIST EN 60749-29:2011
EN 60749-29:2011 - 2 -
Foreword
The text of document 47/2083/FDIS, future edition 2 of IEC 60749-29, prepared by IEC TC 47,
Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 60749-29 on 2011-05-12.
This European Standard supersedes EN 60749-29:2003 + corrigendum March 2004.
The significant changes with respect to EN 60749-29:2003 include:
– a number of minor technical changes;
– the addition of two new annexes covering the testing of special pins and temperature calculations.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent
rights.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
(dop) 2012-02-12
national standard or by endorsement
– latest date by which the national standards conflicting
(dow) 2014-05-12
with the EN have to be withdrawn
__________
Endorsement notice
The text of the International Standard IEC 60749-29:2011 was approved by CENELEC as a European
Standard without any modification.
__________
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SIST EN 60749-29:2011
IEC 60749-29
®
Edition 2.0 2011-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Mechanical and climatic test methods –
Part 29: Latch-up test
Dispositifs à semiconducteurs – Méthodes d'essai mécaniques et climatiques –
Partie 29: Essai de verrouillage
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX T
ICS 31.080.01 ISBN 978-2-88912-434-3
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
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SIST EN 60749-29:2011
– 2 – 60749-29 IEC:2011
CONTENTS
FOREWORD . 3
1 Scope and object . 5
2 Terms and definitions . 5
3 Classification and levels . 8
3.1 Classification . 8
3.2 Levels . 8
4 Apparatus and material . 8
4.1 Latch-up tester . 8
4.1.1 General . 8
4.1.2 V and their qualification method. 9
supply
4.1.3 Trigger source qualification method . 9
4.2 Automated test equipment (ATE) . 10
4.3 Heat source . 10
5 Procedure . 10
5.1 General latch-up test procedure . 10
5.2 Detailed latch-up test procedure . 13
5.2.1 I-test . 13
5.2.2 V overvoltage test . 17
supply
5.2.3 Testing dynamic devices . 19
5.2.4 DUT disposition . 19
5.2.5 Record keeping . 19
6 Failure criteria . 20
7 Summary . 20
Annex A (informative) Examples of special pins that are connected to passive
components . 21
Annex B (informative) Calculation of operating ambient or operating case temperature
for a given operating junction temperature . 23
qualification circuit . 9
Figure 1 – V
supply
Figure 2 – Trigger source qualification circuit . 10
Figure 3 – Latch-up test flow . 11
Figure 4 – Test waveform for positive I-test . 14
Figure 5 – Test waveform for negative I-test . 15
Figure 6 – Equivalent circuit for positive input/output I-test latch-up testing . 16
Figure 7 – Equivalent circuit for negative input/output I-test latch-up testing . 17
Figure 8 – Test waveform for V overvoltage . 18
supply
Figure 9 – Equivalent circuit for V overvoltage test latch-up testing . 19
supply
Figure A.1 – Examples of special pins that are connected to passive components . 22
a
Table 1 – Test matrix . 12
Table 2 – Timing specifications for I-test and V overvoltage test . 13
supply
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SIST EN 60749-29:2011
60749-29 IEC:2011 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 29: Latch-up test
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
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Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60749-29 has been prepared by IEC technical committee 47:
Semiconductor devices.
This second edition cancels and replaces the first edition published in 2003 and constitutes a
technical revision. The significant changes with respect to the previous edition include:
– a number of minor technical changes;
– the addition of two new annexes covering the testing of special pins and temperature
calculations.
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SIST EN 60749-29:2011
– 4 – 60749-29 IEC:2011
The text of this standard is based on the following documents:
FDIS Report on voting
47/2083/FDIS 47/2090/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 60749 series, under the general title Semiconductor devices –
Mechanical and climatic test methods, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
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SIST EN 60749-29:2011
60749-29 IEC:2011 – 5 –
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 29: Latch-up test
1 Scope and object
This part of IEC 60749 covers the I-test and the overvoltage latch-up testing of integrated
circuits.
This test is classified as destructive.
The purpose of this test is to establish a method for determining integrated circuit (IC) latch-
up characteristics and to define latch-up failure criteria. Latch-up characteristics are used in
determining product reliability and minimizing "no trouble found" (NTF) and "electrical
overstress" (EOS) failures due to latch-up.
This test method is primarily applicable to CMOS devices. Applicability to other technologies
must be established.
The classification of latch-up as a function of temperature is defined in 3.1 and the failure
level criteria are defined in 3.2
2 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
2.1
cool-down time
period of time between successive applications of trigger pulses or the period of time between
the removal of the V voltage and the application of the next trigger pulse (See Figures 4,
supply
5, and 8 and Table 2.)
2.2
device under test
DUT
semiconductor product subjected to latch-up test
2.3
ground
GND
common or zero-potential pin(s) of the DUT
NOTE 1 Ground pins are not latch-up tested.
NOTE 2 A ground pin is sometimes called V .
ss
2.4
input pins
all address, data-in control, V and similar pins
ref
2.5
I/O (bi-directional) pins
device pins that can be made to operate as an input or output or in a high-impedance state
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SIST EN 60749-29:2011
– 6 – 60749-29 IEC:2011
2.6
I
supply
total supply current in each V pin (or pin group) with the DUT biased as indicated in
supply
Table 1
2.7
I-test
latch-up test that supplies positive and negative current pulses to the pin under test
2.8
latch-up
state in which a low-impedance path resulting from an overstress that triggers a parasitic
thyristor structure, persists after removal or cessation of the triggering condition
NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or
any other abnormal condition that causes the parasitic thyristor structure to become regenerative.
NOTE 2 Latch-up will not damage the device provided that the current through the low-impedance path is
sufficiently limited in magnitude or duration.
2.9
logic-high
level within the more positive (less negative) of the two ranges of logic levels chosen to
represent the logic states
NOTE 1 For digital devices, a voltage level equal to V is used for latch-up testing, except where otherwise
supply
specified in the relevant specification.
NOTE 2 For non-digital devices, V voltage level or the maximum operating voltage that can be applied to that
supply
pin as defined in the relevant specification may be used for latch-up testing.
2.10
logic-low
level within the more negative (less positive) of the two ranges of logic levels chosen to
represent the logic states
NOTE 1 For digital devices, ground voltage level is used for latch-up testing, except where specified in the
relevant specification.
NOTE 2 For non-digital devices, ground voltage level or the minimum operating voltage that can be applied to that
pin as defined in the relevant specification may be used for latch-up testing.
2.11
maximum V
supply
maximum operating voltage for operation within performance specifications
NOTE 1 The maximum voltage is not the absolute maximum voltage beyond which permanent damage is likely.
NOTE 2 Maximum refers to the magnitude of V and can be either positive or negative.
supply
2.12
no connect pin
pin that has no internal connection and that can be used as a support for external wiring
without disturbing the function of the device
NOTE All “no connect” pins should be left in an open (floating) state during latch-up testing.
2.13
nominal I (I )
supply nom
measured dc supply current for each V pin (or pin group) with the DUT biased at the test
supply
temperature as defined in Clause 5 and Table 1
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SIST EN 60749-29:2011
60749-29 IEC:2011 – 7 –
2.14
output pin
device pin that generates a signal or voltage level as a normal function during the normal
operation of the device
NOTE Output pins, though left in an open (floating) state during testing of other pin types, are latch-up tested.
2.15
preconditioned pin
device pin that has been placed in a defined state or condition (input, output, high impedance,
etc.) by applying control vectors to the DUT
2.16
testing of dynamic devices
latch-up trigger testing of a device in a known stable state, at the minimum-rated clock
frequency applied to the device (see 5.2.3 for specified conditions)
2.17
test condition
test temperature, supply voltage, current limits, voltage limits, clock frequency, input bias
voltages, and preconditioning vectors applied to the DUT during the latch-up test
2.18
timing-related input pin
pin such as clock crystal oscillator, charge pump circuit, etc., required to place the DUT in a
normal operating mode
NOTE Required timing signals may be applied by the latch-up tester, external equipment, and/or external
components as appropriate.
2.19
trigger pulse
positive or negative current pulse (I-Test) or voltage pulse (V overvoltage test) applied to
supply
any pin under test in an attempt to induce latch-up (see Figures 4, 5 and 8)
2.20
trigger duration
duration of an applied pulse from the trigger source (see Figures 4, 5 and 8 and Table 2)
2.21
pin (or pin group)
V
supply
all DUT power supply and external voltage source pins (excluding ground pins), including both
positive- and negative-potential pins
NOTE 1 Generally, it is permissible to treat equal potential voltage source pins as one V pin (or pin group)
supply
and connect them to one power supply.
NOTE 2 When forming V pins (or pin groups), the combination of V pins with significantly different
supply supply
supply current levels is not recommended as this would make it difficult to detect significant current changes on
low supply current pins.
2.22
V overvoltage test
supply
latch-up test that supplies overvoltage pulses or overvoltage d.c. level to the V pin under
supply
test
2.23
V voltage level
supply
applicable voltage level of the V pin specified in the relevant specification. The V
supply supply
voltage level is used for latch-up testing as the typical logic high level unless otherwise
specified (see 2.9)
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SIST EN 60749-29:2011
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2.24
ground voltage level
ground potential used for latch-up testing as the typical logic low level, unless otherwise
specified (see 2.10)
3 Classification and levels
3.1 Classification
There are two classes for latch-up testing.
• Class I is for testing at room temperature ambient.
• Class II is for testing at the maximum operating ambient temperature (T ) or maximum
a
operating case temperature (T ) or maximum operating junction temperature (T) in the
c j
detailed specification.
For Class II testing at the maximum operating T or T , the ambient temperature or case
a c
temperature (T ) shall be established at the required test value. For Class II testing at the
c
maximum operating T, the ambient temperature T or the case temperature T should be
j a c
selected to achieve a temperature characteristic of the junction temperature for a given device
operating mode(s) during latch-up testing. The maximum operating ambient or case
temperature during stress may be calculated based on the methods detailed in Annex B.
NOTE Elevated temperature will reduce latch-up resistance, and class II testing is recommended for devices that
are required to operate at elevated temperature.
3.2 Levels
Level defines the I-test current injection value used during latch-up testing. Latch-up passing
levels are defined as follows:
Level A – The trigger current value in Table 1 shall be +100 mA as defined in Figure 6 and -
100 mA as defined in Figure 7. If all pins on the part pass at least the Level A trigger current
values, then the part shall be considered a Level A part.
Level B – If any pins on the part do not pass the Level A standard, then the supplier shall
determine the minimum passing trigger current requirement for each pin stressed differently
than in Level A. The maximum (or highest) passing trigger current value shall be reported in
the record for each pin stressed differently than in Level A, and the part shall be considered to
be a Level B part, see 5.2.5.
4 Apparatus and material
The apparatus required for this test method includes the following.
4.1 Latch-up tester
4.1.1 General
Test equipment capable of performing the tests as specified in this standard. For devices
requiring dynamic testing, the test equipment shall be capable of supplying timing signals and
logic setup vectors required to control the I/O pin output states as specified in 5.2.3. The
required timing signals and logic vectors may be applied by the latch-up tester itself, external
equipment, and/or external components as appropriate.
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SIST EN 60749-29:2011
60749-29 IEC:2011 – 9 –
4.1.2 V and their qualification method
supply
For the I-test, sink type voltage power supplies shall be connected to all V pins as shown
supply
in Figure 6 and Figure 7, and the transient characteristics shall be qualified as shown in
Figure 1. The qualification steps are as follows:
a) Connect the supply voltage (e.g. 5 V, 3,3 V) to the V pin. The value of voltage may
supply
be specified in the relevant specification.
b) Apply positive and negative pulses from the 200 mA trigger source, and measure their
effect on the voltage waveform shown on the oscilloscope.
c) The voltage measured by the oscilloscope shall be within 90 % to 110 % of the supply
voltage.
I
source
V pin
supply
Trigger source
Voltage
R
probe
+
Pin under test
V 1
supply
DUT socket
or equivalent
–
To oscilloscope
GND pin
Value of R (e.g. 50 Ω) is specified in the applicable procurement document.
Input impedance of voltage probe and oscilloscope is over 10 kΩ.
IEC 671/11
Figure 1 – V qualification circuit
supply
4.1.3 Trigger source qualification method
The electrical characteristics of the trigger source including its transient characteristics shall
be qualified as shown in Figure 2. The qualification steps are as follows:
a) With switch S1 closed, apply positive and negative pulses from the 200 mA trigger source,
and measure its current waveform. The current waveform shall satisfy the requirements of
Table 1.
b) After setting the voltage clamp level and opening S1, apply positive and negative pulses
from the 100 mA trigger source and measure its voltage waveform. The voltage waveform
during the working voltage clamp shall be within 90 % to 110 % of the voltage clamp
setting level.
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SIST EN 60749-29:2011
– 10 – 60749-29 IEC:2011
Trigger source
Voltage
probe
DUT socket
or equivalent
S1
Pin of DUT socket
R
To oscilloscope
GND pin
Value of R (e.g. 50 Ω) is specified in the applicable specification.
Input impedance of voltage probe and oscilloscope is over 10 kΩ.
IEC 672/11
Figure 2 – Trigger source qualification circuit
4.2 Automated test equipment (ATE)
A device tester capable of performing full functional and parametric testing of the device
specified in the relevant specification.
4.3 Heat source
Equipment capable of heating and maintaining the DUT at the maximum operating
temperature specified in the relevant specification during the latch-up test.
5 Procedure
5.1 General latch-up test procedure
Prior to the latch-up test, the device needs to be in a stable state with reproducible I .
nom
Engineering judgment may be needed to achieve sufficient stability. The supply current should
be made as low as practicable. The supply current must be stable enough and low enough to
reliably detect the supply current increase if latch-up occurs.
A sample group of devices (e.g. six) shall be subjected to latch-up testing using the I-test and
V overvoltage test. The use of a new sample group for each latch-up test type (I-test,
supply
and/or V overvoltage test) is also acceptable. All devices to be latch-up tested shall have
supply
passed the specified functional and parametric testing.
Before latch-up testing, the device continuity in the socket should be checked to avoid false
latch-up failures. The latch-up test flow shall be as shown in Figure 3. The devices to be
tested shall be subjected to the test conditions specified in Table 1 and Table 2. All “no
connect” pins on the DUT shall be left open (floating) at all times.
All pins on the DUT, with the exception of “no connect” pins and timing related pins, shall be
latch-up tested. The input, output and configurable I/O pins shall be tested with the I-test and
the V pins tested with the overvoltage test. This includes special pins defined in Annex A.
supply
The passing current or voltage values for the special pins can be used for determining the
values of the passive-components connected to the pins. I/O pins shall be tested in all
possible operating states or the worst case operating state (typically high impedance for
configurable I/O pins and output pins).
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SIST EN 60749-29:2011
60749-29 IEC:2011 – 11 –
Dynamic devices shall be tested according to 5.2.3. When a device is sufficiently complex that
testing of all configurable I/O pins in the worst case condition is not practicable, the device
should be conditioned with a set of vectors representative of the typical operation of the
device as determined by engineering judgement. When an I/O pin cannot be tested in the high
impedance state, the I/O shall be tested in a valid logic state. Untested pins and pins that
could not be completely tested shall be recorded as specified in 5.2.5 and the user shall be
informed of all I/O pins that were not tested or tested in all states. After latch-up testing, all
devices shall pass the criteria specified in Clause 6.
ATE test devices to be
latch-up tested
DUT
I-test
Fail Device failed
latch-up test*
Pass
V overvoltage
supply
test
Device failed Fail
latch-up test*
Pass
ATE test devices
after latch-up test
Reduce trigger
Fail
current until pass
Device passed
latch-up test
* Change in I exceeds failure criteria in 3.2
supply
IEC 673/11
Figure 3 – Latch-up test flow
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SIST EN 60749-29:2011
– 12 – 60749-29 IEC:2011
a
Table 1 – Test matrix
Condition
Test
of Trigger
V
Test Trigger supply Failure
temperature
untested test
fg
type polarity criteria
g
condition
input pins conditions
(±2°C)
b
Max logic
Positive According to
high
see classification
d
Min logic
Figure 6 levels in 3.
...
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