oSIST prEN IEC 63550-3:2025

Semiconductor devices - Neuromorphic devices - Part 3: Evaluation method of spike dependent plasticity in memristor devices

Halbleiterbauelemente – Neuromorphe Bauelemente –Teil 3: Bewertungsmethode für spikeabhängige Plastizität in Memristor-Bauelementen

Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 3: Méthode d’évaluation de la plasticité dépendant de la temporisation des impulsions pré- Et postsynaptiques dans les dispositifs à memristance

Polprevodniški elementi - Nevromorfne naprave - 3. del: Metoda ocenjevanja od konic odvisne plastičnosti v memristorskih napravah

General Information

• Status: Not Published
• Public Enquiry End Date: 27-Nov-2025
• ICS: 31.080.99 - Other semiconductor devices
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 4020 - Public enquire (PE) (Adopted Project)
• Start Date: 10-Sep-2025
• Due Date: 28-Jan-2026
• Completion Date: 19-Nov-2025
• Ref Project: prEN IEC 63550-3:2025 - Semiconductor devices - Neuromorphic devices - Part 3: Evaluation method of spike dependent plasticity in memristor devices

Standards Content (Sample)

SLOVENSKI STANDARD
01-november-2025
Polprevodniški elementi - Nevromorfne naprave - 3. del: Metoda ocenjevanja od
konic odvisne plastičnosti v memristorskih napravah
Semiconductor devices - Neuromorphic devices - Part 3: Evaluation method of spike
dependent plasticity in memristor devices
Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 3: Méthode
d’évaluation de la plasticité dépendant de la temporisation des impulsions pré- Et
postsynaptiques dans les dispositifs à memristance
Ta slovenski standard je istoveten z: prEN IEC 63550-3:2025
ICS:
31.080.99 Drugi polprevodniški elementi Other semiconductor devices
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47/2941/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 63550-3 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2025-09-05 2025-11-28
SUPERSEDES DOCUMENTS:
47/2876/CD, 47/2927/CC
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

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TITLE:
Semiconductor devices - Neuromorphic devices - Part 3: Evaluation method of spike
dependent plasticity in memristor devices

PROPOSED STABILITY DATE: 2029
NOTE FROM TC/SC OFFICERS:
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IEC CDV 63550-3 © IEC:2025
1 CONTENTS
3 FOREWORD . 4
4 1 Scope . 6
5 2 Normative references . 6
6 3 Terms and definitions . 6
7 4 Device under testing (DUT) . 8
8 4.1 General . 8
9 5 Test method . 9
10 5.1 General . 9
11 5.2 Test equipment and tools . 9
12 5.2.1 Spike time dependent plasticity (STDP) . 9
13 5.2.2 Indirect Spike time dependent plasticity (Indirect STDP) . 13
14 5.2.3 Spike rate dependent plasticity (SRDP) . 15
15 6 Test Report . 18
16 Annex A (informative) . 19
17 A.1 Synaptic plasticity network between presynaptic and postsynaptic neuron . 19
18 A.2 Hebbian and Anti-Hebbian synaptic plasticity . 20
19 A.3 Representative examples of STDP measurement . 21
20 A.4 Retention characteristics in synaptic plasticity . 22
21 A.5 Spike rate dependent synaptic plasticity (SRDP) characteristics . 23
23 Figure 1 – a) Schematic of memristor device. b) Equivalent circuit of a memristor
24 device . 8
25 Figure 2 – Block diagram of the measurement setup of a memristor device . 9
26 Figure 3 – (a) Circuit diagram for STDP process (b) Voltage-time graph to exhibit the
27 STDP operation of a memristor device . 11
28 Figure 4 – stimulation test flow chart of the STDP operation of a memristor device . 11
29 Figure 5 – Synaptic weight changes-spike timing graph of STDP according to inset
30 timing scheme . 12
31 Figure 6 – Stimulation test flow chart of the STDP retention of memristor device when
32 (a) Δt > 0 (potentiation) and (b) Δt < 0 (depression) . 13
33 Figure 7 – STDP retention measurement of a memristor device when (a) Δt > 0
34 (potentiation) and (b) Δt < 0 (depression) of selected Δt state . 13
35 Figure 8 – (a) Circuit diagram of indirect STDP process (b) Voltage-time graph to
36 exhibit the indirect STDP operation of a memristor device (c) Change in a synaptic
37 weight-spike timing graph of indirect STDP according to inset voltage scheme . 14
38 Figure 9 – Stimulation test flow chart of the indirect STDP of a memristor device when
39 (a) V > 0 (potentiation) and (b) V < 0 (depression) . 15
40 Figure 10 – Indirect STDP retention measurement of memristor device when (a) V > 0
41 (potentiation) and (b) V < 0 (depression) of selected Δt state . 15
42 Figure 11 – (a) Circuit diagram in SRDP process (b) Voltage-time graph to exhibit the
43 SRDP operation of memristor device . 16
44 Figure 12 – Stimulation test flow chart of the SRDP operation of memristor device . 17
45 Figure 13 – (a) Change in synaptic weight-spike frequency graph of SRDP (b) SRDP
46 retention measurement of a memristor device of a selected frequency state . 18
IEC CDV 63550-3 © IEC:2025
47 Figure A.1 –Schematic of synaptic plasticity between presynaptic and postsynaptic
48 neuron . 19
49 Figure A.2 – Hebbian STDP and anti-Hebbian STDP observed in the biological neural
50 system. Synaptic plasticity shall be modulated based on the relative timing of pre - and
51 postsynaptic spike. . 20
52 Figure A.3 – STDP shall be exhibited by applying input voltage spikes at relative timing
53 intervals (Δt) to each pre- and post-synaptic neuron. . 21
54 Figure A.4 – Examples of retention characteristics for each of potentiation and
55 depression in STDP . 22
56 Figure A.5 – Examples of retention characteristics for each of potentiation and
57 depression in STDP . 23
IEC CDV 63550-3 © IEC:2025
60 INTERNATIONAL ELECTROTECHNICAL COMMISSION
61 ____________
63  Semiconductor devices - Neuromorphic devices -
65 Part 3: Evaluation method of spike dependent plasticity in memristor
66 devices
70 FOREWORD
71 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
72 all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
73 co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
74 in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
75 Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their
76 preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
77 may participate in this preparatory work. International, governmental and non-governmental organizations liaising
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79 Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
80 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
81 consensus of opinion on the relevant subjects since each technical committee has representation from all
82 interested IEC National Committees.
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87 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
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89 any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
90 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
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97 expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
98 Publications.
99 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
100 indispensable for the correct application of this publication.
101 9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
102 patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
103 respect thereof. As of the date of publication of this document, IEC had not received notice of (a) patent(s), which
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105 the latest information, which may be obtained from the patent database available at https://patents.iec.ch. IEC
106 shall not be held responsible for identifying any or all such patent rights.
107 International Standard IEC 62951-X has been prepared by technical committee 47:
108 Semiconductor devices.
109 The text of this International Standard is based on the following documents:
NP Report on voting
47/XX/NP 47/XX/NP
IEC CDV 63550-3 © IEC:2025
111 Full information on the voting for the approval of this standard can be found in the report on
112 voting indicated in the above table.
113 The language used for the development of this International Standard is English.
114 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
115 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, and the
116 ISO/IEC Directives, JTC 1 Supplement available at www.iec.ch/members_experts/refdocs. The
117 main document types developed by IEC are described in greater detail at
118 www.iec.ch/publications.
119 The committee has decided that the contents of this publication will remain unchanged until the
120 stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data related to
121 the specific publication. At this date, the publication will be
122 • reconfirmed,
123 • withdrawn,
124 • replaced by a revised edition, or
125 • amended.
IEC CDV 63550-3 © IEC:2025
127 Semiconductor devices - Neuromorphic devices -
129 Part 3: Evaluation method of spike dependent plasticity in memristor
130 devices
132 1 Scope
133 This part of IEC63550-3 specifies the test methods for evaluating the spike dependent plasticity
134 of neuromorphic memristor devices. The test methods in this international standard include
135 spike time dependent plasticity (STDP), indirect STDP, spike rate dependent plasticity (SRDP),
136 and their retention properties. This document can be applicable to neuromorphic memristor
137 devices without any limitations prone to device technology and size.
138 2 Normative references
139 The following documents are referred to in the text in such a way that some or all of their content
140 constitutes requirements of this document. For dated references, only the edition cited applies.
141 For undated references, the latest edition of the referenced document (including any
142 amendments) applies.
143 IEC 62951-9:2022 Semiconductor devices - Flexible and stretchable semiconductor devices
144 Part 9: Performance testing methods of one transistor and one resistor (1T1R) resistive memory
145 cells
146 3 Terms and definitions
147 For the purpose of this document, the following terms and definitions apply.
148 ISO and IEC maintain terminological databases for use in standardization at the following
149 addresses:
150 • IEC Electropedia: available at http://www.electropedia.org/
151 • ISO Online browsing platform: available at http://www.iso.org/obp
153 3.1
154 pre-synaptic voltage
155 V
pre
156 bias applied to the pre-synaptic terminal of the memristor devices [SOURCE: IEC 63550-1:XXX,3.14]
157 3.2
158 post-synaptic voltage
159 V
post
160 bias applied to the post-synaptic terminal of the memristor devices [SOURCE: IEC 63550-
161 1:XXX,3.14]
162 3.3
163 memristor
164 nonlinear two-terminal electrical component that limits or regulate the flow of electrical current
165 in a circuit and remembers the amount of charge that has previously flowed through it [SOURCE:
166 IEC 63550-1:XXX,3.14]
167 3.4
168 forming voltage
169 V
form
170 high voltage applied across the active layer to induce defects within the active layer to form a filament
171 or conduction path initially [SOURCE: IEC 63550-1:XXX,3.14]
IEC CDV 63550-3 © IEC:2025
172 3.5
173 memristor program voltage
174 VP
175 voltage applied to the pre-synaptic terminal of memristor to change its resistance state
176 [SOURCE: IEC 63550-1:XXX,3.14]
177 3.6
178 step voltage
179 V
Step
180 step size of voltage increments during gradual voltage application [SOURCE: IEC 63550-
181 1:XXX,3.14]
182 3.7
183 read voltage
184 VRead
185 specific voltage for measuring the resistance of memristor [SOURCE: IEC 63550-1:XXX,3.14]
186 3.8
187 read current
188 IRead
189 specific current value at VRead of memristor [SOURCE: IEC 63550-1:XXX,3.14]
190 3.9
191 resistance of memristor
192 R
Read
193 resistance value at VRead, defined by the following formula [SOURCE: IEC 63550-1:XXX,3.14]
𝑽
𝐑𝐞𝐚𝐝
𝑹 =
𝑅𝑒𝑎𝑑
𝑰
𝐑𝐞𝐚𝐝
194 3.10
195 conductance of memristor
196 G
Read
197 conductance value at VRead, defined by the following formula [SOURCE: IEC 63550-1:XXX,3.14]
𝑰
𝐑𝐞𝐚𝐝
𝑮 =
𝐑𝐞𝐚𝐝
𝑽
𝐑𝐞𝐚𝐝
198 3.11
199 potentiation
200 increase in conductance (synaptic weights) depending on applied voltages over time [SOURCE: IEC
201 63550-1:XXX,3.14]
202 3.12
203 depression
204 decrease in conductance (synaptic weights) depending on applied voltages over time [SOURCE: IEC
205 63550-1:XXX,3.15]
206 3.13
207 potentiation voltage
208 VPo
209 voltage required to increase the conductance of the memristor after forming process [SOURCE:
210 IEC 63550-2:XXX,3.3]
211 3.14
212 depression voltage
213 VDe
214 voltage required to switch to decrease the conductance of the memristor [SOURCE: IEC 63550-
215 2:XXX,3.4]
IEC CDV 63550-3 © IEC:2025
216 3.15
217 potentiation time
218 t
Po
219 time required to increase the conductance of memristor [SOURCE: IEC 63550-2:XXX,3.5]
220 3.16
221 depression time
222 tDe
223 time required to decrease the conductance of memristor [SOURCE: IEC 63550-2:XXX,3.6]
224 3.17
225 pulse width
226 tR
227 elapsed time between the rise and fall of a single pulse.
228 3.18
229 pulse interval
230 △t
231 time interval between the falling edge of the first pulse and the rising edge of the second pulse
232 of two consecutive pulses [SOURCE: IEC 63550-1:XXX,3.16]
233 3.19
234 synaptic weight
235 W
236 scalar value determining the influence of a presynaptic neuron on a postsynaptic neuron
237 [SOURCE: IEC 63550-1:XXX,3.17]
238 3.20
239 synaptic Plasticity
240 synaptic plasticity is a property dependent modification of the strength of synaptic weights by
241 stimuli [SOURCE: IEC 63550-1:XXX,3.18]
243 4 Device under testing (DUT)General
244 The equivalent circuit diagram and schematic structure of 2-terminal memristor devices (DUT)
245 is shown in Figure 1. The top and bottom electrode of the memristor can be defined as terminal
246 Vpre and Vpost and vice versa. Different voltage biases are applied to each terminal during
247 forming, potentiation and depression operations. For some devices, the forming operation is
248 not required. [SOURCE: IEC 63550-1:XXX,4.1]
250 (a)                                  (b)
251 Figure 1 – a) Schematic of memristor device. b) Equivalent circuit of a memristor device
IEC CDV 63550-3 © IEC:2025
252 5 Test method
253 5.1 General
254 Test procedures for memristor device are performed as shown in Figure 2. First, memristor
255 device (DUT) shall be mounted on a test fixture and its electrical characteristics are measured
256 by varying voltage and current. For measuring and characterizing these devices accurately,
257 ultra-high accuracy sensors must be employed.
258 5.2 Test equipment and tools
259 A variety of experimental approaches have been
...