SIST EN 62374:2008

Semiconductor devices - Time Dependent Dielectric Breakdown (TDDB) test for gate dielectric films

This International Standard provides a test method of Time Dependent Dielectric Breakdown (TDDB) for gate dielectric films on semiconductor devices and a product lifetime estimation method of TDDB failure.

Halbleiterbauelemente - Prüfung des zeitabhängigen dielektrischen Durchbruchs (TDDB) für dielektrische Gate-Schichten

Dispositifs à semiconductors - Essai de rupture diélectrique en fonction du temps (TDDB) pour films diélectriques de grille

Cette norme décrit une méthode d essai de la rupture diélectrique en fonction du temps (TDDB) pour films diélectriques de grille des dispositifs à semiconducteurs et une méthode d estimation de la durée de vie de produit en présence d unedéfaillance de type TDDB.

Polprevodniški elementi - Preskus dielektrične plasti vrat s časovno odvisnim dielektričnim prebojem (TDDB) (IEC 62374:2007)

General Information

• Status: Published
• Publication Date: 22-Nov-2007
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 06-Nov-2007
• Due Date: 11-Jan-2008
• Completion Date: 23-Nov-2007
• Ref Project: EN 62374:2007 - Semiconductor devices - Time Dependent Dielectric Breakdown (TDDB) test for gate dielectric films

Relations

• Replaced By: SIST EN 62374-1:2011 - Semiconductor devices - Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers (IEC 62374-1:2010)
• Effective Date: 01-Nov-2013

Standards Content (Sample)

SLOVENSKI STANDARD
SIST EN 62374:2008
01-januar-2008
3ROSUHYRGQLãNLHOHPHQWL3UHVNXVGLHOHNWULþQHSODVWLYUDWVþDVRYQRRGYLVQLP
GLHOHNWULþQLPSUHERMHP7''%,(&
Semiconductor devices - Time Dependent Dielectric Breakdown (TDDB) test for gate
dielectric films
Halbleiterbauelemente - Prüfung des zeitabhängigen dielektrischen Durchbruchs (TDDB)
für dielektrische Gate-Schichten
Dispositifs à semiconductors - Essai de rupture diélectrique en fonction du temps
(TDDB) pour films diélectriques de grille
Ta slovenski standard je istoveten z: EN 62374:2007
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
SIST EN 62374:2008 en,fr,de
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

---------------------- Page: 1 ----------------------

SIST EN 62374:2008

---------------------- Page: 2 ----------------------

SIST EN 62374:2008


EUROPEAN STANDARD
EN 62374

NORME EUROPÉENNE
October 2007
EUROPÄISCHE NORM

ICS 31.080


English version


Semiconductor devices -
Time Dependent Dielectric Breakdown (TDDB) test
for gate dielectric films
(IEC 62374:2007)


Dispositifs à semiconductors -  Halbleiterbauelemente -
Essai de rupture diélectrique Prüfung des zeitabhängigen
en fonction du temps (TDDB) dielektrischen Durchbruchs (TDDB)
pour films diélectriques de grille für dielektrische Gate-Schichten
(CEI 62374:2007) (IEC 62374:2007)




This European Standard was approved by CENELEC on 2007-10-01. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Cyprus, the
Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain,
Sweden, Switzerland and the United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Central Secretariat: rue de Stassart 35, B - 1050 Brussels


© 2007 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 62374:2007 E

---------------------- Page: 3 ----------------------

SIST EN 62374:2008
EN 62374:2007 – 2 –
Foreword
The text of document 47/1894/FDIS, future edition 1 of IEC 62374, prepared by IEC TC 47,
Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 62374 on 2007-10-01.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2008-07-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2010-10-01
__________
Endorsement notice
The text of the International Standard IEC 62374:2007 was approved by CENELEC as a European
Standard without any modification.
__________

---------------------- Page: 4 ----------------------

SIST EN 62374:2008
NORME CEI
INTERNATIONALE
IEC



62374
INTERNATIONAL


Première édition
STANDARD

First edition

2007-03


Dispositifs à semiconducteurs –
Essai de rupture diélectrique en fonction du
temps (TDDB) pour films diélectriques de grille


Semiconductor devices –
Time dependent dielectric breakdown
(TDDB) test for gate dielectric films
© IEC 2007 Droits de reproduction réservés ⎯ Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in any
utilisée sous quelque forme que ce soit et par aucun procédé, form or by any means, electronic or mechanical, including
électronique ou mécanique, y compris la photocopie et les photocopying and microfilm, without permission in writing from
microfilms, sans l'accord écrit de l'éditeur. the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: [phone] Telefax: [phone] E-mail: [e-mail] Web: www.iec.ch
CODE PRIX
S
PRICE CODE
Commission Electrotechnique Internationale
International Electrotechnical Commission
МеждународнаяЭлектротехническаяКомиссия
Pour prix, voir catalogue en vigueur
For price, see current catalogue

---------------------- Page: 5 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 3 –
CONTENTS
FOREWORD.5

1 Scope.9
2 Terms and definitions .9
3 Test equipment.13
4 Test samples.13
4.1 General .13
4.2 Test structure: capacitor structure .13
4.3 Area .15
5 Procedures.15
5.1 General .15
5.2 Pre-test .19
5.3 Test conditions .19
5.4 Criteria .19
6 Lifetime estimation .25
6.1 General .25
6.2 Acceleration model.25
6.3 A procedure for a lifetime estimation .29
7 Lifetime dependence on gate oxide area .35

Annex A (informative) Supplementary determining test condition and data analysis .37

Bibliography.43

Figure 1 – Test flow diagram of constant voltage stress method .17
Figure 2– Typical example of implementing the variance method for detecting
breakdown .23
Figure 3 – Timing diagram showing the implementation of the stress interruption
technique for monitoring the change in SILC (t shall be <1 % of the anticipated t ) .25
init bd
Figure 4– Graph fitted Weibull/Lognormal distribution (Weibull is recommended).31
Figure 5 – Estimate procedure of electric acceleration factor .33
Figure 6 – Estimation procedure of activation energy.33
Figure A.1 – Voltage dependence of lifetime for TDDB.37
Figure A.2 – Each component plotted as a function of V .41
OX

---------------------- Page: 6 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

SEMICONDUCTOR DEVICES −

TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) TEST
FOR GATE DIELECTRIC FILMS

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62374 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/1894/FDIS 47/1896/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

---------------------- Page: 7 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 7 –
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.

---------------------- Page: 8 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 9 –
SEMICONDUCTOR DEVICES −

TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) TEST
FOR GATE DIELECTRIC FILMS



1 Scope
This International Standard provides a test method of Time Dependent Dielectric Breakdown
(TDDB) for gate dielectric films on semiconductor devices and a product lifetime estimation
method of TDDB failure.
2 Terms and definitions
For the purposes of this document, the following terms and definitions apply:
2.1
oxide electric field (strength)
E
ox
defined as oxide voltage divided by oxide thickness.
NOTE
E = V /t (1)
ox ox ox
where
E (MV/cm) is the oxide electric field;
ox
V is the oxide voltage;
ox
t is the oxide thickness.
ox
t must be determined by a consistent, documented method (physical measurement method
ox
by Scanning Electron Microscope (SEM), Transmission Electron Microscope (TEM) or
Capacitance-Voltage (CV) analysis). It is important to point out that the applied voltage is not
necessarily the voltage across the oxide. Ultra-thin oxides exhibit quantum confinement
effects and gate electrode depletion effects effectively reducing the voltage across the oxide.
The method of determining t or a reference to the documented standard must be included in
ox
the data report.
2.2
gate oxide leakage current
I
g
the leakage current flowing in the gate terminal of an insulated-gate field-effect transistor
NOTE The letter symbol “I ” is in common use for the gate leakage current.
g
2.3
initial gate oxide leakage current
I
g0
leakage current flowing in the gate terminal of an oxide insulated-gate when a use voltage is
applied before stress voltage or stress electric field is applied

---------------------- Page: 9 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 11 –
2.4
compliance current
I
comp
maximum current of the voltage-forcing equipment
NOTE A compliance limit can be specified for a particular test.
2.5
measured gate oxide leakage current
I
meas
gate leakage current measured in the pre-test or Constant Voltage Stress (CVS) test
2.6
stress-induced leakage oxide current
I
SILC
stress-induced leakage current measured at V
SILC
NOTE This value is measured and compared during the constant voltage test if the stress interruption method is
used to detect breakdown.
2.7
use gate oxide leakage current
I
use
typical measured current through the oxide at the normal use voltage
2.8
stress gate oxide leakage current
I
stress
oxide gate current measured during the CVS test
2.9
previously measured gate oxide leakage current
I
previous
previously measured oxide current in CVS test condition
2.10
breakdown time
t
bd
summation of time at which stress voltage is applied to gate oxide until oxide failure
NOTE In the CVS test, the applied stress voltage is interrupted by measuring and judging repeatedly. (See Figure
1)
2.11
interval time
t
int
time that stress is applied before the stress is interrupted and I is measured during the
SILC
stress interruption technique for detecting breakdown
NOTE  See Figure 3
2.12
gate oxide thickness
t
ox
physical thickness of gate oxide

---------------------- Page: 10 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 13 –
2.13
wait time
t
wait
time before I is measured after a stress is interrupted during the stress interruption
SILC
technique for detecting breakdown (see Figure 3)
2.14
SILC voltage
V
SILC
voltage at which the stress-induced leakage current (I ) is measured
SILC
2.15
stress voltage
V
stress
voltage applied during CVS test
2.16
use voltage
V
use
voltage that is applied during the pre-test to determine device validity
NOTE This voltage is usually the power supply voltage or use voltage of the technology.
3 Test equipment
TDDB test can be applied for both package level test and wafer level tests. A high
temperature oven is used for the package level test. In the case of the wafer level tests, a
wafer prober with a hot plate or a hot chuck is necessary. Additionally, measurement
instruments are necessary that can detect failure criterion (that depends on t , device
ox
structure and area).
4 Test samples
4.1 General
The test samples for TDDB test should have the following test structure and area.
4.2 Test structure: capacitor structure
The test sample has a capacitor structure that consists of the gate dielectric film and gate
electrode formed on a silicon substrate.
A capacitor or a field effect transistor (FET)-structure can be selected for the purpose of the
test. The area and geometry can be varied.
FET-structures are preferred over capacitors, because stress should be performed in use
mode, which is the inversion case. Multiple structures with variation in active area, isolation
edge and gate edge perimeter are recommended in order to measure area scaling and to
identify area vs. perimeter effects.
Test structure leads should be designed to minimize resistance to prevent voltage drops.

---------------------- Page: 11 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 15 –
It is recommended that at least three device areas be used so proper area scaling can be
achieved. The area range can span over two orders of magnitude.
It is important to get the Weibull Shape parameter.
4.3 Area
In the case of thin gate oxides (t < 5 nm) with a large dielectric area, the I ratio becomes
ox g
too large by tunnel current effects, the breakdowns become “softer” and noisy, so that the
dielectric breakdown cannot be accurately measured. As a result the area shall be small
enough so that the I ratio after breakdown to before breakdown is measurable.
g
-11 2 -3 2
A typical area for thin gate oxide is in the range of 1 x 10 cm to 1 x 10 cm . There are
cases where the "current noise“ criterion is effective.
A small area capacitor may be necessary to detect soft breakdown when large tunneling
current exists.
For thick gate oxides (t > 5 nm) the tunnelling current has a negligible effect, so the area
ox
-3 2 -1 2
upper limit can be extended from 1 x 10 cm to 1 x 10 cm .
5 Procedures
5.1 General
In this section the test procedure is explained.
Figure 1 shows a procedure for the constant voltage stress method.

---------------------- Page: 12 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 17 –

Pre-TEST
Apply operating voltage
Gate current measurement (I )
meas
Yes
 I > defined criterion
meas Reject initial failure
No
t = 0
Apply stress voltage (V )
stress
Gate current measurement (I )
meas
Yes
 I > defined criterion
meas
Record breakdown time (t )
bd

No
Yes
t > t ?

max Stop test
No
t = t + t
inter
IEC  114/07

Figure 1 – Test flow diagram of constant voltage stress method

---------------------- Page: 13 ----------------------

SIST EN 62374:2008
62374 © IEC:2007 – 19 –
5.2 Pre-test
The pre-test is performed for identifying initial failed samples. The gate current is measured at
the applied use voltage. If the measured current is larger than the defined criterion, then that
sample is rejected as an initial failed sample. When obtaining the defective distribution is
necessary, the CVS test without pre-test may be effective. In this case the pre-test can be
omitted.
5.3 Test conditions
5.3.1 General
The following test condition is recommended for the TDDB test. The sample size should be
selected to provide the necessary confidence level for the application.
5.3.2 Electric field
V shall be decided by a trial test to get the TDDB lifetime data in a reasonable time. It is
stress
...