oSIST prEN IEC 63550-1:2025
(Main)Semiconductor devices - Neuromorphic devices - Part 1: Evaluation method of basic characteristics in memristor devices
Semiconductor devices - Neuromorphic devices - Part 1: Evaluation method of basic characteristics in memristor devices
Halbleiterbauelemente – Neuromorphe Bauelemente – Teil 1: Bewertungsverfahren für grundlegende Eigenschaften in Memristor-Bauelementen
Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 1: Méthode d’évaluation des caractéristiques de base des dispositifs à memristance
Polprevodniški elementi - Nevromorfne naprave - 1. del: Metoda ocenjevanja osnovnih značilnosti v memristorskih napravah
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
01-november-2025
Polprevodniški elementi - Nevromorfne naprave - 1. del: Metoda ocenjevanja
osnovnih značilnosti v memristorskih napravah
Semiconductor devices - Neuromorphic devices - Part 1: Evaluation method of basic
characteristics in memristor devices
Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 1: Méthode
d’évaluation des caractéristiques de base des dispositifs à memristance
Ta slovenski standard je istoveten z: prEN IEC 63550-1:2025
ICS:
31.080.99 Drugi polprevodniški elementi Other semiconductor devices
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
47/2943/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 63550-1 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2025-09-05 2025-11-28
SUPERSEDES DOCUMENTS:
47/2870/CD, 47/2925/CC
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):
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TITLE:
Semiconductor devices - Neuromorphic devices - Part 1: Evaluation method of basic
characteristics in memristor devices
PROPOSED STABILITY DATE: 2029
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IEC CDV 63550-1 © IEC 2025
1 CONTENTS
3 FOREWORD . 3
4 INTRODUCTION . 5
5 1 Scope . 7
6 2 Normative references . 7
7 3 Terms and definitions . 7
8 4 Device under test (DUT) . 9
9 4.1 General . 9
10 5. Test apparatus and environment. 9
11 5.1 General . 9
12 5.2 Test equipment and tools . 9
13 5.3 Probe station . 10
14 5.4 Test environment . 11
15 6. Test method . 11
16 6.1.1 Read . 11
17 6.1.2 Forming . 11
18 6.1.3 Initialize . 12
19 6.1.4 Potentiation programming . 13
20 6.1.5 Depression programming . 14
21 7. Test Report . 16
22 Bibliography . 17
25 Figure 1 – a) Schematic of a feedforward neural network. b) A biological-memristor
26 synapse comparison. . 6
27 Figure 2 – a) Schematic of memristor device. b) Equivalent circuit of a memristor
28 device . 9
29 Figure 3 – Block diagram of the measurement setup of a memristor device (example) . 10
30 Figure 4 – (a) Circuit diagram for read process (b) Voltage-time graph to exhibit the
31 read operation of a memristor device . 11
32 Figure 5 – (a) Circuit diagram in forming process (b) Voltage-time graph to exhibit the
33 forming operation of a memristor . 12
34 Figure 6 – Simulation test flow chart of the forming process . 12
35 Figure 7 – Simulation test flow chart of the initialize operation of a memristor device . 13
36 Figure 8 – (a) Circuit diagram for forming process (b) Voltage-time graph to exhibit the
37 potentiation operation of a memristor . 14
38 Figure 9 – Simulation test flow chart of the potentiation operation of a memristor . 14
39 Figure 10 – (a) Circuit diagram for forming process (b) Voltage-time graph to exhibit
40 the depression operation of a memristor . 15
41 Figure 11 – Simulation test flow chart of the depression operation of a memristor . 15
42 Figure 12 – Exemplary cumulative resistance distribution after set and reset
43 programming of a memristor device . 15
IEC CDV 63550-1 © IEC 2025
INTERNATIONAL ELECTROTECHNICAL COMMISSION
47 ____________
49 Semiconductor devices - Neuromorphic devices -
51 Part 1: Evaluation method of basic characteristics in memristor devices
FOREWORD
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International Standard IEC 62951-X has been prepared by technical committee 47:
Semiconductor devices.
The text of this International Standard is based on the following documents:
NP Report on voting
47/XX/NP 47/XX/NP
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The language used for the development of this International Standard is English.
IEC CDV 63550-1 © IEC 2025
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
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IEC CDV 63550-1 © IEC 2025
INTRODUCTION
112 With the rapid development of artificial intelligence, hardware performance and energy
113 efficiency are facing higher demands. The traditional von Neumann architecture is limited by
114 the separation of memory and process units, inevitably encountering the memory wall and
115 power wall challenges. Neuromorphic computing directly performs operations inside memory,
116 realizing the organic integration of the logic unit and memory, which can effectively reduce the
117 power consumption caused by the data transfer between memory and processor, breaking
118 through the traditional von Neumann bottleneck.
Traditional memory can be divided into volatile memory such as SRAM, DRAM, and non-volatile
memory such as Flash, EPROM. These traditional memories generally have problems such as
long writing time, high power consumption, and low endurance, while neuromorphic memristor
devices, such as RRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random
Access Memory), PCM (Phase Change Memory), MRAM (Magnetoresistive Random Access
Memory), ferroelectric filed-effect transistor (FeFET)and EGT (electrolyte-gated transistors),
and so on, has the advantages of good CMOS compatibility, low power consumption, and fast
read and write speed. Therefore, the hardware carrier of neuromorphic computing is gradually
changing from NOR Flash to neuromorphic memristor devices.
At present, the design of neuromorphic computing has attracted more and more attention. It is significant
to further standardize testing methods of neuromorphic memristor devices and propose requirements
for comprehensive tests. It can be used to clarify the core elements of the test and ensure further in-
depth research of the neuromorphic memristor devices and calculation array. It is crucial to define the
core elements which can ensure tests will be executed evidently, thus guaranteeing further in-depth
study of neuromorphic memristor array.
To develop a neural network (Figure 1a) in hardware, the appropriate circuit to represent the
function of the neuron and synapse must be found. Emerging memory technologies are crucial
in this context because they can enhance the capability of traditional CMOS technology by
enabling the implementation of analog and embedding non-volatile memory in a nanoscale
portion of the chip. The emerging memory also makes it possible for in-memory computing for
which data is processed in real time. For neuromorphic hardware systems, neural networks can
be divided into deep neural networks (DNNs) and spiking neural networks (SNNs) [1]. DNNs
require artificial synapses with analog conductance variation during training via
backpropagation. In SNNs, artificial synapse is required to mimic the spike dependent plasticity
(STDP) features which is utilised in unsupervised learning [2].
Figure 1b shows the schematic of artificial neural system based on memristor. The memristor
is a novel two-terminal electrical device that adds to the traditional repertory of fundamental
circuit components which includes the resistor, inductor, and capacitor. Although Leon Chua
proposed it in 1971, it remained a theoretical curiosity until 2008 wh
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