ETSI TR 103 570 V1.1.1 (2017-10)

CYBER; Quantum-Safe Key Exchanges

DTR/CYBER-QSC-007

General Information

• Status: Published
• Publication Date: 04-Oct-2017
• Technical Committee: CYBER QSC - Quantum-Safe Cryptography
• Current Stage: 12 - Completion
• Due Date: 30-Oct-2017
• Completion Date: 05-Oct-2017

Standards Content (Sample)

TECHNICAL REPORT
CYBER;
Quantum-Safe Key Exchanges
2 ETSI TR 103 570 V1.1.1 (2017-10)

Reference
DTR/CYBER-QSC-007
Keywords
algorithm, confidentiality, quantum cryptography,
security
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3 ETSI TR 103 570 V1.1.1 (2017-10)
Contents
Intellectual Property Rights . 6
Foreword . 6
Modal verbs terminology . 6
1 Scope . 7
2 References . 7
2.1 Normative references . 7
2.2 Informative references . 7
3 Abbreviations . 13
4 Quantum-safe key exchanges . 13
4.1 Introduction . 13
4.2 Use cases . 14
4.2.1 General comments . 14
4.2.2 Network security . 14
4.2.3 Internet of Things . 14
4.3 Candidate primitives. 14
5 Implementation considerations . 15
5.1 Introduction . 15
5.2 Active security . 15
5.2.1 Invalid key attacks . 15
5.2.2 Key validation . 15
5.2.3 Performance impact . 16
5.3 Side-channel protection . 16
5.3.1 Side-channel vulnerabilities . 16
5.3.2 Side-channel mitigations . 16
5.3.3 Performance impact . 16
6 Learning with Errors . 17
6.1 Introduction . 17
6.2 LWE key exchange . 17
6.2.1 Overview . 17
6.2.2 Public parameters . 18
6.2.3 Key generation . 18
6.2.4 Key extraction . 18
6.2.5 Reconciliation . 19
6.3 Ring-LWE key exchange . 19
6.3.1 Overview . 19
6.3.2 Public parameters . 20
6.3.3 Key generation . 21
6.3.4 Key extraction . 21
6.3.5 Reconciliation . 21
6.4 Implementation considerations . 22
6.4.1 Active security . 22
6.4.2 Side-channel protection . 22
6.5 Parameter selection. 22
6.5.1 LWE proposed parameters . 22
6.5.2 Ring-LWE proposed parameters . 23
6.5.3 Security estimates . 23
6.6 Performance . 23
6.6.1 Performance on a 64-bit processor . 23
6.6.2 Performance on a 32-bit embedded processor . 24
6.6.3 Performance on 32-bit microcontrollers . 24
6.7 Summary . 25
7 Supersingular isogenies . 25
ETSI
4 ETSI TR 103 570 V1.1.1 (2017-10)
7.1 Introduction . 25
7.2 SIDH key exchange . 25
7.2.1 Overview . 25
7.2.2 Public parameters . 26
7.2.3 Key generation . 26
7.2.4 Key exchange . 27
7.3 Implementation considerations . 27
7.3.1 Static key exchanges . 27
7.3.2 Side-channel protection . 28
7.4 Parameter selection. 28
7.4.1 Proposed parameters . 28
7.4.2 Security estimates . 28
7.5 Performance . 28
7.5.1 Performance on a 64-bit desktop processor . 28
7.5.2 Performance on a 64-bit embedded processor . 29
7.5.3 Performance on a 32-bit embedded processor . 29
7.6 Summary . 29
8 Key exchanges from key transport mechanisms . 29
8.1 General construction. 29
8.2 Niederreiter. 30
8.2.1 Introduction. 30
8.2.2 Niederreiter key exchange . 30
8.2.2.1 Overview . 30
8.2.2.2 Public parameters . 31
8.2.2.3 Key generation . 31
8.2.2.4 Decryption . 32
8.2.3 Implementation considerations . 32
8.2.3.1 Active attacks . 32
8.2.3.2 Side-channel attacks . 32
8.2.4 Parameter selection . 32
8.2.4.1 Proposed parameters . 32
8.2.4.2 Security estimates . 33
8.2.5 Performance . 33
8.2.5.1 Performance on a 64-bit server processor . 33
8.2.5.2 Performance on a 64-bit desktop processor . 33
8.2.5.3 Performance on an 8-bit microcontroller . 33
8.2.6 Summary . 34
8.3 NTRU . 34
8.3.1 Introduction. 34
8.3.2 NTRU key exchange . 34
8.3.2.1 Overview . 34
8.3.2.2 Public parameters . 35
8.3.2.3 Decryption . 35
8.3.3 Implementation considerations . 35
8.3.3.1 Static key exchange . 35
8.3.3.2 Side channel attacks . 35
8.3.4 Parameter selection . 36
8.3.4.1 Proposed parameters . 36
8.3.4.2 Security estimates . 36
8.3.5 Performance . 36
8.3.5.1 Performance on a 64-bit desktop processor . 36
8.3.5.2 Performance on a 32-bit embedded processor. 36
8.3.5.3 Performance on a 32-bit microcontroller . 37
8.3.6 Summary . 37
9 Conclusions . 37
Annex A: LWE design and security considerations . 39
A.1 LWE and Ring-LWE variants . 39
A.1.1 Rings . 39
A.1.2 Distributions . 39
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5 ETSI TR 103 570 V1.1.1 (2017-10)
A.1.2.1 Discrete Gaussians . 39
A.1.2.2 Approximate Gaussians . 39
A.1.2.3 Small distributions . 40
A.1.2.4 Learning with Rounding . 40
A.1.3 Varying A . 40
A.1.4 Reconciliation mechanisms . 41
A.1.5 Key transport . 41
A.2 Security considerations. 42
A.2.1 Provable security . 42
A.2.2 Passive security . 42
A.2.3 Active security . 43
Annex B: SIDH background and security considerations . 44
B.1 Mathematical background . 44
B.1.1 Isogenies . 44
B.1.2 Parameter generation . 44
B.1.3 Public key compression . 45
B.2 Security. 45
B.2.1 Provable security . 45
B.2.2 Passive security . 46
B.2.3 Active security . 46
Annex C: Open Quantum-Safe benchmarks . 48
C.1 Open Quantum-Safe . 48
C.2 Benchmarks . 48
C.2.1 Performance on a 64-bit desktop processor . 48
C.2.2 Performance on a 64-bit laptop processor . 49
C.2.3 Performance on a 32-bit embedded processor . 49
C.3 Discussion . 49
History . 50

ETSI
6 ETSI TR 103 570 V1.1.1 (2017-10)
Intellectual Property Rights
Essential patents
IPRs essential or potentially essential to the present document may have been declared to ETSI. The information
pertaining to these essential IPRs, if any, is publicly available for ETSI members and non-members, and can be found
in ETSI SR 000 314: "Intellectual Property Rights (IPRs); Essential, or potentially Essential, IPRs notified to ETSI in
respect of ETSI standards", which is available from the ETSI Secretariat. Latest updates are available on the ETSI Web
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Foreword
This Technical Report (TR) has been produced by ETSI Technical Committee Cyber Security (CYBER).
Modal verbs terminology
In the present document "should", "should not", "may", "need not", "will", "will not", "can" and "cannot" are to be
interpreted as described in clause 3.2 of the ETSI Drafting Rules (Verbal forms for the expression of provisions).
"must" and "must not" are NOT allowed in ETSI deliverables except when used in direct citation.

ETSI
7 ETSI TR 103 570 V1.1.1 (2017-10)
1 Scope
The present document compares a selection of proposals for quantum-safe key exchanges taken from the academic
literature. In particular, it includes key exchanges based on the Learning with Errors (LWE), Ring-LWE and
Supersingular Isogeny Diffie-Hellman (SIDH) problems, as well as key exchanges constructed from the Niederreiter
and NTRU key transport schemes.
The present document gives an overview of each key exchange, lists proposed parameters and gives software
performance estimates on a range of processors. It also discusses various security and implementation considerations
such as active attacks and side-channel vulnerabilities.
2 References
2.1 Normative references
Normative references are not applicable in the present document.
2.2 Informative references
References are either specific (identified by date of publication and/or edition number or version number) or
non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the
referenced document (including any amendments) applies.
NOTE: While any hyperlinks included in this clause were valid at the time of publication ETSI cannot guarantee
their long term validity.
The following referenced documents are not necessary for the application of the present document but they assist the
user with regard to a particular subject area.
user with regard to a particular subject area.
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11 ETSI TR 103 570 V1.1.1 (2017-10)
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