ETSI TS 102 361-1 V2.2.1 (2013-02)

Electromagnetic compatibility and Radio spectrum Matters (ERM); Digital Mobile Radio (DMR) Systems; Part 1: DMR Air Interface (AI) protocol

RTS/ERM-TGDMR-311-1

General Information

• Status: Published
• Publication Date: 25-Feb-2013
• Technical Committee: ERM TGDMR - Digital Mobile Radio
• Current Stage: 12 - Completion
• Due Date: 05-Mar-2013
• Completion Date: 26-Feb-2013

Standards Content (Sample)

Technical Specification
Electromagnetic compatibility
and Radio spectrum Matters (ERM);
Digital Mobile Radio (DMR) Systems;
Part 1: DMR Air Interface (AI) protocol

2 ETSI TS 102 361-1 V2.2.1 (2013-02)

Reference
RTS/ERM-TGDMR-311-1
Keywords
air interface, digital, PMR, protocol, radio
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ETSI
3 ETSI TS 102 361-1 V2.2.1 (2013-02)
Contents
Intellectual Property Rights . 8
Foreword . 8
1 Scope . 9
2 References . 9
2.1 Normative references . 9
2.2 Informative references . 10
3 Definitions, symbols and abbreviations . 10
3.1 Definitions . 10
3.2 Symbols . 13
3.3 Abbreviations . 13
4 Overview . . 15
4.1 Protocol architecture. 15
4.1.1 Air Interface Physical Layer (layer 1). 16
4.1.2 Air Interface Data Link Layer (layer 2) . 17
4.1.3 Air Interface Call Control Layer (CCL) (layer 3) . 17
4.2 DMR TDMA structure . 17
4.2.1 Overview of burst and channel structure . 17
4.2.2 Burst and frame structure . 19
4.3 Frame synchronization . 20
4.4 Timing references . 22
4.4.1 Repeater mode BS established timing relationship . 22
4.4.2 Repeater mode MS established timing relationship . 22
4.4.3 Direct mode timing relationship . 22
4.4.4 TDMA direct mode timing relationship. 22
4.5 Common Announcement Channel (CACH) . 23
4.6 Basic channel types . 24
4.6.1 Traffic channel with CACH . 24
4.6.2 Traffic channel with guard time . 24
4.6.3 Bi-directional channel . 25
5 Layer 2 protocol description . 25
5.1 Layer 2 timing . 25
5.1.1 Channel timing relationship . 25
5.1.1.1 Aligned channel timing . 26
5.1.1.2 Offset channel timing . 26
5.1.2 Voice timing . 27
5.1.2.1 Voice superframe . 27
5.1.2.2 Voice initiation . 27
5.1.2.3 Voice termination . 28
5.1.3 Data timing . 28
5.1.3.1 Single slot data timing . 29
5.1.3.2 Dual slot data timing . 29
5.1.4 Traffic timing . 30
5.1.4.1 BS timing . 30
5.1.4.2 Single frequency BS timing . 31
5.1.4.3 Direct mode timing . 31
5.1.4.4 Time Division Duplex (TDD) timing . 32
5.1.4.5 Continuous transmission mode . 32
5.1.4.6 TDMA direct mode timing . 33
5.1.5 Reverse Channel (RC) timing . 33
5.1.5.1 Embedded outbound Reverse Channel (RC) . 33
5.1.5.2 Dedicated outbound Reverse Channel (RC) . 34
5.1.5.3 Standalone inbound Reverse Channel (RC) . 35
5.1.5.4 Direct mode Reverse Channel (RC) . 35
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4 ETSI TS 102 361-1 V2.2.1 (2013-02)
5.2 Channel access . 35
5.2.1 Basic channel access rules . 37
5.2.1.1 Types of channel activity . 37
5.2.1.2 Channel status . 38
5.2.1.3 Timing master . 38
5.2.1.4 Hang time messages and timers . 38
5.2.1.5 Slot 1 and 2 dependency . 38
5.2.1.6 Transmit admit criteria . 39
5.2.1.7 Transmission re-tries . 39
5.2.2 Channel access procedure . 40
5.2.2.1 Direct mode Channel Access . 40
5.2.2.1.1 MS Out_of_Sync Channel Access. 40
5.2.2.1.2 MS Out_of_Sync_Channel_Monitored Channel Access . 42
5.2.2.1.3 MS In_Sync_Unknown_System Channel Access . 43
5.2.2.1.4 MS Not_in_Call Channel Access . 44
5.2.2.1.5 MS Others_Call Channel Access . 44
5.2.2.1.6 MS My_Call Channel Access . 44
5.2.2.2 Repeater mode channel access . 44
5.2.2.2.1 MS Out_of_Sync Channel Access. 44
5.2.2.2.2 MS Out_of_Sync_Channel_Monitored Channel Access . 46
5.2.2.2.3 MS In_Sync_Unknown_System channel access . 47
5.2.2.2.4 MS TX_Wakeup_Message . 48
5.2.2.2.5 MS Not_In_Call channel access . 49
5.2.2.2.6 MS Others_Call channel access . 50
5.2.2.2.7 MS My_Call channel access . 50
5.2.2.2.8 MS In_Session channel access . 50
5.2.2.3 Non-time critical CSBK ACK/NACK channel access . 50
5.2.2.4 TDMA direct mode channel access . 51
5.2.2.4.1 MS Out_of_Sync channel access . 51
5.2.2.4.2 MS Out_of_Sync_Channel_Monitored channel access . 54
5.2.2.4.3 MS In_Sync_Unknown_System channel access . 55
5.2.2.4.4 MS Not_in_Call channel access . 56
5.2.2.4.5 MS Others_Call channel access . 56
5.2.2.4.6 MS My_Call channel access . 56
5.2.2.4.7 Immediate response channel access. 56
6 Layer 2 burst format . 56
6.1 Vocoder socket . 57
6.2 Data and control . 58
6.3 Common Announcement Channel burst . 59
6.4 Reverse Channel . 60
6.4.1 Standalone inbound Reverse Channel burst . 60
6.4.2 Outbound reverse channel (RC) burst . 61
7 DMR signalling . 61
7.1 Link Control message structure . 61
7.1.1 Voice LC header . 62
7.1.2 Terminator with LC . 63
7.1.3 Embedded signalling. 64
7.1.3.1 Outbound channel . 65
7.1.3.2 Inbound channel . 66
7.1.4 Short Link Control in CACH . 66
7.2 Control Signalling BlocK (CSBK) message structure . 67
7.2.1 Control Signalling BlocK (CSBK) . 67
7.3 Idle message . 68
7.4 Multi Block Control (MBC) message structure. 69
7.4.1 Multi Block Control (MBC) . 71
8 DMR Packet Data Protocol (PDP) . . 72
8.1 Internet Protocol . 72
8.2 Datagram fragmentation and re-assembly . 73
8.2.1 Header block structure . 74
8.2.1.1 Unconfirmed data Header . 75
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5 ETSI TS 102 361-1 V2.2.1 (2013-02)
8.2.1.2 Confirmed data header . 76
8.2.1.3 Response data header . 76
8.2.1.4 Proprietary data header . 76
8.2.1.5 Status/precoded short data header . 77
8.2.1.6 Raw short data header . 78
8.2.1.7 Defined short data header . 78
8.2.1.8 Unified Data Transport (UDT) data header. 79
8.2.2 Data block structure . 79
8.2.2.1 Unconfirmed data block structure . 79
8.2.2.2 Confirmed data block structure . 82
8.2.2.3 Response packet format . 85
8.2.2.4 Hang time for response packet . 87
8.2.2.5 Unified Data Transport (UDT) last data block structure . 87
9 Layer 2 PDU description . 88
9.1 PDUs for voice bursts, general data bursts and the CACH . 89
9.1.1 Synchronization (SYNC) PDU . 89
9.1.2 Embedded signalling (EMB) PDU . 89
9.1.3 Slot Type (SLOT) PDU . 90
9.1.4 TACT PDU . 90
9.1.5 Reverse Channel (RC) PDU . 90
9.1.6 Full Link Control (FULL LC) PDU . 91
9.1.7 Short Link Control (SHORT LC) PDU . 91
9.1.8 Control Signalling Block (CSBK) PDU . 91
9.1.9 Pseudo Random Fill Bit (PR FILL) PDU . 91
9.2 Data related PDU description . 91
9.2.1 Confirmed packet Header (C_HEAD) PDU . 92
9.2.2 Rate ¾ coded packet Data (R_3_4_DATA) PDU . 92
9.2.3 Rate ¾ coded Last Data block (R_3_4_LDATA) PDU . 92
9.2.4 Confirmed Response packet Header (C_RHEAD) PDU . 93
9.2.5 Confirmed Response packet Data (C_RDATA) PDU . 93
9.2.6 Unconfirmed data packet Header (U_HEAD) PDU . 94
9.2.7 Rate ½ coded packet Data (R_1_2_DATA) PDU . 94
9.2.8 Rate ½ coded Last Data block (R_1_2_LDATA) PDU . 95
9.2.9 Proprietary Header (P_HEAD) PDU . 95
9.2.10 Status/Precoded short data packet Header (SP_HEAD) PDU . 96
9.2.11 Raw short data packet Header (R_HEAD) PDU . 96
9.2.12 Defined Data short data packet Header (DD_HEAD) PDU . 97
9.2.13 Unified Data Transport Header (UDT_HEAD) PDU . 97
9.2.14 Unified Data Transport Last Data block (UDT_LDATA) PDU . 97
9.2.15 Rate 1 coded packet Data (R_1_DATA) PDU . 98
9.2.16 Rate 1 coded Last Data block (R_1_LDATA) PDU . 98
9.3 Layer 2 information element coding . 99
9.3.1 Colour Code (CC) . 99
9.3.2 Privacy Indicator (PI). 99
9.3.3 LC Start/Stop (LCSS) . 99
9.3.4 EMB parity . 99
9.3.5 Feature set ID (FID) . 100
9.3.6 Data Type. 100
9.3.7 Slot Type parity . 100
9.3.8 Access Type (AT) . 101
9.3.9 TDMA Channel (TC). 101
9.3.10 Protect Flag (PF) . 101
9.3.11 Full Link Control Opcode (FLCO) . 101
9.3.12 Short Link Control Opcode (SLCO) . 101
9.3.13 TACT parity. 102
9.3.14 RC parity . 102
9.3.15 Group or Individual (G/I) . 102
9.3.16 Response Requested (A) . 102
9.3.17 Data Packet Format (DPF) . 102
9.3.17A Header Compression (HC) . 103
9.3.18 SAP identifier (SAP) . 103
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6 ETSI TS 102 361-1 V2.2.1 (2013-02)
9.3.19 Logical Link ID (LLID) . 103
9.3.20 Full message flag (F) . 103
9.3.21 Blocks to Follow (BF) . 104
9.3.22 Pad Octet Count (POC) . 104
9.3.23 Re-Synchronize Flag (S) . 104
9.3.24 Send sequence number (N(S)) . 105
9.3.25 Fragment Sequence Number (FSN) . 105
9.3.26 Data Block Serial Number (DBSN) . 106
9.3.27 Data block CRC (CRC-9) . 106
9.3.28 Class (Class) . 106
9.3.29 Type (Type) . 106
9.3.30 Status (Status) . 106
9.3.31 Last Block (LB) . 107
9.3.32 Control Signalling BlocK Opcode (CSBKO) . 107
9.3.33 Appended Blocks (AB) . 107
9.3.34 Source Port (SP) . 107
9.3.35 Destination Port (DP). 107
9.3.36 Status/Precoded (S_P). 108
9.3.37 Selective Automatic Repeat reQuest (SARQ) . 108
9.3.38 Defined Data format (DD) . 108
9.3.39 Unified Data Transport Format (UDT Format) . 109
9.3.40 UDT Appended Blocks (UAB) . 109
9.3.41 Supplementary Flag (SF) . 109
9.3.42 Pad Nibble . 109
10 Physical Layer . 110
10.1 General parameters . 110
10.1.1 Frequency range . 110
10.1.2 RF carrier bandwidth . 110
10.1.3 Transmit frequency error . 110
10.1.4 Time base clock drift error . 110
10.2 Modulation . 111
10.2.1 Symbols . 111
10.2.2 4FSK generation . 111
10.2.2.1 Deviation index . 111
10.2.2.2 Square root raised cosine filter . 111
10.2.2.3 4FSK Modulator . 112
10.2.3 Burst timing . 112
10.2.3.1 Normal burst . 113
10.2.3.1.1 Power ramp time. 113
10.2.3.1.2 Symbol timing . 114
10.2.3.1.3 Propagation delay and transmission time . 114
10.2.3.2 Reverse channel (RC) burst. 115
10.2.3.2.1 Power ramp time. 115
10.2.3.2.2 Symbol timing . 116
10.2.3.2.3 Propagation delay . 117
10.2.3.3 Synthesizer Lock-Time constraints . 117
10.2.3.4 Transient frequency constraints during symbol transmission time . 117
Annex A (normative): Numbering and addressing . 118
Annex B (normative): FEC and CRC codes . 119
B.1 Block Product Turbo Codes . 120
B.1.1 BPTC (196,96) . 120
B.2 Variable length BPTC . 123
B.2.1 Variable length BPTC for embedded signalling . 123
B.2.2 Variable length BPTC for Reverse Channel . 125
B.2.3 Variable length BPTC for CACH signalling . 126
B.2.4 Rate ¾ Trellis code . 128
B.2.5 Rate 1 coded data . 132
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7 ETSI TS 102 361-1 V2.2.1 (2013-02)
B.3 Generator matrices and polynomials . 134
B.3.1 Golay (20,8) . 134
B.3.2 Quadratic residue (16,7,6) . 134
B.3.3 Hamming (17,12,3) . 135
B.3.4 Hamming (13,9,3), Hamming (15,11,3), and Hamming (16,11,4) . 135
B.3.5 Hamming (7,4,3) . 136
B.3.6 Reed-Solomon (12,9) . 136
B.3.7 8-bit CRC calculation . 138
B.3.8 CRC-CCITT calculation . 139
B.3.9 32-bit CRC calculation . 139
B.3.10 CRC-9 calculation . 141
B.3.11 5-bit Checksum (CS) calculation . 142
B.3.12 Data Type CRC Mask . 143
B.4 Interleaving . 144
B.4.1 CACH interleaving . 144
Annex C (informative): Example timing diagrams . 145
C.1 Direct mode timing . 145
C.2 Reverse Channel timing . 145
Annex D (normative): Idle and Null message bit definition . 146
D.1 Null embedded message bit definitions . 146
D.2 Idle message bit definitions . 147
Annex E (normative): Transmit bit order . 149
Annex F (normative): Timers and constants in DMR . 162
F.1 Layer 2 timers . 162
F.2 Layer 2 constants . 163
Annex G (informative): High level states overview . 164
G.1 High Level MS states and SDL description . 164
G.1.1 MS Level 1 SDL . 164
G.1.2 MS Level 2 SDL . 167
G.2 High level BS states and SDL descriptions . 169
G.2.1 BS Both Slots SDL . 169
G.2.2 BS Single Slot SDL . 170
Annex H (normative): Feature interoperability . 172
H.1 Feature set ID (FID) . 172
H.2 Application for Manufacturer's Feature set ID . 172
Annex I (informative): ETSI MFID application form . 173
Annex J (informative): Change requests . 175
History . 177

ETSI
8 ETSI TS 102 361-1 V2.2.1 (2013-02)
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