ETSI TS 103 713 V16.0.0 (2022-05)

Smart Secure Platform (SSP); SPI interface (Release 16)

RTS/SET-T103713vg00

General Information

• Status: Not Published
• Technical Committee: SET TEC - SET-TEC
• Current Stage: 12 - Completion
• Due Date: 30-May-2022
• Completion Date: 24-May-2022

Standards Content (Sample)

ETSI TS 103 713 V16.0.0 (2022-05)






TECHNICAL SPECIFICATION
Smart Secure Platform (SSP);
SPI interface
(Release 16)

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Release 16 2 ETSI TS 103 713 V16.0.0 (2022-05)

Reference
RTS/SET-T103713vg00
Keywords
M2M, MFF
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© ETSI 2022.
All rights reserved.

ETSI

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Release 16 3 ETSI TS 103 713 V16.0.0 (2022-05)
Contents
Intellectual Property Rights . 5
Foreword . 5
Modal verbs terminology . 6
1 Scope . 7
2 References . 7
2.1 Normative references . 7
2.2 Informative references . 7
3 Definition of terms, symbols and abbreviations . 8
3.1 Terms . 8
3.2 Symbols . 8
3.3 Abbreviations . 8
4 Introduction . 9
5 SCL Under-Layers Protocol Stack . 9
6 Electrical interfaces . 10
6.1 Introduction . 10
6.2 Physical interface with 5 signals . 10
6.3 Physical interface with 4 signals . 11
6.4 Electrical characteristics . 12
6.4.1 DC characteristics . 12
6.4.2 Data transfer mode, AC characteristics . 12
6.5 Slave state . 14
6.5.1 Slave state definitions . 14
6.5.2 Slave state diagram . 15
7 Data Link Layer . 16
7.1 Overview . 16
7.2 MAC Layer . 16
7.2.1 Overview . 16
7.2.2 Timing . 16
7.2.2.1 Timing definitions . 16
7.2.2.2 T1 = Slave Ready Time. 16
7.2.2.3 T2 = Slave Request Time . 17
7.2.2.4 T3 = Slave resume time from power saving mode . 17
7.2.3 5 signals MAC layer . 17
7.2.3.1 Initiation of the data transfer from the master . 17
7.2.3.2 Initiation of the data transfer from the slave . 18
7.2.3.3 Simultaneous initiation of a data transfer from both master and slave . 18
7.2.3.4 MAC activation . 19
7.2.3.5 MAC deactivation . 19
7.2.4 4 signals MAC layer . 19
7.2.4.1 Introduction . 19
7.2.4.2 Initiation of the data transfer from the master . 20
7.2.4.3 Initiation of the data transfer from the slave . 20
7.2.4.4 Simultaneous initiation of the data transfer from both master and slave. 21
7.2.4.5 Slave-driven Flow Control . 21
7.2.4.6 MAC activation . 22
7.2.4.7 MAC deactivation . 22
7.3 Link Layer Frame . 22
7.3.1 Overview . 22
7.3.2 Frame generation and transfer rules . 24
7.3.2.1 Overview . 24
7.3.2.2 Generally applicable rules . 24
7.3.2.3 Slave frame retrieval in one SPI access. 24
ETSI

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Release 16 4 ETSI TS 103 713 V16.0.0 (2022-05)
7.3.2.4 Slave frame retrieval in two SPI accesses . 25
7.3.3 Data transfer cases . 25
7.4 LLC layers . 27
7.5 Interworking of the LLC layers . 29
7.6 MCT LLC definition . 29
7.6.1 MCT LPDU structure . 29
7.6.2 MCT_DATA from master . 30
7.6.3 MCT_DATA from slave . 31
7.6.4 MCT activation procedure . 32
7.7 SHDLC LLC definition . 32
7.7.1 SHDLC overview . 32
7.7.2 Endpoints . 32
7.7.3 Flow control . 33
7.7.3.1 Overview . 33
7.7.3.2 Flow control based on SHDLC . 33
7.8 Power management . 33
7.8.1 Power saving mode . 33
7.8.2 Conditions for entering power saving mode . 33
7.8.2.1 Slave entering power saving mode . 33
7.8.2.2 Master entering power saving mode . 34
7.8.3 Resuming from power saving mode . 34
7.8.3.1 Resuming the slave from power saving mode . 34
7.8.3.2 Resuming the master from power saving mode . 34
Annex A (informative): Slave SPI interface states electrical description . 35
A.1 Slave SPI interface for 5 wire interface . 35
A.1.1 Slave SPI 5 wire interface diagram . 35
A.1.2 Slave SPI 5 wire interface states electrical description . 35
A.2 Slave SPI interface states for 4 wire interface . 36
A.2.1 Slave SPI 4 wire interface diagram . 36
A.2.2 Slave SPI 4 wire interface states electrical description . 36
Annex B (informative): Change history . 38
History . 39

ETSI

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Release 16 5 ETSI TS 103 713 V16.0.0 (2022-05)
Intellectual Property Rights
Essential patents
IPRs essential or potentially essential to normative deliverables may have been declared to ETSI. The declarations
pertaining to these essential IPRs, if any, are publicly available for ETSI members and non-members, and can be
found in ETSI SR 000 314: "Intellectual Property Rights (IPRs); Essential, or potentially Essential, IPRs notified to
ETSI in respect of ETSI standards", which is available from the ETSI Secretariat. Latest updates are available on the
ETSI Web server (https://ipr.etsi.org/).
Pursuant to the ETSI Directives including the ETSI IPR Policy, no investigation regarding the essentiality of IPRs,
including IPR searches, has been carried out by ETSI. No guarantee can be given as to the existence of other IPRs not
referenced in ETSI SR 000 314 (or the updates on the ETSI Web server) which are, or may be, or may become,
essential to the present document.
Trademarks
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ETSI claims no ownership of these except for any which are indicated as being the property of ETSI, and conveys no
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Members. 3GPP™ and LTE™ are trademarks of ETSI registered for the benefit of its Members and of the 3GPP
Organizational Partners. oneM2M™ logo is a trademark of ETSI registered for the benefit of its Members and of the
®
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Foreword
This Technical Specification (TS) has been produced by ETSI Technical Committee Secure Element Technologies
(SET).
The contents of the present document are subject to continuing work within TC SET and may change following formal
TC SET approval. If TC SET modifies the contents of the present document, it will then be republished by ETSI with
an identifying change of release date and an increase in version number as follows:
Version x.y.z
where:
x the first digit:
0 early working draft;
1 presented to TC SET for information;
2 presented to TC SET for approval;
3 or greater indicates TC SET approved document under change control.
y the second digit is incremented for all changes of substance, i.e. technical enhancements, corrections,
updates, etc.
z the third digit is incremented when editorial only changes have been incorporated in the document.
ETSI

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Release 16 6 ETSI TS 103 713 V16.0.0 (2022-05)
Modal verbs terminology
In the present document "shall", "shall not", "should", "should not", "may", "need not", "will", "will not", "can" and
"cannot" are to be interpreted as described in clause 3.2 of the ETSI Drafting Rules (Verbal forms for the expression of
provisions).
"must" and "must not" are NOT allowed in ETSI deliverables except when used in direct citation.
ETSI

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Release 16 7 ETSI TS 103 713 V16.0.0 (2022-05)
1 Scope
The present document describes the SPI interface for the communication of an SSP, as defined in ETSI
TS 103 666-1 [1] using the SCL protocol.
2 References
2.1 Normative references
References are either specific (identified by date of publication and/or edition number or version number) or
non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the
referenced document (including any amendments) applies.
• In the case of a reference to a TC SET document, a non-specific reference implicitly refers to the latest version
of that document in the same Release as the present document.
Referenced documents which are not found to be publicly available in the expected location might be found at
https://docbox.etsi.org/Reference/.
NOTE: While any hyperlinks included in this clause were valid at the time of publication, ETSI cannot guarantee
their long term validity.
The following referenced documents are necessary for the application of the present document.
[1] ETSI TS 103 666-1: "Smart Secure Platform (SSP); Part 1: General characteristics".
[2] ETSI TS 102 613: "Smart Cards; UICC - Contactless Front-end (CLF) Interface; Physical and data
link layer characteristics".
[3] ISO/IEC 13239: "Information Technology -- Telecommunications and information exchange
between systems -- High-level Data Link Control (HDLC) procedures".
2.2 Informative references
References are either specific (identified by date of publication and/or edition number or version number) or
non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the
referenced document (including any amendments) applies.
• In the case of a reference to a TC SET document, a non-specific reference implicitly refers to the latest version
of that document in the same Release as the present document.
NOTE: While any hyperlinks included in this clause were valid at the time of publication, ETSI cannot guarantee
their long term validity.
The following referenced documents are not necessary for the application of the present document but they assist the
user with regard to a particular subject area.
[i.1] ETSI TR 102 216: "Smart cards; Vocabulary for Smart Card Platform specifications".
ETSI

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Release 16 8 ETSI TS 103 713 V16.0.0 (2022-05)
3 Definition of terms, symbols and abbreviations
3.1 Terms
For the purposes of the present document, the terms given in ETSI TR 102 216 [i.1] and the following apply:
data transfer: information exchange during an SPI access between the master and the slave with SPI_MISO driven by
the slave and SPI_MOSI driven by the master while the master is toggling the SPI_CLK signal
flow control: mechanism of the Data Link Layer that consists of methods applied by the transmitter in order to send at
any time a number of logical data units that can be accepted by the receiver
frame: link layer data structure consisting of a prologue or frame header, payload and epilogue or trailer usually
containing the CRC bytes
MAC access request: request from the slave to the master for a data transfer, i.e. a MAC phase initiated by the slave
MAC phase: initiation of a data transfer by the master and/or request for a data transfer by the slave
SPI access: SPI_NSS assertion by the master, if not already asserted in the MAC phase, followed by SPI_CLK start for
transferring a certain number of bytes according to the SPI master configuration
NOTE: The number of bytes transferred during an SPI access is always the same in both directions on SPI_MISO
and SPI_MOSI and is also referred to as access length.
window size: maximum number of logical data units that can be sent from the transmitter to the receiver without any
link layer acknowledgements for any of these data units
window size slot: fixed space used by the slave in the receive buffer for the logical data units
NOTE: The length of a window size slot equals the Data Link Layer MTU.
3.2 Symbols
Void.
3.3 Abbreviations
For the purposes of the present document, the following abbreviations apply:
A Asserted
AC Alternating Current
ACT Activation
CLF ContactLess Frontend
CLT ContactLess Tunnelling
CMD Command
CPHA Clock Phase
CPOL Clock Polarity
CRC Cyclic Redundancy Check
D Driven (either Low Level or High Level)
DA De-Asserted
DC Direct Current
HiZ High Impedance
II Input Ignored
IL Input Listened
IO Input/Output
IOH High Output Current (Output current corresponding to VOH)
IOL Low Output Current (Output current corresponding to VOL)
LLC Logical Link Control
LPDU Link Protocol Data Unit
ETSI

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Release 16 9 ETSI TS 103 713 V16.0.0 (2022-05)
MAC Medium Access Control
MCT MAC aCTivation
MISO Master Input Slave Output
MOSI Master Output Slave Input
MSB Most Significant Bit
MTU Maximum Transmission Unit
NSD Non-Significant Data
OD Open Drain
OSI Open System Interconnection
POT Power-On Time
RFU Reserved for Future Use
SCL SSP Common Layer
SHDLC Simplified High Level Data Link Control
SPI Serial Peripheral Interface
SS_MI Slave Select Master Input signal
SS_MO Slave Select Master Output signal
SS_SI Slave Select Slave Input signal
SS_SO Slave Select Slave Output signal
SSP Smart Secure Platform
SWP Single Wire Protocol
NOTE: As defined in ETSI TS 102 613 [2].
UICC Universal Integrated Circuit Card
VDD Supply Voltage
VIH High Input Voltage (Input Voltage for High Logic Level)
VIL Low Input Voltage (Input Voltage for Low Logic Level)
VOH High Output Voltage (Output Voltage for High Logic Level)
VOL Low Output Voltage (Output Voltage for Low Logic Level)
4 Introduction
The Serial Peripheral Interface (SPI) is a serial synchronous full-duplex communication interface between a single
master and one or more slaves present on the same SPI bus, each slave being selected at one time by a dedicated
SPI_NSS signal. This clause defines the physical, MAC and data link layers for the SPI interface.
In this clause the terms master and slave refer respectively to the terms master SPI and slave SPI.
5 SCL Under-Layers Protocol Stack
Figure 5.1 illustrates the protocol stack below the SCL supporting the SPI interface.
ETSI

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Release 16 10 ETSI TS 103 713 V16.0.0 (2022-05)
SCL
t
n
e
m
u
c
LINK LAYER
o
Logical Link Control and SHDLC
d
(RELIABILITY and DATA
s
i
h
FLOW CONTROL)
t

f
o

e
p
o
c
S
MAC MAC
SPI
FRAMES
Other Physical Layer
Physical Layer
TRANSPORT

Figure 5.1: Protocol stack for SPI Interface
6 Electrical interfaces
6.1 Introduction
In the clauses below, different implementations of SPI interface are defined. These implementations allow bi-directional
communication and the possibility for the slave to initiate communication with the master when it has data available
thus avoiding the necessity for continuous polling to be performed by master.
Slave may initiate communication to send a command without a prior command from master.
6.2 Physical interface with 5 signals
Figure 6.1 illustrates the SPI electrical interface using 5 signals.

Figure 6.1: SPI electrical interface with 5 signals
ETSI

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Release 16 11 ETSI TS 103 713 V16.0.0 (2022-05)
This SPI interface describes two sets of signals:
• The generic and legacy SPI interface using the 4 signals:
- SPI_MOSI (Master Output Slave Input);
- SPI_MISO (Master Input Slave Output);
- SPI_CLK (clock);
- SPI_NSS signal used for the selection of a Slave Endpoint among N slaves sharing the same bus;
SPI_MISO, SPI_MOSI and SPI_CLK can be shared between several SPI slaves present on the same SPI bus.
• The SPI_INT signal allows the slave to initiate a MAC access request in order to notify the master to start a
data transfer.
SPI_INT is defined as an edge-triggered interrupt. It is asserted on the rising edge of the signal.
SPI_NSS is considered active or asserted at low voltage level.
6.3 Physical interface with 4 signals
Figure 6.2 illustrates the SPI interface using 4 signals, bi-directional SPI_NSS.
MASTER SLAVE
SPI_MISO
SPI_MOSI
SPI_CLK
VDD
R
SS_MI SS_SI
SPI_NSS
SS_MO SS_SO
VSS
VSS

Figure 6.2: SPI electrical interface with 4 signals, bi-directional SPI_NSS
The SPI interface with 4 signals describes two sets of signals:
• The three generic and legacy SPI signals as SPI_MOSI (Master Output Slave Input), SPI_MISO (Master Input
Slave Output) and SPI_CLK (clock). These signals can be shared between several SPI slaves as a bus.
• The SPI_NSS (Negative Slave Select) signal used for the selection of a slave endpoint among N slaves sharing
the same bus and for the slave to initiate a MAC access request to notify the master to initiate a data transfer.
SPI_NSS is considered active or asserted at low voltage level. SPI_NSS requires a bidirectional IO implementing an
Open Drain (OD) interface for both master and slave. This configuration allows driving the SPI_NSS signal to low
voltage level by both master and slave without electrical conflict.
A pull-up resistor keeps SPI_NSS at high state level (i.e. idle state) when SS_MO and SS_SO are not asserted. The
SPI_NSS signal is at low state when either SS_MO or SS_SO are asserted.
NOTE: The current industry de-facto SPI specification defines SPI_NSS signal as unid
...