ISO/IEC 24739-3:2010

Information technology — AT Attachment with Packet Interface - 7 — Part 3: Serial transport protocols and physical interconnect (ATA/ATAPI-7 V3)

ISO/IEC 24739-3:2010(E) specifies the connectors and cables for physical interconnection between host and storage device, the electrical and logical characteristics of the interconnecting signals, and the protocols for the transporting of commands, data, and status over the interface for the serial interface.

Technologies de l'information — Attachement AT avec interface paquet - 7 — Partie 3: Protocoles de transport en série et interconnexion physique (ATA/ATAPI-7 V3)

General Information

• Status: Published
• Publication Date: 25-Mar-2010
• ICS: 35.200 - Interface and interconnection equipment
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Drafting Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: 9093 - International Standard confirmed
• Completion Date: 19-Jun-2015

Standards Content (Sample)

ISO/IEC 24739-3
Edition 1.0 2010-03
INTERNATIONAL
STANDARD


Information technology – AT attachment with packet interface-7 –
Part 3: Serial transport protocols and physical interconnect (ATA/ATAPI-7 V3)


ISO/IEC 24739-3:2010(E)

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THIS PUBLICATION IS COPYRIGHT PROTECTED
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ISO/IEC 24739-3
Edition 1.0 2010-03
INTERNATIONAL
STANDARD


Information technology – AT attachment with packet interface-7 –
Part 3: Serial transport protocols and physical interconnect (ATA/ATAPI-7 V3)


INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XE
ICS 35.200 ISBN 2-8318-1083-6

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CONTENTS
FOREWORD.12
INTRODUCTION.13
1 Scope.14
2 Normative references .14
3 Terms and definitions, abbreviations and conventions .14
3.1 Terms and definitions .14
3.2 Abbreviations .21
3.3 Conventions .22
3.3.1 General .22
3.3.2 Precedence .22
3.3.3 Lists .23
3.3.4 Keywords .23
3.3.5 Numbering.24
3.3.6 Signal conventions .24
3.3.7 Bit conventions .24
3.3.8 State diagram conventions .24
3.3.9 Timing conventions.25
3.3.10 Byte ordering for data transfers .26
4 General operational requirements.28
5 I/O register descriptions .28
6 Command descriptions .28
7 Parallel interface physical and electrical requirements.28
8 Parallel interface signal assignments and descriptions .28
9 Parallel interface general operating requirements of the physical, data link, and
transport layers .28
10 Parallel interface register addressing.28
11 Parallel interface transport protocols .29
12 Parallel interface timing .29
13 Serial interface general overview.29
13.1 Overview .29
13.2 Sub-module operation .30
13.3 Parallel ATA emulation .31
13.3.1 General .31
13.3.2 Software reset .32
13.3.3 Device 0-only emulation .32
13.3.4 Device 0/Device 1 emulation (optional).33
14 Serial interface physical layer.34
14.1 Overview .34
14.1.1 General .34
14.1.2 List of services .34
14.2 Connectors specifications.35
14.2.1 Overview .35
14.2.2 General descriptions.35
14.2.3 Connector drawings.37
14.2.4 Connector pinouts .44

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24739-3 © ISO/IEC:2010(E) – 3 –
14.2.5 Backplane connector configuration and blind-mating tolerance .45
14.2.6 Connector locations.45
14.2.7 Connector conformance requirements .49
14.3 Cable assemblies .55
14.4 Phy (physical layer electronics) .56
14.4.1 Physical plant as a system .56
14.4.2 Bit error rate testing .60
14.4.3 Frame error rate testing.61
14.4.4 Test requirements, non-compliant patterns.62
14.4.5 Test requirements, compliant frame patterns .62
14.4.6 Test requirements, loopback .62
14.4.7 Test Method for Data Rate Frequency Variation, SSC Profile .63
14.4.8 Block diagram .63
14.4.9 Electrical specifications .65
14.4.10 Frame error-rate measurements .68
14.4.11 Receiver Differential voltage .68
14.4.12 Receiver Common-mode voltage.68
14.4.13 Transmitter Differential voltage.68
14.4.14 Transmitter Common-mode voltage.68
14.4.15 Rise/fall times .68
14.5 Electrical features .69
14.5.1 Definitions .69
14.5.2 Differential voltage/timing (EYE) diagram .70
14.5.3 Spread spectrum clocking (SSC) .73
14.5.4 Common-mode biasing .75
14.5.5 Matching .75
14.5.6 Out of band signalling.76
14.6 Elasticity buffer management .94
14.7 BIST (Built in self test) .94
14.7.1 General .94
14.7.2 Loopback testing .94
15 Serial interface Link layer .97
15.1 Overview .97
15.1.1 General .97
15.1.2 Frame transmission .97
15.1.3 Frame receipt .97
15.2 Encoding method .98
15.2.1 General .98
15.2.2 Notation and conventions .98
15.2.3 Character code.99
15.2.4 Transmission summary.106
15.2.5 Reception .107
15.3 Transmission method .108
15.4 Primitives .109
15.4.1 Overview .109
15.4.2 Primitive descriptions .110
15.4.3 Primitive encoding.111
15.4.4 ALIGN primitive .111
15.4.5 CONT primitive.112

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15.4.6 DMAT primitive.113
15.4.7 EOF primitive .114
15.4.8 HOLD/HOLDA primitives .114
15.4.9 PMREQ_P, PMREQ_S, PMACK, and PMNAK primitives . 116
15.4.10 R_ERR primitive.116
15.4.11 R_IP primitive.116
15.4.12 R_OK primitive .116
15.4.13 R_RDY primitive.116
15.4.14 SOF primitive .116
15.4.15 SYNC primitive.116
15.4.16 WTRM primitive.116
15.4.17 X_RDY primitive.116
15.4.18 Examples .116
15.5 CRC calculation .120
15.6 Scrambling .121
15.6.1 Frame content scrambling .121
15.6.2 Repeated primitive suppression.121
15.6.3 Link layer state diagrams.121
16 Serial interface Transport layer.139
16.1 Transport layer overview .139
16.1.1 General .139
16.1.2 FIS construction .139
16.1.3 FIS decomposition.139
16.2 Frame Information Structure (FIS) .139
16.2.1 Overview .139
16.2.2 Payload content .139
16.2.3 FIS types.140
16.2.4 Register, Device to Host.141
16.2.5 Set Device Bits - Device to Host.143
16.2.6 DMA Activate, Device to Host.144
16.2.7 First Party DMA Setup, Device to Host or Host to Device
(bidirectional) .145
16.2.8 BIST Activate, bidirectional .146
16.2.9 PIO Setup, Device to Host.148
16.2.10 Data, Host to Device or Device to Host (bidirectional) . 150
16.3 Host transport states .151
16.3.1 Host transport idle state diagram.151
16.3.2 Host Transport transmit command FIS diagram .153
16.3.3 Host Transport transmit control FIS diagram . 154
16.3.4 Host Transport transmit First Party DMA Setup, Device to Host or
Host to Device FIS state diagram .155
16.3.5 Host Transport transmit BIST Activate FIS . 156
16.3.6 Host Transport decompose Register FIS diagram.157
16.3.7 Host Transport decompose a Set Device Bits FIS state diagram . 158
16.3.8 Host Transport decompose a DMA Activate FIS diagram and DMA
Data Transfer .158
16.3.9 Host Transport decompose a PIO Setup FIS state diagram . 161
16.3.10 Host Transport decompose a First Party DMA Setup FIS state
diagram.164
16.3.11 Host transport decompose a BIST Activate FIS state diagram .165

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24739-3 © ISO/IEC:2010(E) – 5 –
16.4 Device transport states.167
16.4.1 Device transport idle state diagram .167
16.4.2 Device Transport send Register, Device to Host state diagram. 168
16.4.3 Device Transport send Set Device Bits FIS state diagram . 169
16.4.4 Device Transport transmit PIO Setup, Device to Host FIS state
diagram.170
16.4.5 Device Transport transmit DMA Activate FIS state diagram . 170
16.4.6 Device Transport transmit First Party DMA Setup, Device to Host
FIS state diagram.171
16.4.7 Device Transport transmit Data, Device to Host FIS diagram .172
16.4.8 Device Transport transmit BIST Activate FIS diagram . 174
16.4.9 Device Transport decompose Register, Host to Device state
diagram.176
16.4.10 Device Transport decompose Data (Host to Device) FIS state
diagram.177
16.4.11 Device Transport decompose First Party DMA Setup FIS, Host to
Device or Device to Host state diagram.178
16.4.12 Device Transport decompose a BIST Activate FIS state diagram. 179
17 Serial interface Device Command Layer Protocol .180
17.1 COMRESET or SRST sent by Host.180
17.2 Power-on and COMRESET protocol diagram . 180
17.3 Device Idle protocol .182
17.4 Software reset protocol.185
17.5 EXECUTE DEVICE DIAGNOSTIC command protocol . 187
17.6 DEVICE RESET command protocol .188
17.7 Non-data command protocol .188
17.8 PIO data-in command protocol.189
17.9 PIO data-out command protocol.190
17.10 DMA data-in command protocol . 192
17.11 DMA data out command protocol .193
17.12 PACKET protocol.195
17.13 READ DMA QUEUED command protocol. 200
17.14 WRITE DMA QUEUED command protocol .201
18 Host command layer state diagram. 204
18.1 Overview .204
18.2 Device Emulation of nIEN with Interrupt Pending.207
19 Serial interface host adapter register interface .208
19.1 Overview .208
19.2 SStatus, SError and SControl registers .209
19.2.1 General .209
19.2.2 SStatus register.209
19.2.3 SError register.210
19.2.4 SControl register .211
20 Serial interface error handling .212
20.1 Architecture.212
20.2 Phy error handling overview .213
20.2.1 Error detection.213
20.2.2 Error control actions .214
20.2.3 Error reporting .214

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20.3 Link error handling overview.214
20.3.1 Error detection.214
20.3.2 Error control actions .215
20.3.3 Error reporting .216
20.4 Transport error handling. 216
20.4.1 Overview .216
20.4.2 Error detection.216
20.4.3 Error control actions .217
20.4.4 Error reporting .218
20.5 Software error handling overview .218
20.5.1 General .218
20.5.2 Error detection.218
20.5.3 Error control actions .219
Annex A (informative) Command Set summary .220
Annex B (informative) Design and programming considerations for large physical
sector devices.220
Annex C (informative) Device determination of cable type.220
Annex D (informative) Signal integrity and UDMA guide.220
Annex E (informative) Register selection address summary . 220
Annex F (informative) SAMPLE code for Serial CRC Scrambling .221
F.1 CRC calculation.221
F.1.1 Overview .221
F.1.2 Maximum frame size .221
F.1.3 Example code for CRC algorithm. 221
F.1.4 Example CRC implementation output . 224
F.2 Scrambling calculation.224
F.2.1 Overview .224
F.2.2 Example code for scrambling algorithm . 224
F.2.3 Example scrambler implementation .227
F.3 Example frame .228
Annex G (ínformative) FIS Type field value selection .229
G.1 Overview .229
G.2 Type field values .229
Annex H (informative) Physical Layer implementation examples . 230
H.1 Cable construction example.230
H.2 Contact material and plating .231
H.3 Relationship of frequency to the jitter specification .231
H.4 Sampling BER and jitter formulas .232
H.5 DC and AC coupled transmitter examples.233
H.6 OOB signal and squelch detector examples. 235
Annex I (informative) Command Processing example. 238
I.1 Non-data commands.238
I.1.1 General .238
I.1.2 Legacy DMA read by host from device.238
I.1.3 Legacy DMA write by host to device .238
I.1.4 PIO data read from the device
...