ISO/IEC 14776-115:2004
(Main)Information technology — Small Computer System Interface (SCSI) — Part 115: Parallel Interface-5 (SPI-5)
Information technology — Small Computer System Interface (SCSI) — Part 115: Parallel Interface-5 (SPI-5)
The SCSI parallel interface (SPI) is designed to provide an efficient peer-to-peer I/O bus with the maximum number of hosts and peripherals determined by the bus width (i.e., 8 or 16). Data may be transferred asynchronously or synchronously at rates that depend on implementation. The objectives of the SCSI parallel interface are: a) To provide host computers with device independence within a class of devices. Thus, different disk drives, tape drives, printers, optical media drives, and other SCSI devices may be added to the host computers without requiring modifications to generic system hardware. b) To provide compatibility such that conforming SPI-2, SPI-3 devices may interoperate with SPI-5 devices given that the systems engineering is correctly done. The interface protocol includes provision for the connection of multiple SCSI initiator ports (i.e., SCSI devices capable of initiating an I/O process) and multiple SCSI target ports (i.e., SCSI devices capable of responding to a request to perform an I/O process). This international standard defines mechanical, electrical, timing requirements, command, and the task management delivery protocol requirements to transfer commands and data between SCSI devices attached to an SCSI parallel interface, i.e. to allow conforming SCSI devices to interoperate. It is intended to be used in conjunction with the SCSI command sets. The resulting interface facilitates the interconnection of computers and intelligent peripherals and thus provides a common interface standard for both system integrators and suppliers of intelligent peripherals. This standard is a functional description. Conforming implementations may employ any design technique that does not violate interoperability. This standard has made obsolete single-ended and multimode signalling alternatives. Implementations that use single-ended or multimode signalling alternatives should reference the SCSI Parallel Interface-2 standard (ISO/IEC 14776-112).
Technologies de l'information — Interface de petit système d'ordinateur (SCSI) — Partie 115: Interface parallèle 5 (SPI-5)
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Standards Content (Sample)
INTERNATIONAL ISO/IEC
STANDARD 14776-115
First edition
2004-11
Information technology –
Small computer system interface (SCSI) –
Part 115:
Parallel Interface-5 (SPI-5)
Reference number
ISO/IEC 14776-115:2004(E)
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INTERNATIONAL ISO/IEC
STANDARD 14776-115
First edition
2004-11
Information technology –
Small computer system interface (SCSI) –
Part 115:
Parallel Interface-5 (SPI-5)
© ISO/IEC 2004
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.
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ISO/IEC © 14776-115 3
14776-115 © ISO/IEC:2004(E) 3
Contents
Page
Foreword .19
Introduction.20
1 Scope .21
2 Normative references .22
2.1 Normative references .22
2.2 Approved references .22
2.3 References under development .23
2.4 Other references .23
3 Definitions, symbols, abbreviations, and conventions .23
3.1 Definitions .23
3.2 Symbols and abbreviations .32
3.3 Keywords .33
3.4 Conventions .34
3.5 Notation for Procedures and Functions .35
4 SCSI parallel interface model .36
4.1 SCSI parallel interface model overview .36
4.2 Cables, connectors, signals, transceivers .36
4.3 Physical architecture of bus segment .36
4.4 Driver-receiver connections .37
4.5 Physical topology details and definitions .37
4.6 Bus segment loading .39
4.7 Termination requirements .39
4.8 SCSI device Addressing .39
4.9 Clocking methods for data transfers .40
4.10 Paced transfer on a SCSI bus .42
4.11 Data transfers .44
4.11.1 Data transfer modes .44
4.11.1.1 Asynchronous transfers .44
4.11.1.2 Synchronous transfers .44
4.11.1.3 Paced transfers .44
4.11.2 ST DATA phase parallel transfers .44
4.11.3 DT DATA phase parallel transfers .45
4.11.3.1 DT DATA phase parallel transfers format .45
4.11.3.2 Data group transfers .45
4.11.3.3 Information unit transfers .45
4.12 Negotiation .46
4.12.1 Negotiation introduction .46
4.12.2 Negotiation algorithm .46
4.12.3 When to negotiate .47
4.12.4 Negotiable fields .48
4.12.4.1 Negotiable fields introduction .48
4.12.4.2 Transfer agreements .49
4.12.4.3 Transfer period factor .49
4.12.4.4 REQ/ACK offset .51
4.12.4.5 Transfer width exponent .52
4.12.4.6 Protocol options .52
4.12.4.6.1 Protocol options introduction .52
4.12.4.6.2 IU_REQ .53
4.12.4.6.3 DT_REQ .54
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4.12.4.6.4 QAS_REQ .54
4.12.4.6.5 HOLD_MCS .54
4.12.4.6.6 WR_FLOW .55
4.12.4.6.7 RD_STRM .55
4.12.4.6.8 RTI .55
4.12.4.6.9 PCOMP_EN .55
4.12.5 Negotiable field combinations .56
4.12.6 Message restrictions .57
4.12.7 Negotiation message sequences .58
4.12.7.1 Negotiation message sequences overview .58
4.12.7.2 SCSI initiator port originated PPR negotiation .59
4.12.7.3 SCSI initiator port originated WDTR negotiation .60
4.12.7.4 SCSI initiator port originated SDTR negotiation .62
4.12.7.5 SCSI target port originated WDTR negotiation .64
4.12.7.6 SCSI target port originated SDTR negotiation .67
4.13 Protocol .68
5 SCSI parallel interface connectors .71
5.1 SCSI parallel interface connectors overview .71
5.2 Non-shielded connector .71
5.2.1 Non-shielded connector alternative 1 - A cable .71
5.2.2 Non-shielded connector alternative 2 - A cable .71
5.2.3 Non-shielded connector alternative 3 - P cable .72
5.2.4 Non-shielded connector alternative 4 .72
5.3 Shielded connector .78
5.3.1 Shielded connector overview .78
5.3.2 Shielded connector alternative 1 - A cable .78
5.3.3 Shielded connector alternative 2 - A cable .78
5.3.4 Shielded connector alternative 3 - P cable .78
5.3.5 Shielded connector alternative 4 - P cable .78
5.4 Connector contact assignments .86
5.4.1 Connector contact assignments overview .86
5.4.2 Differential connector contact assignments .87
6 SCSI bus segment interconnect .90
6.1 SCSI bus segment interconnect overview .90
6.2 SCSI bus segment cables .90
6.3 Interconnect characteristics for signals .91
6.3.1 SCSI bulk cable .91
6.3.2 Minimum conductor size for signals .92
6.3.3 Local transmission line impedance .92
6.3.4 Extended distance transmission line impedance .92
6.3.5 Capacitance .92
6.3.6 Differential propagation time and propagation time skew .92
6.3.7 Differential attenuation .92
6.3.8 Crosstalk .93
6.4 Decoupling characteristics for TERMPWR lines .93
6.5 Connection requirements for RESERVED lines .94
6.6 Cables used with LVD transceivers .94
6.7 LVD stub length and spacing .95
7 SCSI parallel interface electrical characteristics .96
7.1 SCSI parallel interface electrical characteristics overview .96
7.2 LVD termination .96
7.2.1 LVD termination overview .96
7.2.2 LVD driver characteristics .101
7.2.3 LVD receiver characteristics .104
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7.2.4 LVD capacitive loads .105
7.2.4.1 Management of LVD release glitches .107
7.2.5 SE/HVD transmission mode detection .109
7.2.5.1 SE/HVD transmission mode detection overview .109
7.2.5.2 LVD DIFFSENS driver .109
7.2.5.3 LVD DIFFSENS receiver .110
7.3 Terminator power .112
8 SCSI bus signals .114
8.1 SCSI bus signals overview .114
8.2 Signal descriptions .114
8.3 LVD Signal states .117
8.4 OR-tied signals .118
8.5 Signal sources .118
9 SCSI parallel bus timing .120
9.1 SCSI parallel bus timing values .120
9.2 Timing description .126
9.2.1 Arbitration delay .126
9.2.2 ATN transmit setup time .127
9.2.3 ATN receive setup time .127
9.2.4 Bus clear delay .127
9.2.5 Bus free delay .127
9.2.6 Bus set delay .127
9.2.7 Bus settle delay .128
9.2.8 Cable skew .128
9.2.9 Chip noise in receiver .128
9.2.10 Clock jitter .128
9.2.11 Crosstalk time shift .128
9.2.12 Flow control receive hold time .128
9.2.13 Flow control receive setup time .128
9.2.14 Flow control transmit hold time .128
9.2.15 Flow control transmit setup time .128
9.2.16 Offset induced time asymmetry .129
9.2.17 pCRC receive hold time .129
9.2.18 pCRC receive setup time .129
9.2.19 pCRC transmit hold time .129
9.2.20 pCRC transmit setup time .129
9.2.21 Data release delay .129
9.2.22 DIFFSENS voltage filter time .129
9.2.23 Physical disconnection delay .129
9.2.24 Power on to selection .129
9.2.25 QAS arbitration delay .130
9.2.26 QAS assertion delay .130
9.2.27 QAS release delay .130
9.2.28 QAS non-DATA phase REQ(ACK) period .130
9.2.29 Receive assertion period .130
9.2.30 Receive hold time .130
9.2.31 Receive internal hold time .130
9.2.32 Receive internal setup time .130
9.2.33 Receive negation period .131
9.2.34 Receive setup time .131
9.2.35 Receive REQ(ACK) period tolerance .131
9.2.36 Receive REQ assertion period with P_CRCA transitioning .131
9.2.37 Receive REQ negation period with P_CRCA transitioning .131
9.2.38 Receive Skew Compensation .131
9.2.39 Receiver amplitude time skew .131
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9.2.40 Receiver de-skewed data valid window .131
9.2.41 REQ(ACK) period .132
9.2.42 Reset delay .132
9.2.43 Reset hold time .132
9.2.44 Reset to selection .132
9.2.45 Residual skew error .133
9.2.46 Selection abort time .133
9.2.47 Selection time-out delay .133
9.2.48 Signal timing skew .133
9.2.49 Skew correction range .133
9.2.50 Strobe offset tolerance .134
9.2.51 System deskew delay .134
9.2.52 System noise at launch .134
9.2.53 System noise at receiver .134
9.2.54 Time asymmetry .134
9.2.55 Transmit assertion period .134
9.2.56 Transmit hold time .135
9.2.57 Transmit ISI Compensation .135
9.2.58 Transmit negation period .135
9.2.59 Transmit setup time .135
9.2.60 Transmit REQ(ACK) period tolerance .135
9.2.61 Transmit REQ assertion period with P_CRCA transitioning .135
9.2.62 Transmit REQ negation period with P_CRCA transitioning .135
9.2.63 Transmitter skew .135
9.2.64 Transmitter time asymmetry .136
9.3 Measurement points .136
9.3.1 Measurement points overview .136
9.3.2 LVD measurement points .137
9.4 Receiver Masks .139
9.4.1 Synchronous transfers and for fast-160 paced transfer clocking signals .139
9.4.2 Paced transfers with precompensation enabled on fast-160 .140
9.4.3 Paced transfers with precompensation disabled on fast-160 and fast-320 .142
9.5 Timing parameters .148
9.6 Setup and hold timings .148
9.6.1 ST data transfer calculations .148
9.6.2 DT data transfer calculations .149
10 SCSI bus phases .151
10.1 SCSI bus phases overview .151
10.2 BUS FREE phase .151
10.3 Expected and unexpected bus free phases .151
10.4 Arbitration .152
10.4.1 Arbitration and QAS overview .152
10.4.2 NORMAL ARBITRATION phase .152
10.4.3 QAS protocol .153
10.4.4 QAS phase .154
10.5 SELECTION phase .155
10.5.1 Selection Overview .155
10.5.2 Selection using attention condition .15
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